sdc added. must rework for timing again... all clocks must be aligned on the risigg...

[motonesfpga/motonesfpga.git] / de1_nes / simulation / modelsim / de1_nes_run_msim_gate_vhdl.do

diff --git a/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do b/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do
index 76fc1d3..a6f0f83 100644 (file)
--- a/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do
+++ b/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do
@@ -65,7 +65,7 @@ add wave -label ppu_data -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu
 \r
 \r
 add wave -divider vga_pos\r
-add wave -label emu_ppu_clk     sim:/testbench_motones_sim/sim_board/dbg_exec_cycle(3)\r
+add wave -label emu_ppu_clk     sim:/testbench_motones_sim/sim_board/dbg_emu_ppu_clk\r
 add wave -label nes_x           -radix decimal -unsigned  {sim:/testbench_motones_sim/sim_board/dbg_exec_cycle(0) & \r
                                                            sim:/testbench_motones_sim/sim_board/dbg_instruction(7 downto 0)}\r
 add wave -label nes_y           -radix decimal -unsigned  {sim:/testbench_motones_sim/sim_board/dbg_exec_cycle(4) & \r