/*\r
FreeRTOS V7.0.0 - Copyright (C) 2011 Real Time Engineers Ltd.\r
- \r
+\r
\r
***************************************************************************\r
* *\r
\r
/* Kernel includes. */\r
#include "EtherDev_DP83848C_protected.h"\r
-#include "../os/NyLPC_cThread.h"\r
+#include "LPC17xx.h"\r
+#include "NyLPC_os.h"\r
+\r
\r
#define DP83848C_ID 0x20005C90 /* PHY Identifier */\r
\r
#define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */\r
#define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */\r
#define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */\r
-#define PHY_AUTO_NEG_COMPLETE 0x0020 /* Auto negotiation have finished. */\r
+#define PHY_AUTO_NEG_COMPLETE 0x0020 /* Auto negotiation have finished. */\r
#define ETHDEV_PHY_DEF_ADR 0x0100 /* Default PHY device address */\r
\r
\r
#ifndef configEMAC_INTERRUPT_PRIORITY\r
- #define configEMAC_INTERRUPT_PRIORITY 5\r
+ #define configEMAC_INTERRUPT_PRIORITY 5\r
#endif\r
\r
/* Time to wait between each inspection of the link status. */\r
#define emacWAIT_FOR_LINK_TO_ESTABLISH_MS 500\r
\r
/* Short delay used in several places during the initialisation process. */\r
-#define emacSHORT_DELAY_MS 2\r
+#define emacSHORT_DELAY_MS 10\r
\r
/* Hardware specific bit definitions. */\r
-#define emacPINSEL2_VALUE ( 0x50150105 )\r
+#define emacPINSEL2_VALUE ( 0x50150105 )\r
\r
/* If no buffers are available, then wait this long before looking again.... */\r
#define emacBUFFER_WAIT_DELAY_MS 3\r
#define emacBUFFER_WAIT_EMPTY_MS 10\r
\r
/* ...and don't look more than this many times. */\r
-#define emacBUFFER_WAIT_ATTEMPTS ( 30 )\r
+#define emacBUFFER_WAIT_ATTEMPTS ( 30 )\r
\r
/* Index to the Tx descriptor that is always used first for every Tx. The second\r
descriptor is then used to re-send in order to speed up the uIP Tx process. */\r
-#define emacTX_DESC_INDEX ( 0 )\r
+#define emacTX_DESC_INDEX ( 0 )\r
\r
/*-----------------------------------------------------------*/\r
\r
\r
const static struct TiEthernetDevice _interface=\r
{\r
- "DP83848C",\r
- start,\r
- stop,\r
- EthDev_LPC17xx_getRxEthFrame,\r
- EthDev_LPC17xx_nextRxEthFrame,\r
- EthDev_LPC17xx_allocTxBuf,\r
- EthDev_LPC17xx_releaseTxBuf,\r
- EthDev_LPC17xx_sendTxEthFrame,\r
- EthDev_LPC17xx_processTx};\r
+ "DP83848C",\r
+ start,\r
+ stop,\r
+ EthDev_LPC17xx_getRxEthFrame,\r
+ EthDev_LPC17xx_nextRxEthFrame,\r
+ EthDev_LPC17xx_allocTxBuf,\r
+ EthDev_LPC17xx_releaseTxBuf,\r
+ EthDev_LPC17xx_sendTxEthFrame,\r
+ EthDev_LPC17xx_processTx};\r
/*\r
* EthernetDeviceのファクトリー関数\r
*/\r
\r
NyLPC_TBool EthDev_DP83848C_getInterface(\r
- const struct TiEthernetDevice** o_dev)\r
+ const struct TiEthernetDevice** o_dev)\r
{\r
- unsigned long ulID1, ulID2;\r
- NyLPC_TBool lReturn = NyLPC_TBool_TRUE;\r
- //Reset MCU Interface. and wait for reset.\r
- prvSetupEMACHardware();\r
- //Check peripheral name\r
- ulID1 = prvReadPHY( PHY_REG_IDR1, &lReturn );\r
- ulID2 = prvReadPHY( PHY_REG_IDR2, &lReturn );\r
- if( ( (ulID1 << 16UL ) | ( ulID2 & 0xFFF0UL ) ) != DP83848C_ID)\r
- {\r
- return NyLPC_TBool_FALSE;\r
- }\r
- *o_dev=&_interface;\r
- return NyLPC_TBool_TRUE;\r
+ unsigned long ulID1, ulID2;\r
+ NyLPC_TBool lReturn = NyLPC_TBool_TRUE;\r
+ //Reset MCU Interface. and wait for reset.\r
+ prvSetupEMACHardware();\r
+ //Check peripheral name\r
+ ulID1 = prvReadPHY( PHY_REG_IDR1, &lReturn );\r
+ ulID2 = prvReadPHY( PHY_REG_IDR2, &lReturn );\r
+ if( ( (ulID1 << 16UL ) | ( ulID2 & 0xFFF0UL ) ) != DP83848C_ID)\r
+ {\r
+ return NyLPC_TBool_FALSE;\r
+ }\r
+ *o_dev=&_interface;\r
+ LPC_EMAC->TxProduceIndex = 0;\r
+ LPC_EMAC->RxConsumeIndex = 0;\r
+ return NyLPC_TBool_TRUE;\r
}\r
\r
\r
static NyLPC_TBool start(const struct NyLPC_TEthAddr* i_eth_addr)\r
{\r
- /* Set the Ethernet MAC Address registers */\r
- LPC_EMAC->SA0 = (((uint32_t)(i_eth_addr->addr[0])) << 8 ) | i_eth_addr->addr[1];\r
- LPC_EMAC->SA1 = (((uint32_t)(i_eth_addr->addr[2])) << 8 ) | i_eth_addr->addr[3];\r
- LPC_EMAC->SA2 = (((uint32_t)(i_eth_addr->addr[4])) << 8 ) | i_eth_addr->addr[5];\r
+ /* Set the Ethernet MAC Address registers */\r
+ LPC_EMAC->SA0 = (((uint32_t)(i_eth_addr->addr[0])) << 8 ) | i_eth_addr->addr[1];\r
+ LPC_EMAC->SA1 = (((uint32_t)(i_eth_addr->addr[2])) << 8 ) | i_eth_addr->addr[3];\r
+ LPC_EMAC->SA2 = (((uint32_t)(i_eth_addr->addr[4])) << 8 ) | i_eth_addr->addr[5];\r
\r
- /* Initialize Tx and Rx DMA Descriptors */\r
- EthDev_LPC17xx_prevRxDescriptor();\r
- EthDev_LPC17xx_prevTxDescriptor();\r
+ /* Initialize Tx and Rx DMA Descriptors */\r
+ EthDev_LPC17xx_prevRxDescriptor();\r
+ EthDev_LPC17xx_prevTxDescriptor();\r
\r
- /* Receive broadcast and perfect match packets */\r
- LPC_EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;\r
\r
- /* Setup the PHY. */\r
- prvConfigurePHY();\r
+ /* Setup the PHY. */\r
+ prvConfigurePHY();\r
\r
- //wait for Link up...\r
- while(!prvSetupLinkStatus())\r
- {\r
- NyLPC_cThread_sleep(100);\r
- }\r
+ //wait for Link up...\r
+ while(!prvSetupLinkStatus())\r
+ {\r
+ NyLPC_cThread_sleep(100);\r
+ }\r
\r
- /* Receive Broadcast and Perfect Match Packets */\r
- LPC_EMAC->RxFilterCtrl = RFC_BCAST_EN | RFC_PERFECT_EN;\r
+ /* Receive Broadcast and Perfect Match Packets */\r
+ LPC_EMAC->RxFilterCtrl = RFC_BCAST_EN | RFC_PERFECT_EN | RFC_MCAST_EN;\r
\r
- /* Reset all interrupts */\r
- LPC_EMAC->IntClear = 0xffff;\r
+ //Ethernetの割込み開始設定\r
+ NyLPC_cIsr_enterCritical();\r
+ {\r
+ /* Reset all interrupts */\r
+ LPC_EMAC->IntClear = 0xffff;\r
+ LPC_EMAC->IntEnable = ( INT_RX_DONE | INT_TX_DONE );\r
\r
- /* Enable receive and transmit mode of MAC Ethernet core */\r
- LPC_EMAC->Command |= ( CR_RX_EN | CR_TX_EN );\r
- LPC_EMAC->MAC1 |= MAC1_REC_EN;\r
+ /* Enable receive and transmit mode of MAC Ethernet core */\r
+ LPC_EMAC->Command |= ( CR_RX_EN | CR_TX_EN );\r
+ LPC_EMAC->MAC1 |= MAC1_REC_EN;\r
\r
- //Ethernetの割込み開始設定\r
- NyLPC_cIsr_enterCritical();\r
- {\r
- LPC_EMAC->IntEnable = ( INT_RX_DONE | INT_TX_DONE );\r
- /* Set the interrupt priority to the max permissible to cause some\r
- interrupt nesting. */\r
- NVIC_SetPriority( ENET_IRQn, configEMAC_INTERRUPT_PRIORITY );\r
+ /* Set the interrupt priority to the max permissible to cause some\r
+ interrupt nesting. */\r
+ NVIC_SetPriority( ENET_IRQn, configEMAC_INTERRUPT_PRIORITY );\r
\r
- /* Enable the interrupt. */\r
- NVIC_EnableIRQ( ENET_IRQn );\r
- }\r
- NyLPC_cIsr_exitCritical();\r
+ /* Enable the interrupt. */\r
+ NVIC_EnableIRQ( ENET_IRQn );\r
+ }\r
+ NyLPC_cIsr_exitCritical();\r
\r
- return NyLPC_TBool_TRUE;\r
+ return NyLPC_TBool_TRUE;\r
\r
}\r
static void stop(void)\r
{\r
- NyLPC_cIsr_enterCritical();\r
- {\r
- LPC_EMAC->IntEnable = (~(INT_RX_DONE|INT_TX_DONE))&LPC_EMAC->IntEnable;\r
- NVIC_DisableIRQ( ENET_IRQn );\r
- }\r
- NyLPC_cIsr_exitCritical();\r
- return;\r
+ NyLPC_cIsr_enterCritical();\r
+ {\r
+ LPC_EMAC->IntEnable = (~(INT_RX_DONE|INT_TX_DONE))&LPC_EMAC->IntEnable;\r
+ NVIC_DisableIRQ( ENET_IRQn );\r
+ }\r
+ NyLPC_cIsr_exitCritical();\r
+ LPC_EMAC->Command &= ~( CR_RX_EN | CR_TX_EN );\r
+ LPC_EMAC->MAC1 &= ~MAC1_REC_EN;\r
+ return;\r
}\r
\r
\r
\r
static void prvSetupEMACHardware( void )\r
{\r
- unsigned short us;\r
- long x;\r
- NyLPC_TBool lDummy;\r
-\r
- /* Power Up the EMAC controller. */\r
- LPC_SC->PCONP |= 0x40000000;\r
- NyLPC_cThread_sleep( emacSHORT_DELAY_MS);\r
-\r
- /* Enable P1 Ethernet Pins. */\r
- LPC_PINCON->PINSEL2 = emacPINSEL2_VALUE;\r
- LPC_PINCON->PINSEL3 = ( LPC_PINCON->PINSEL3 & ~0x0000000F ) | 0x00000005;\r
-\r
- /* Reset all EMAC internal modules. */\r
- LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;\r
- LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES| CR_PASS_RUNT_FRM;\r
- /* A short delay after reset. */\r
- NyLPC_cThread_sleep( emacSHORT_DELAY_MS );\r
-\r
- /* Initialize MAC control registers. */\r
- LPC_EMAC->MAC1 = MAC1_PASS_ALL;\r
- LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;\r
- LPC_EMAC->MAXF = ETH_MAX_FLEN;\r
- LPC_EMAC->CLRT = CLRT_DEF;\r
- LPC_EMAC->IPGR = IPGR_DEF;\r
-\r
- /*PCLK=18MHz, clock select=6, MDC=18/6=3MHz */ // I don't think so!\r
- /* Enable Reduced MII interface. */\r
- LPC_EMAC->MCFG = MCFG_CLK_DIV20 | MCFG_RES_MII;\r
- NyLPC_cThread_sleep( emacSHORT_DELAY_MS );\r
- LPC_EMAC->MCFG = MCFG_CLK_DIV20;\r
-\r
- /* Enable Reduced MII interface. */\r
- LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM | CR_PASS_RX_FILT;\r
-\r
- /* Reset Reduced MII Logic. */\r
- LPC_EMAC->SUPP = SUPP_RES_RMII | SUPP_SPEED;\r
- NyLPC_cThread_sleep( emacSHORT_DELAY_MS );\r
- LPC_EMAC->SUPP = SUPP_SPEED;\r
-\r
- /* Put the PHY in reset mode */\r
- prvWritePHY( PHY_REG_BMCR, MCFG_RES_MII );\r
- NyLPC_cThread_sleep( emacSHORT_DELAY_MS * 5);\r
-\r
- /* Wait for hardware reset to end. */\r
- for( x = 0; x < 100; x++ )\r
- {\r
- NyLPC_cThread_sleep( emacSHORT_DELAY_MS * 5 );\r
- us = prvReadPHY( PHY_REG_BMCR, &lDummy );\r
- if( !( us & MCFG_RES_MII ) )\r
- {\r
- /* Reset complete */\r
- break;\r
- }\r
- }\r
+ unsigned short us;\r
+ long x;\r
+ NyLPC_TBool lDummy;\r
+\r
+ /* Power Up the EMAC controller. */\r
+ LPC_SC->PCONP |= 0x40000000;\r
+ NyLPC_cThread_sleep( emacSHORT_DELAY_MS);\r
+\r
+ /* Enable P1 Ethernet Pins. */\r
+ LPC_PINCON->PINSEL2 = emacPINSEL2_VALUE;\r
+ LPC_PINCON->PINSEL3 = ( LPC_PINCON->PINSEL3 & ~0x0000000F ) | 0x00000005;\r
+\r
+ /* Reset all EMAC internal modules. */\r
+ LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;\r
+ LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES| CR_PASS_RUNT_FRM;\r
+ /* A short delay after reset. */\r
+ NyLPC_cThread_sleep( emacSHORT_DELAY_MS );\r
+\r
+ /* Initialize MAC control registers. */\r
+ LPC_EMAC->MAC1 = MAC1_PASS_ALL;\r
+ LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN | MAC2_VLAN_PAD_EN;\r
+ LPC_EMAC->MAXF = ETH_MAX_FLEN;\r
+ LPC_EMAC->CLRT = CLRT_DEF;\r
+ LPC_EMAC->IPGR = IPGR_DEF;\r
+\r
+ /*PCLK=18MHz, clock select=6, MDC=18/6=3MHz */ // I don't think so!\r
+ /* Enable Reduced MII interface. */\r
+ LPC_EMAC->MCFG = MCFG_CLK_DIV20 | MCFG_RES_MII;\r
+ NyLPC_cThread_sleep( emacSHORT_DELAY_MS );\r
+ LPC_EMAC->MCFG = MCFG_CLK_DIV20;\r
+\r
+ /* Enable Reduced MII interface. */\r
+ LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM | CR_PASS_RX_FILT;\r
+\r
+ /* Reset Reduced MII Logic. */\r
+ LPC_EMAC->SUPP = SUPP_RES_RMII | SUPP_SPEED;\r
+ NyLPC_cThread_sleep( emacSHORT_DELAY_MS );\r
+ LPC_EMAC->SUPP = SUPP_SPEED;\r
+\r
+ /* Put the PHY in reset mode */\r
+ prvWritePHY( PHY_REG_BMCR, MCFG_RES_MII );\r
+ NyLPC_cThread_sleep( emacSHORT_DELAY_MS * 5);\r
+\r
+ /* Wait for hardware reset to end. */\r
+ for( x = 0; x < 100; x++ )\r
+ {\r
+ NyLPC_cThread_sleep( emacSHORT_DELAY_MS * 5 );\r
+ us = prvReadPHY( PHY_REG_BMCR, &lDummy );\r
+ if( !( us & MCFG_RES_MII ) )\r
+ {\r
+ /* Reset complete */\r
+ break;\r
+ }\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
\r
static NyLPC_TBool prvWritePHY( long lPhyReg, long lValue )\r
{\r
- const long lMaxTime = 10;\r
- long x;\r
-\r
- LPC_EMAC->MCMD = 0;\r
- LPC_EMAC->MADR = ETHDEV_PHY_DEF_ADR | lPhyReg;\r
- LPC_EMAC->MWTD = lValue;\r
-\r
- for( x = 0; x < lMaxTime; x++ )\r
- {\r
- if( ( LPC_EMAC->MIND & MIND_BUSY ) == 0 )\r
- {\r
- /* Operation has finished. */\r
- break;\r
- }\r
-\r
- NyLPC_cThread_sleep( emacSHORT_DELAY_MS );\r
- }\r
-\r
- if( x < lMaxTime )\r
- {\r
- return NyLPC_TBool_TRUE;\r
- }\r
- else\r
- {\r
- return NyLPC_TBool_FALSE;\r
- }\r
+ const long lMaxTime = 10;\r
+ long x;\r
+\r
+ LPC_EMAC->MCMD = 0;\r
+ LPC_EMAC->MADR = ETHDEV_PHY_DEF_ADR | lPhyReg;\r
+ LPC_EMAC->MWTD = lValue;\r
+\r
+ for( x = 0; x < lMaxTime; x++ )\r
+ {\r
+ if( ( LPC_EMAC->MIND & MIND_BUSY ) == 0 )\r
+ {\r
+ /* Operation has finished. */\r
+ break;\r
+ }\r
+\r
+ NyLPC_cThread_sleep( emacSHORT_DELAY_MS );\r
+ }\r
+\r
+ if( x < lMaxTime )\r
+ {\r
+ return NyLPC_TBool_TRUE;\r
+ }\r
+ else\r
+ {\r
+ return NyLPC_TBool_FALSE;\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
static unsigned short prvReadPHY( unsigned int ucPhyReg, NyLPC_TBool* plStatus )\r
{\r
- long x;\r
- const long lMaxTime = 10;\r
-\r
- LPC_EMAC->MCMD = 1;\r
- LPC_EMAC->MADR = ETHDEV_PHY_DEF_ADR | ucPhyReg;\r
- LPC_EMAC->MCMD = MCMD_READ;\r
-\r
- for( x = 0; x < lMaxTime; x++ )\r
- {\r
- /* Operation has finished. */\r
- if( ( LPC_EMAC->MIND & MIND_BUSY ) == 0 )\r
- {\r
- break;\r
- }\r
- NyLPC_cThread_sleep( emacSHORT_DELAY_MS );\r
- }\r
-\r
- LPC_EMAC->MCMD = 0;\r
-\r
- if( x >= lMaxTime )\r
- {\r
- *plStatus = NyLPC_TBool_FALSE;\r
- }\r
-\r
- return( LPC_EMAC->MRDD );\r
+ long x;\r
+ const long lMaxTime = 10;\r
+\r
+ LPC_EMAC->MCMD = 1;\r
+ LPC_EMAC->MADR = ETHDEV_PHY_DEF_ADR | ucPhyReg;\r
+ LPC_EMAC->MCMD = MCMD_READ;\r
+\r
+ for( x = 0; x < lMaxTime; x++ )\r
+ {\r
+ /* Operation has finished. */\r
+ if( ( LPC_EMAC->MIND & MIND_BUSY ) == 0 )\r
+ {\r
+ break;\r
+ }\r
+ NyLPC_cThread_sleep( emacSHORT_DELAY_MS );\r
+ }\r
+\r
+ LPC_EMAC->MCMD = 0;\r
+\r
+ if( x >= lMaxTime )\r
+ {\r
+ *plStatus = NyLPC_TBool_FALSE;\r
+ }\r
+\r
+ return( LPC_EMAC->MRDD );\r
}\r
/*------------------------------------------------\r
* Private function depend on device.\r
- * デバイス依存部分
+ * デバイス依存部分\r
------------------------------------------------*/\r
\r
\r
/*for mbed\r
*/\r
-#define emacLINK_ESTABLISHED ( 0x0001 )\r
-#define emacFULL_DUPLEX_ENABLED ( 0x0004 )\r
-#define emac10BASE_T_MODE ( 0x0002 )\r
+#define emacLINK_ESTABLISHED ( 0x0001 )\r
+#define emacFULL_DUPLEX_ENABLED ( 0x0004 )\r
+#define emac10BASE_T_MODE ( 0x0002 )\r
\r
\r
static void prvConfigurePHY( void )\r
{\r
- unsigned short us;\r
- long x;\r
- NyLPC_TBool lDummy;\r
-\r
- /* Auto negotiate the configuration. */\r
- if( prvWritePHY( PHY_REG_BMCR, PHY_AUTO_NEG ) )\r
- {\r
- NyLPC_cThread_sleep( emacSHORT_DELAY_MS * 5 );\r
-\r
- for( x = 0; x < 10; x++ )\r
- {\r
- us = prvReadPHY( PHY_REG_BMSR, &lDummy );\r
-\r
- if( us & PHY_AUTO_NEG_COMPLETE )\r
- {\r
- break;\r
- }\r
-\r
- NyLPC_cThread_sleep( emacWAIT_FOR_LINK_TO_ESTABLISH_MS);\r
- }\r
- }\r
+ unsigned short us;\r
+ long x;\r
+ NyLPC_TBool lDummy;\r
+\r
+ /* Auto negotiate the configuration. */\r
+ if( prvWritePHY( PHY_REG_BMCR, PHY_AUTO_NEG ) )\r
+ {\r
+ NyLPC_cThread_sleep( emacSHORT_DELAY_MS * 5 );\r
+\r
+ for( x = 0; x < 10; x++ )\r
+ {\r
+ us = prvReadPHY( PHY_REG_BMSR, &lDummy );\r
+\r
+ if( us & PHY_AUTO_NEG_COMPLETE )\r
+ {\r
+ break;\r
+ }\r
+\r
+ NyLPC_cThread_sleep( emacWAIT_FOR_LINK_TO_ESTABLISH_MS);\r
+ }\r
+ }\r
}\r
\r
static NyLPC_TBool prvSetupLinkStatus( void )\r
{\r
- NyLPC_TBool lReturn = NyLPC_TBool_FALSE;\r
- long x;\r
- unsigned short usLinkStatus;\r
-\r
- /* Wait with timeout for the link to be established. */\r
- for( x = 0; x < 10; x++ )\r
- {\r
- usLinkStatus = prvReadPHY( PHY_REG_STS, &lReturn );\r
- if( usLinkStatus & emacLINK_ESTABLISHED )\r
- {\r
- /* Link is established. */\r
- lReturn = NyLPC_TBool_TRUE;\r
- break;\r
- }\r
-\r
- NyLPC_cThread_sleep( emacWAIT_FOR_LINK_TO_ESTABLISH_MS);\r
- }\r
-\r
- if( lReturn == NyLPC_TBool_TRUE )\r
- {\r
- /* Configure Full/Half Duplex mode. */\r
- if( usLinkStatus & emacFULL_DUPLEX_ENABLED )\r
- {\r
- /* Full duplex is enabled. */\r
- LPC_EMAC->MAC2 |= MAC2_FULL_DUP;\r
- LPC_EMAC->Command |= CR_FULL_DUP;\r
- LPC_EMAC->IPGT = IPGT_FULL_DUP;\r
- }\r
- else\r
- {\r
- /* Half duplex mode. */\r
- LPC_EMAC->IPGT = IPGT_HALF_DUP;\r
- }\r
-\r
- /* Configure 100MBit/10MBit mode. */\r
- if( usLinkStatus & emac10BASE_T_MODE )\r
- {\r
- /* 10MBit mode. */\r
- LPC_EMAC->SUPP = 0;\r
- }\r
- else\r
- {\r
- /* 100MBit mode. */\r
- LPC_EMAC->SUPP = SUPP_SPEED;\r
- }\r
- }\r
-\r
- return lReturn;\r
+ NyLPC_TBool lReturn = NyLPC_TBool_FALSE;\r
+ long x;\r
+ unsigned short usLinkStatus;\r
+\r
+ /* Wait with timeout for the link to be established. */\r
+ for( x = 0; x < 10; x++ )\r
+ {\r
+ usLinkStatus = prvReadPHY( PHY_REG_STS, &lReturn );\r
+ if( usLinkStatus & emacLINK_ESTABLISHED )\r
+ {\r
+ /* Link is established. */\r
+ lReturn = NyLPC_TBool_TRUE;\r
+ break;\r
+ }\r
+\r
+ NyLPC_cThread_sleep( emacWAIT_FOR_LINK_TO_ESTABLISH_MS);\r
+ }\r
+\r
+ if( lReturn == NyLPC_TBool_TRUE )\r
+ {\r
+ /* Configure Full/Half Duplex mode. */\r
+ if( usLinkStatus & emacFULL_DUPLEX_ENABLED )\r
+ {\r
+ /* Full duplex is enabled. */\r
+ LPC_EMAC->MAC2 |= MAC2_FULL_DUP;\r
+ LPC_EMAC->Command |= CR_FULL_DUP;\r
+ LPC_EMAC->IPGT = IPGT_FULL_DUP;\r
+ }\r
+ else\r
+ {\r
+ /* Half duplex mode. */\r
+ LPC_EMAC->IPGT = IPGT_HALF_DUP;\r
+ }\r
+\r
+ /* Configure 100MBit/10MBit mode. */\r
+ if( usLinkStatus & emac10BASE_T_MODE )\r
+ {\r
+ /* 10MBit mode. */\r
+ LPC_EMAC->SUPP = 0;\r
+ }\r
+ else\r
+ {\r
+ /* 100MBit mode. */\r
+ LPC_EMAC->SUPP = SUPP_SPEED;\r
+ }\r
+ }\r
+\r
+ return lReturn;\r
}\r
\r
\r
OSDN Git Service
