* TXバッファ\r
***********************************************************************/\r
\r
-//TXバッファの先頭アドレス\r
+/**\r
+ * TXバッファの先頭アドレス\r
+ * Ethernetベースアドレス+RXメモリ領域\r
+ */\r
#define ETH_TX_BUF_BASE (ETH_BUF_BASE+ETH_FRAG_SIZE*NUM_RX_FRAG)\r
\r
-#define NUM_OF_1536_BUF 3\r
+#define NUM_OF_MAX_BUF 3\r
#define NUM_OF_512_BUF 3\r
#define NUM_OF_256_BUF 4\r
#define NUM_OF_128_BUF 16\r
\r
/**\r
+ * FULLサイズのEthernetFrame送信メモリのサイズ。\r
+ * ここで最大送信サイズを制限する。\r
+ * 通常は1460+20+20+14=1514バイト\r
+ */\r
+#define MAX_TX_ETHERNET_FRAME_SIZE 1514\r
+\r
+/**\r
* TXメモリブロックの配置\r
- * 12360バイト\r
+ * 9246バイト\r
*/\r
struct TTxMemoryBlock\r
{\r
struct{\r
struct NyLPC_TTxBufferHeader h;\r
- NyLPC_TUInt8 b[1536];\r
- }buf1536[NUM_OF_1536_BUF];//(4+1536)*3=4620\r
+ NyLPC_TUInt8 b[MAX_TX_ETHERNET_FRAME_SIZE];\r
+ }buf_max[NUM_OF_MAX_BUF];//(4+MAX_TX_ETHERNET_FRAME_SIZE(1514))*3=? default=4554\r
struct{\r
struct NyLPC_TTxBufferHeader h;\r
NyLPC_TUInt8 b[512];\r
- }buf512[NUM_OF_512_BUF];//(4+512)*3=1548\r
+ }buf_512[NUM_OF_512_BUF];//(4+512)*3=1548\r
struct{\r
struct NyLPC_TTxBufferHeader h;\r
NyLPC_TUInt8 b[256];\r
- }buf256[NUM_OF_256_BUF];//(4+256)*4=1560\r
+ }buf_256[NUM_OF_256_BUF];//(4+256)*4=1560\r
struct{\r
struct NyLPC_TTxBufferHeader h;\r
NyLPC_TUInt8 b[128];\r
- }buf128[NUM_OF_128_BUF];//(4+128)*16=1584\r
+ }buf_128[NUM_OF_128_BUF];//(4+128)*16=1584\r
};\r
\r
//メモリブロックの定義\r
int x;\r
NyLPC_TUInt8 r1,r2,r3,r4;\r
r1=r2=r3=r4=0;\r
- for(x=0;x<NUM_OF_1536_BUF;x++){\r
- if(_txbuf->buf1536[x].h.is_lock || _txbuf->buf1536[x].h.ref>0){\r
+ for(x=0;x<NUM_OF_MAX_BUF;x++){\r
+ if(_txbuf->buf_max[x].h.is_lock || _txbuf->buf_max[x].h.ref>0){\r
r1++;\r
continue;\r
}\r
}\r
for(x=0;x<NUM_OF_512_BUF;x++){\r
- if(_txbuf->buf512[x].h.is_lock || _txbuf->buf512[x].h.ref>0){\r
+ if(_txbuf->buf_512[x].h.is_lock || _txbuf->buf_512[x].h.ref>0){\r
r2++;\r
continue;\r
}\r
}\r
for(x=0;x<NUM_OF_256_BUF;x++){\r
- if(_txbuf->buf256[x].h.is_lock || _txbuf->buf256[x].h.ref>0){\r
+ if(_txbuf->buf_256[x].h.is_lock || _txbuf->buf_256[x].h.ref>0){\r
r3++;\r
continue;\r
}\r
}\r
for(x=0;x<NUM_OF_128_BUF;x++){\r
- if(_txbuf->buf128[x].h.is_lock || _txbuf->buf128[x].h.ref>0){\r
+ if(_txbuf->buf_128[x].h.is_lock || _txbuf->buf_128[x].h.ref>0){\r
r4++;\r
continue;\r
}\r
TX_STAT_INFO( x ) = 0;\r
}\r
//TXバッファを初期化\r
- for(x=0;x<NUM_OF_1536_BUF;x++){\r
- _txbuf->buf1536[x].h.is_lock=NyLPC_TUInt8_FALSE;\r
- _txbuf->buf1536[x].h.ref=0;\r
+ for(x=0;x<NUM_OF_MAX_BUF;x++){\r
+ _txbuf->buf_max[x].h.is_lock=NyLPC_TUInt8_FALSE;\r
+ _txbuf->buf_max[x].h.ref=0;\r
}\r
for(x=0;x<NUM_OF_512_BUF;x++){\r
- _txbuf->buf512[x].h.is_lock=NyLPC_TUInt8_FALSE;\r
- _txbuf->buf512[x].h.ref=0;\r
+ _txbuf->buf_512[x].h.is_lock=NyLPC_TUInt8_FALSE;\r
+ _txbuf->buf_512[x].h.ref=0;\r
}\r
for(x=0;x<NUM_OF_256_BUF;x++){\r
- _txbuf->buf256[x].h.is_lock=NyLPC_TUInt8_FALSE;\r
- _txbuf->buf256[x].h.ref=0;\r
+ _txbuf->buf_256[x].h.is_lock=NyLPC_TUInt8_FALSE;\r
+ _txbuf->buf_256[x].h.ref=0;\r
}\r
for(x=0;x<NUM_OF_128_BUF;x++){\r
- _txbuf->buf128[x].h.is_lock=NyLPC_TUInt8_FALSE;\r
- _txbuf->buf128[x].h.ref=0;\r
+ _txbuf->buf_128[x].h.is_lock=NyLPC_TUInt8_FALSE;\r
+ _txbuf->buf_128[x].h.ref=0;\r
}\r
/* Set LPC_EMAC Transmit Descriptor Registers. */\r
LPC_EMAC->TxDescriptor = TX_DESC_BASE;\r
}\r
switch(buf_type){\r
case 3:\r
- for(i=0;i<NUM_OF_1536_BUF;i++){\r
+ for(i=0;i<NUM_OF_MAX_BUF;i++){\r
//未参照かつ送信中でないもの。\r
- if(_txbuf->buf1536[i].h.ref>0 || _txbuf->buf1536[i].h.is_lock){\r
+ if(_txbuf->buf_max[i].h.ref>0 || _txbuf->buf_max[i].h.is_lock){\r
continue;\r
}\r
- _txbuf->buf1536[i].h.ref++;\r
- *o_size=1536;\r
- return &(_txbuf->buf1536[i].h);\r
+ _txbuf->buf_max[i].h.ref++;\r
+ *o_size=MAX_TX_ETHERNET_FRAME_SIZE;\r
+ return &(_txbuf->buf_max[i].h);\r
}\r
case 2:\r
for(i=0;i<NUM_OF_512_BUF;i++){\r
//未参照かつ送信中でないもの。\r
- if(_txbuf->buf512[i].h.ref>0 || _txbuf->buf512[i].h.is_lock){\r
+ if(_txbuf->buf_512[i].h.ref>0 || _txbuf->buf_512[i].h.is_lock){\r
continue;\r
}\r
*o_size=512;\r
- _txbuf->buf512[i].h.ref++;\r
- return &(_txbuf->buf512[i].h);\r
+ _txbuf->buf_512[i].h.ref++;\r
+ return &(_txbuf->buf_512[i].h);\r
}\r
case 1:\r
for(i=0;i<NUM_OF_256_BUF;i++){\r
//未参照かつ送信中でないもの。\r
- if(_txbuf->buf256[i].h.ref>0 || (_txbuf->buf256[i].h.is_lock)){\r
+ if(_txbuf->buf_256[i].h.ref>0 || (_txbuf->buf_256[i].h.is_lock)){\r
continue;\r
}\r
*o_size=256;\r
- _txbuf->buf256[i].h.ref++;\r
- return &(_txbuf->buf256[i].h);\r
+ _txbuf->buf_256[i].h.ref++;\r
+ return &(_txbuf->buf_256[i].h);\r
}\r
default:\r
for(i=0;i<NUM_OF_128_BUF;i++){\r
//未参照かつ送信中でないもの。\r
- if(_txbuf->buf128[i].h.ref>0 || (_txbuf->buf128[i].h.is_lock)){\r
+ if(_txbuf->buf_128[i].h.ref>0 || (_txbuf->buf_128[i].h.is_lock)){\r
continue;\r
}\r
*o_size=128;\r
- _txbuf->buf128[i].h.ref++;\r
- return &(_txbuf->buf128[i].h);\r
+ _txbuf->buf_128[i].h.ref++;\r
+ return &(_txbuf->buf_128[i].h);\r
}\r
}\r
return NULL;\r
if (i_size > ETH_FRAG_SIZE){\r
i_size = ETH_FRAG_SIZE;\r
}\r
+\r
//送信処理\r
TX_DESC_PACKET( Index ) = ( unsigned long )(i_buf+1);\r
- TX_DESC_CTRL( Index ) = ( i_size | TCTRL_LAST | TCTRL_INT );\r
+ //See UM10360.pdf Table 181. Transmit descriptor control word\r
+ TX_DESC_CTRL( Index ) = ((i_size-1) | TCTRL_LAST | TCTRL_INT );\r
LPC_EMAC->TxProduceIndex = IndexNext;\r
return;\r
}\r
#define emacWAIT_FOR_LINK_TO_ESTABLISH_MS 500\r
\r
/* Short delay used in several places during the initialisation process. */\r
-#define emacSHORT_DELAY_MS 2\r
+#define emacSHORT_DELAY_MS 10\r
\r
/* Hardware specific bit definitions. */\r
#define emacPINSEL2_VALUE ( 0x50150105 )\r
EthDev_LPC17xx_prevRxDescriptor();\r
EthDev_LPC17xx_prevTxDescriptor();\r
\r
- /* Receive broadcast and perfect match packets */\r
- LPC_EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;\r
\r
/* Setup the PHY. */\r
prvConfigurePHY();\r
}\r
\r
/* Receive Broadcast and Perfect Match Packets */\r
- LPC_EMAC->RxFilterCtrl = RFC_BCAST_EN | RFC_PERFECT_EN;\r
-\r
- /* Reset all interrupts */\r
- LPC_EMAC->IntClear = 0xffff;\r
-\r
- /* Enable receive and transmit mode of MAC Ethernet core */\r
- LPC_EMAC->Command |= ( CR_RX_EN | CR_TX_EN );\r
- LPC_EMAC->MAC1 |= MAC1_REC_EN;\r
+ LPC_EMAC->RxFilterCtrl = RFC_BCAST_EN | RFC_PERFECT_EN | RFC_MCAST_EN;\r
\r
//Ethernetの割込み開始設定\r
NyLPC_cIsr_enterCritical();\r
{\r
+ /* Reset all interrupts */\r
+ LPC_EMAC->IntClear = 0xffff;\r
LPC_EMAC->IntEnable = ( INT_RX_DONE | INT_TX_DONE );\r
+\r
+ /* Enable receive and transmit mode of MAC Ethernet core */\r
+ LPC_EMAC->Command |= ( CR_RX_EN | CR_TX_EN );\r
+ LPC_EMAC->MAC1 |= MAC1_REC_EN;\r
+\r
/* Set the interrupt priority to the max permissible to cause some\r
interrupt nesting. */\r
NVIC_SetPriority( ENET_IRQn, configEMAC_INTERRUPT_PRIORITY );\r
\r
/* Initialize MAC control registers. */\r
LPC_EMAC->MAC1 = MAC1_PASS_ALL;\r
- LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;\r
+ LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN | MAC2_VLAN_PAD_EN;\r
LPC_EMAC->MAXF = ETH_MAX_FLEN;\r
LPC_EMAC->CLRT = CLRT_DEF;\r
LPC_EMAC->IPGR = IPGR_DEF;\r
#define emacWAIT_FOR_LINK_TO_ESTABLISH_MS 500\r
\r
/* Short delay used in several places during the initialisation process. */\r
-#define emacSHORT_DELAY_MS 2\r
+#define emacSHORT_DELAY_MS 10\r
\r
/* Hardware specific bit definitions. */\r
#define emacPINSEL2_VALUE ( 0x50150105 )\r
EthDev_LPC17xx_prevRxDescriptor();\r
EthDev_LPC17xx_prevTxDescriptor();\r
\r
- /* Receive broadcast and perfect match packets */\r
- LPC_EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;\r
\r
/* Setup the PHY. */\r
prvConfigurePHY();\r
}\r
\r
/* Receive Broadcast and Perfect Match Packets */\r
- LPC_EMAC->RxFilterCtrl = RFC_BCAST_EN | RFC_PERFECT_EN;\r
-\r
- /* Reset all interrupts */\r
- LPC_EMAC->IntClear = 0xffff;\r
-\r
- /* Enable receive and transmit mode of MAC Ethernet core */\r
- LPC_EMAC->Command |= ( CR_RX_EN | CR_TX_EN );\r
- LPC_EMAC->MAC1 |= MAC1_REC_EN;\r
+ LPC_EMAC->RxFilterCtrl = RFC_BCAST_EN | RFC_PERFECT_EN | RFC_MCAST_EN;\r
\r
//Ethernetの割込み開始設定\r
NyLPC_cIsr_enterCritical();\r
{\r
+ /* Reset all interrupts */\r
+ LPC_EMAC->IntClear = 0xffff;\r
LPC_EMAC->IntEnable = ( INT_RX_DONE | INT_TX_DONE );\r
+ /* Enable receive and transmit mode of MAC Ethernet core */\r
+ LPC_EMAC->Command |= ( CR_RX_EN | CR_TX_EN );\r
+ LPC_EMAC->MAC1 |= MAC1_REC_EN;\r
+\r
/* Set the interrupt priority to the max permissible to cause some\r
interrupt nesting. */\r
NVIC_SetPriority( ENET_IRQn, configEMAC_INTERRUPT_PRIORITY );\r
\r
/* Initialize MAC control registers. */\r
LPC_EMAC->MAC1 = MAC1_PASS_ALL;\r
- LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;\r
+ LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN | MAC2_VLAN_PAD_EN;\r
LPC_EMAC->MAXF = ETH_MAX_FLEN;\r
LPC_EMAC->CLRT = CLRT_DEF;\r
LPC_EMAC->IPGR = IPGR_DEF;\r