radeonsi: flush TC L2 cache for indirect draw data

[android-x86/external-mesa.git] / src / gallium / drivers / radeonsi / si_descriptors.c

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 57d2ae6..9f5af59 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -60,6 +60,7 @@
 #include "si_shader.h"
 #include "sid.h"
 
+#include "util/u_format.h"
 #include "util/u_math.h"
 #include "util/u_memory.h"
 #include "util/u_suballoc.h"
@@ -482,6 +483,23 @@ si_disable_shader_image(struct si_images_info *images, unsigned slot)
 }
 
 static void
+si_mark_image_range_valid(struct pipe_image_view *view)
+{
+       struct r600_resource *res = (struct r600_resource *)view->resource;
+       const struct util_format_description *desc;
+       unsigned stride;
+
+       assert(res && res->b.b.target == PIPE_BUFFER);
+
+       desc = util_format_description(view->format);
+       stride = desc->block.bits / 8;
+
+       util_range_add(&res->valid_buffer_range,
+                      stride * (view->u.buf.first_element),
+                      stride * (view->u.buf.last_element + 1));
+}
+
+static void
 si_set_shader_images(struct pipe_context *pipe, unsigned shader,
                     unsigned start_slot, unsigned count,
                     struct pipe_image_view *views)
@@ -513,6 +531,9 @@ si_set_shader_images(struct pipe_context *pipe, unsigned shader,
                                           RADEON_USAGE_READWRITE);
 
                if (res->b.b.target == PIPE_BUFFER) {
+                       if (views[i].access & PIPE_IMAGE_ACCESS_WRITE)
+                               si_mark_image_range_valid(&views[i]);
+
                        si_make_buffer_descriptor(screen, res,
                                                  views[i].format,
                                                  views[i].u.buf.first_element,
@@ -1031,10 +1052,10 @@ static void si_set_streamout_targets(struct pipe_context *ctx,
                 * and most other clients can use TC L2 as well, we don't need
                 * to flush it.
                 *
-                * The only case which requires flushing it is VGT DMA index
-                * fetching, which is a rare case. Thus, flag the TC L2
-                * dirtiness in the resource and handle it when index fetching
-                * is used.
+                * The only cases which requires flushing it is VGT DMA index
+                * fetching (on <= CIK) and indirect draw data, which are rare
+                * cases. Thus, flag the TC L2 dirtiness in the resource and
+                * handle it at draw call time.
                 */
                for (i = 0; i < sctx->b.streamout.num_targets; i++)
                        if (sctx->b.streamout.targets[i])
@@ -1309,6 +1330,9 @@ static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource
                        unsigned i = u_bit_scan(&mask);
 
                        if (images->views[i].resource == buf) {
+                               if (images->views[i].access & PIPE_IMAGE_ACCESS_WRITE)
+                                       si_mark_image_range_valid(&images->views[i]);
+
                                si_desc_reset_buffer_offset(
                                        ctx, images->desc.list + i * 8 + 4,
                                        old_va, buf);