#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#include "qemu/cpu-float.h"
/* CPU Subtypes */
#define SH_CPU_SH7750 (1 << 0)
#define FPSCR_RM_NEAREST (0 << 0)
#define FPSCR_RM_ZERO (1 << 0)
-#define DELAY_SLOT_MASK 0x7
-#define DELAY_SLOT (1 << 0)
-#define DELAY_SLOT_CONDITIONAL (1 << 1)
-#define DELAY_SLOT_RTE (1 << 2)
-
-#define TB_FLAG_PENDING_MOVCA (1 << 3)
-#define TB_FLAG_UNALIGN (1 << 4)
-
-#define GUSA_SHIFT 4
-#ifdef CONFIG_USER_ONLY
-#define GUSA_EXCLUSIVE (1 << 12)
-#define GUSA_MASK ((0xff << GUSA_SHIFT) | GUSA_EXCLUSIVE)
-#else
-/* Provide dummy versions of the above to allow tests against tbflags
- to be elided while avoiding ifdefs. */
-#define GUSA_EXCLUSIVE 0
-#define GUSA_MASK 0
-#endif
-
-#define TB_FLAG_ENVFLAGS_MASK (DELAY_SLOT_MASK | GUSA_MASK)
+#define TB_FLAG_DELAY_SLOT (1 << 0)
+#define TB_FLAG_DELAY_SLOT_COND (1 << 1)
+#define TB_FLAG_DELAY_SLOT_RTE (1 << 2)
+#define TB_FLAG_PENDING_MOVCA (1 << 3)
+#define TB_FLAG_GUSA_SHIFT 4 /* [11:4] */
+#define TB_FLAG_GUSA_EXCLUSIVE (1 << 12)
+#define TB_FLAG_UNALIGN (1 << 13)
+#define TB_FLAG_SR_FD (1 << SR_FD) /* 15 */
+#define TB_FLAG_FPSCR_PR FPSCR_PR /* 19 */
+#define TB_FLAG_FPSCR_SZ FPSCR_SZ /* 20 */
+#define TB_FLAG_FPSCR_FR FPSCR_FR /* 21 */
+#define TB_FLAG_SR_RB (1 << SR_RB) /* 29 */
+#define TB_FLAG_SR_MD (1 << SR_MD) /* 30 */
+
+#define TB_FLAG_DELAY_SLOT_MASK (TB_FLAG_DELAY_SLOT | \
+ TB_FLAG_DELAY_SLOT_COND | \
+ TB_FLAG_DELAY_SLOT_RTE)
+#define TB_FLAG_GUSA_MASK ((0xff << TB_FLAG_GUSA_SHIFT) | \
+ TB_FLAG_GUSA_EXCLUSIVE)
+#define TB_FLAG_FPSCR_MASK (TB_FLAG_FPSCR_PR | \
+ TB_FLAG_FPSCR_SZ | \
+ TB_FLAG_FPSCR_FR)
+#define TB_FLAG_SR_MASK (TB_FLAG_SR_FD | \
+ TB_FLAG_SR_RB | \
+ TB_FLAG_SR_MD)
+#define TB_FLAG_ENVFLAGS_MASK (TB_FLAG_DELAY_SLOT_MASK | \
+ TB_FLAG_GUSA_MASK)
typedef struct tlb_t {
uint32_t vpn; /* virtual page number */
struct memory_content *next;
} memory_content;
-typedef struct CPUSH4State {
+typedef struct CPUArchState {
uint32_t flags; /* general execution flags */
uint32_t gregs[24]; /* general registers */
float32 fregs[32]; /* floating point registers */
*
* A SuperH CPU.
*/
-struct SuperHCPU {
- /*< private >*/
+struct ArchCPU {
CPUState parent_obj;
- /*< public >*/
- CPUNegativeOffsetState neg;
CPUSH4State env;
};
+/**
+ * SuperHCPUClass:
+ * @parent_realize: The parent class' realize handler.
+ * @parent_phases: The parent class' reset phase handlers.
+ * @pvr: Processor Version Register
+ * @prr: Processor Revision Register
+ * @cvr: Cache Version Register
+ *
+ * A SuperH CPU model.
+ */
+struct SuperHCPUClass {
+ CPUClass parent_class;
+
+ DeviceRealize parent_realize;
+ ResettablePhases parent_phases;
+
+ uint32_t pvr;
+ uint32_t prr;
+ uint32_t cvr;
+};
void superh_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
-hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
int superh_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int superh_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
-void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
- MMUAccessType access_type, int mmu_idx,
- uintptr_t retaddr) QEMU_NORETURN;
+G_NORETURN void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
+ MMUAccessType access_type, int mmu_idx,
+ uintptr_t retaddr);
void sh4_translate_init(void);
void sh4_cpu_list(void);
#if !defined(CONFIG_USER_ONLY)
+hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
void cpu_load_tlb(CPUSH4State * env);
-#define SUPERH_CPU_TYPE_SUFFIX "-" TYPE_SUPERH_CPU
-#define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX
#define CPU_RESOLVING_TYPE TYPE_SUPERH_CPU
#define cpu_list sh4_cpu_list
{
/* The instruction in a RTE delay slot is fetched in privileged
mode, but executed in user mode. */
- if (ifetch && (env->flags & DELAY_SLOT_RTE)) {
+ if (ifetch && (env->flags & TB_FLAG_DELAY_SLOT_RTE)) {
return 0;
} else {
return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0;
}
}
-typedef CPUSH4State CPUArchState;
-typedef SuperHCPU ArchCPU;
-
#include "exec/cpu-all.h"
/* MMU control register */
env->sr = sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T));
}
-static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc,
- target_ulong *cs_base, uint32_t *flags)
+static inline void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *flags)
{
*pc = env->pc;
/* For a gUSA region, notice the end of the region. */
- *cs_base = env->flags & GUSA_MASK ? env->gregs[0] : 0;
- *flags = env->flags /* TB_FLAG_ENVFLAGS_MASK: bits 0-2, 4-12 */
- | (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR)) /* Bits 19-21 */
- | (env->sr & ((1u << SR_MD) | (1u << SR_RB))) /* Bits 29-30 */
- | (env->sr & (1u << SR_FD)) /* Bit 15 */
+ *cs_base = env->flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0;
+ *flags = env->flags
+ | (env->fpscr & TB_FLAG_FPSCR_MASK)
+ | (env->sr & TB_FLAG_SR_MASK)
| (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */
#ifdef CONFIG_USER_ONLY
*flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
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