bg display done with rtl...

diff --git a/de0_cv_nes/mem/chr_rom.vhd b/de0_cv_nes/mem/chr_rom.vhd
index ff83c27..d35334d 100644 (file)
--- a/de0_cv_nes/mem/chr_rom.vhd
+++ b/de0_cv_nes/mem/chr_rom.vhd
@@ -46,12 +46,12 @@ function rom_fill return rom_array is
 
 --for GHDL environment
 --itinialize with the rom_fill function.
-signal p_rom : rom_array := rom_fill;
+--signal p_rom : rom_array := rom_fill;
 
 --for Quartus II environment
---signal p_rom : rom_array;
---attribute ram_init_file : string;
---attribute ram_init_file of p_rom : signal is "sample1-chr.hex";
+signal p_rom : rom_array;
+attribute ram_init_file : string;
+attribute ram_init_file of p_rom : signal is "sample1-chr.hex";
 
 begin
     

diff --git a/de0_cv_nes/ppu/render.vhd b/de0_cv_nes/ppu/render.vhd
index b303adc..b9cbbe0 100644 (file)
--- a/de0_cv_nes/ppu/render.vhd
+++ b/de0_cv_nes/ppu/render.vhd
@@ -463,7 +463,6 @@ end;
             reg_disp_attr   <= (others => 'Z');\r
         elsif (rising_edge(pi_base_clk)) then\r
             reg_v_data      <= pi_v_data;\r
-            reg_plt_data    <= pi_plt_data;\r
 \r
             if (is_bg(pi_ppu_mask(PPUSBG), reg_nes_x, reg_nes_y) = 1) then\r
                 ----fetch next tile byte.\r
@@ -546,13 +545,52 @@ end;
     plt_ac_p : process (pi_rst_n, pi_base_clk)\r
     begin\r
         if (pi_rst_n = '0') then\r
+            reg_plt_addr    <= (others => 'Z');\r
+            reg_plt_data    <= (others => 'Z');\r
         elsif (rising_edge(pi_base_clk)) then\r
+            \r
+            reg_plt_data    <= pi_plt_data;\r
+            \r
             if (is_bg(pi_ppu_mask(PPUSBG), reg_nes_x, reg_nes_y) = 1) then\r
+                if (conv_std_logic_vector(reg_nes_y, 9)(4) = '0'\r
+                    and (reg_disp_ptn_h(0) or reg_disp_ptn_l(0)) = '1') then\r
+                    reg_plt_addr <=\r
+                            "0" & reg_disp_attr(1 downto 0) & reg_disp_ptn_h(0) & reg_disp_ptn_l(0);\r
+                elsif (conv_std_logic_vector(reg_nes_y, 9)(4) = '1'\r
+                    and (reg_disp_ptn_h(0) or reg_disp_ptn_l(0)) = '1') then\r
+                    reg_plt_addr <=\r
+                            "0" & reg_disp_attr(5 downto 4) & reg_disp_ptn_h(0) & reg_disp_ptn_l(0);\r
+                else\r
+                    ---else: no output color >> universal bg color output.\r
+                    --0x3f00 is the universal bg palette.\r
+                    reg_plt_addr <= (others => '0');\r
+                end if;\r
             end if;\r
         end if;--if (pi_rst_n = '0') then\r
     end process;\r
 \r
-    reg_plt_addr <= (others => 'Z');\r
+    rgb_out_p : process (pi_rst_n, pi_base_clk)\r
+    begin\r
+        if (pi_rst_n = '0') then\r
+            po_b <= (others => '0');\r
+            po_g <= (others => '0');\r
+            po_r <= (others => '0');\r
+        else\r
+            if (rising_edge(pi_base_clk)) then\r
+                if (reg_nes_x < HSCAN and reg_nes_y < VSCAN) then\r
+                    --if or if not bg/sprite is shown, output color anyway \r
+                    --sinse universal bg color is included..\r
+                    po_b <= nes_color_palette(conv_integer(reg_plt_data(5 downto 0))) (11 downto 8);\r
+                    po_g <= nes_color_palette(conv_integer(reg_plt_data(5 downto 0))) (7 downto 4);\r
+                    po_r <= nes_color_palette(conv_integer(reg_plt_data(5 downto 0))) (3 downto 0);\r
+                else\r
+                    po_b <= (others => '0');\r
+                    po_g <= (others => '0');\r
+                    po_r <= (others => '0');\r
+                end if;\r
+            end if; --if (rising_edge(emu_ppu_clk)) then\r
+        end if;--if (rst_n = '0') then\r
+    end process;--output_p\r
 \r
     po_ppu_status   <= (others => '0');\r
 \r
@@ -561,8 +599,5 @@ end;
     po_spr_wr_n     <= 'Z';\r
     po_spr_addr     <= (others => 'Z');\r
 \r
-    po_r           <= (others => 'Z');\r
-    po_g           <= (others => 'Z');\r
-    po_b           <= (others => 'Z');\r
 end rtl;\r
 \r

diff --git a/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do b/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
index 5593567..7caf4a1 100644 (file)
--- a/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
+++ b/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
@@ -60,13 +60,16 @@ add wave -label disp_attr   -radix hex sim:/testbench_motones_sim/sim_board/rend
 add wave -label disp_ptn_l -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_disp_ptn_l;\r
 add wave -label disp_ptn_h -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_disp_ptn_h;\r
 \r
+add wave -label plt_addr -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_plt_addr;\r
+add wave -label plt_data -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_plt_data;\r
+\r
 \r
 add wave -divider vga\r
 add wave -label h_sync_n       sim:/testbench_motones_sim/sim_board/po_h_sync_n;\r
 add wave -label v_sync_n    sim:/testbench_motones_sim/sim_board/po_v_sync_n;\r
-add wave -label r       sim:/testbench_motones_sim/sim_board/po_r;\r
-add wave -label g       sim:/testbench_motones_sim/sim_board/po_g;\r
-add wave -label b       sim:/testbench_motones_sim/sim_board/po_b;\r
+add wave -label r -radix hex sim:/testbench_motones_sim/sim_board/po_r;\r
+add wave -label g -radix hex sim:/testbench_motones_sim/sim_board/po_g;\r
+add wave -label b -radix hex sim:/testbench_motones_sim/sim_board/po_b;\r
 \r
 \r
 #add wave -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg*;\r