palette bus separated.

diff --git a/de0_cv_nes/chip_selector.vhd b/de0_cv_nes/chip_selector.vhd
index f38f9bc..f849158 100644 (file)
--- a/de0_cv_nes/chip_selector.vhd
+++ b/de0_cv_nes/chip_selector.vhd
@@ -196,12 +196,12 @@ entity v_chip_selector is
     port (\r
                 pi_rst_n        : in std_logic;\r
                 pi_base_clk     : in std_logic;\r
+                pi_v_ce_n       : in std_logic;\r
                 pi_v_addr       : in std_logic_vector (13 downto 0);\r
                 pi_nt_v_mirror  : in std_logic;\r
                 po_pt_ce_n      : out std_logic;\r
                 po_nt0_ce_n     : out std_logic;\r
-                po_nt1_ce_n     : out std_logic;\r
-                po_plt_ce_n     : out std_logic\r
+                po_nt1_ce_n     : out std_logic\r
         );\r
 end v_chip_selector;\r
 \r
@@ -210,13 +210,11 @@ architecture rtl of v_chip_selector is
 signal reg_pt_ce_n       : std_logic;\r
 signal reg_nt0_ce_n      : std_logic;\r
 signal reg_nt1_ce_n      : std_logic;\r
-signal reg_plt_ce_n      : std_logic;\r
 \r
 begin\r
     po_pt_ce_n <= reg_pt_ce_n;\r
     po_nt0_ce_n <= reg_nt0_ce_n;\r
     po_nt1_ce_n <= reg_nt1_ce_n;\r
-    po_plt_ce_n <= reg_plt_ce_n;\r
 \r
     v_chip_sel_p : process (pi_rst_n, pi_base_clk)\r
     begin\r
@@ -224,45 +222,43 @@ begin
             reg_pt_ce_n <= '1';\r
             reg_nt0_ce_n <= '1';\r
             reg_nt1_ce_n <= '1';\r
-            reg_plt_ce_n <= '1';\r
         else\r
             if (rising_edge(pi_base_clk)) then\r
-                if ((pi_v_addr(13) = '0')) then\r
-                    reg_pt_ce_n <= '0';\r
-                else\r
-                    reg_pt_ce_n <= '1';\r
-                end if;\r
+                if (pi_v_ce_n = '0') then\r
+                    if ((pi_v_addr(13) = '0')) then\r
+                        reg_pt_ce_n <= '0';\r
+                    else\r
+                        reg_pt_ce_n <= '1';\r
+                    end if;\r
 \r
-                if (pi_v_addr(13) = '0') then\r
-                    reg_nt0_ce_n <= '1';\r
-                elsif (pi_v_addr(13 downto 8) = "111111") then\r
-                    reg_nt0_ce_n <= '1';\r
-                elsif (((pi_v_addr(11) or pi_v_addr(10)) = '0') \r
-                        or (pi_nt_v_mirror = '1' and pi_v_addr(11) = '1' and pi_v_addr(10) = '0')\r
-                        or (pi_nt_v_mirror = '0' and pi_v_addr(11) = '0' and pi_v_addr(10) = '1')) then\r
-                    reg_nt0_ce_n <= '0';\r
-                else\r
-                    reg_nt0_ce_n <= '1';\r
-                end if;\r
+                    if (pi_v_addr(13) = '0') then\r
+                        reg_nt0_ce_n <= '1';\r
+                    elsif (pi_v_addr(13 downto 8) = "111111") then\r
+                        reg_nt0_ce_n <= '1';\r
+                    elsif (((pi_v_addr(11) or pi_v_addr(10)) = '0') \r
+                            or (pi_nt_v_mirror = '1' and pi_v_addr(11) = '1' and pi_v_addr(10) = '0')\r
+                            or (pi_nt_v_mirror = '0' and pi_v_addr(11) = '0' and pi_v_addr(10) = '1')) then\r
+                        reg_nt0_ce_n <= '0';\r
+                    else\r
+                        reg_nt0_ce_n <= '1';\r
+                    end if;\r
 \r
-                if (pi_v_addr(13) = '0') then\r
-                    reg_nt1_ce_n <= '1';\r
-                elsif (pi_v_addr(13 downto 8) = "111111") then\r
-                    reg_nt1_ce_n <= '1';\r
-                elsif (((pi_v_addr(11) and pi_v_addr(10)) = '1') \r
-                    or (pi_nt_v_mirror = '1' and pi_v_addr(11) = '0' and pi_v_addr(10) = '1')\r
-                    or (pi_nt_v_mirror = '0' and pi_v_addr(11) = '1' and pi_v_addr(10) = '0')) then\r
-                    reg_nt1_ce_n <= '0';\r
+                    if (pi_v_addr(13) = '0') then\r
+                        reg_nt1_ce_n <= '1';\r
+                    elsif (pi_v_addr(13 downto 8) = "111111") then\r
+                        reg_nt1_ce_n <= '1';\r
+                    elsif (((pi_v_addr(11) and pi_v_addr(10)) = '1') \r
+                        or (pi_nt_v_mirror = '1' and pi_v_addr(11) = '0' and pi_v_addr(10) = '1')\r
+                        or (pi_nt_v_mirror = '0' and pi_v_addr(11) = '1' and pi_v_addr(10) = '0')) then\r
+                        reg_nt1_ce_n <= '0';\r
+                    else\r
+                        reg_nt1_ce_n <= '1';\r
+                    end if;\r
                 else\r
+                    reg_pt_ce_n <= '1';\r
+                    reg_nt0_ce_n <= '1';\r
                     reg_nt1_ce_n <= '1';\r
                 end if;\r
-\r
-                if (pi_v_addr(13 downto 8) = "111111") then\r
-                    reg_plt_ce_n <= '0';\r
-                else\r
-                    reg_plt_ce_n <= '1';\r
-                end if;\r
-\r
             end if;\r
         end if;\r
     end process;\r

diff --git a/de0_cv_nes/de0_cv_nes.vhd b/de0_cv_nes/de0_cv_nes.vhd
index d9d9ce7..e1c2c90 100644 (file)
--- a/de0_cv_nes/de0_cv_nes.vhd
+++ b/de0_cv_nes/de0_cv_nes.vhd
@@ -71,11 +71,18 @@ architecture rtl of de0_cv_nes is
                 pi_cpu_addr    : in std_logic_vector (2 downto 0);
                 pio_cpu_d      : inout std_logic_vector (7 downto 0);
 
+                po_v_ce_n       : out std_logic;\r
                 po_v_rd_n       : out std_logic;\r
                 po_v_wr_n       : out std_logic;\r
                 po_v_addr       : out std_logic_vector (13 downto 0);\r
                 pio_v_data      : inout std_logic_vector (7 downto 0);\r
 \r
+                po_plt_ce_n     : out std_logic;\r
+                po_plt_rd_n     : out std_logic;\r
+                po_plt_wr_n     : out std_logic;\r
+                po_plt_addr     : out std_logic_vector (4 downto 0);\r
+                pio_plt_data    : inout std_logic_vector (7 downto 0);\r
+\r
                 po_spr_ce_n     : out std_logic;\r
                 po_spr_rd_n     : out std_logic;\r
                 po_spr_wr_n     : out std_logic;\r
@@ -126,12 +133,12 @@ architecture rtl of de0_cv_nes is
         port (\r
                     pi_rst_n        : in std_logic;\r
                     pi_base_clk     : in std_logic;\r
+                    pi_v_ce_n       : in std_logic;\r
                     pi_v_addr       : in std_logic_vector (13 downto 0);\r
                     pi_nt_v_mirror  : in std_logic;\r
                     po_pt_ce_n      : out std_logic;\r
                     po_nt0_ce_n     : out std_logic;\r
-                    po_nt1_ce_n     : out std_logic;\r
-                    po_plt_ce_n     : out std_logic\r
+                    po_nt1_ce_n     : out std_logic\r
             );\r
     end component;\r
 \r
@@ -149,11 +156,19 @@ architecture rtl of de0_cv_nes is
             pi_ppu_scroll_y    : in std_logic_vector (7 downto 0);\r
 \r
             --vram i/f\r
-            po_rd_n         : out std_logic;\r
-            po_wr_n         : out std_logic;\r
+            po_v_ce_n       : out std_logic;\r
+            po_v_rd_n       : out std_logic;\r
+            po_v_wr_n       : out std_logic;\r
             po_v_addr       : out std_logic_vector (13 downto 0);\r
             pi_v_data       : in std_logic_vector (7 downto 0);\r
 \r
+            --plt i/f\r
+            po_plt_ce_n     : out std_logic;\r
+            po_plt_rd_n     : out std_logic;\r
+            po_plt_wr_n     : out std_logic;\r
+            po_plt_addr     : out std_logic_vector (4 downto 0);\r
+            pi_plt_data     : in std_logic_vector (7 downto 0);\r
+\r
             --sprite i/f\r
             po_spr_ce_n     : out std_logic;\r
             po_spr_rd_n     : out std_logic;\r
@@ -190,11 +205,18 @@ signal wr_ram_ce_n     : std_logic;
 signal wr_ppu_ce_n     : std_logic;\r
 signal wr_apu_ce_n     : std_logic;\r
 \r
+signal wr_v_ce_n        : std_logic;\r
 signal wr_v_rd_n        : std_logic;\r
 signal wr_v_wr_n        : std_logic;\r
 signal wr_v_addr        : std_logic_vector (13 downto 0);\r
 signal wr_v_data        : std_logic_vector (7 downto 0);\r
 \r
+signal wr_plt_ce_n      : std_logic;\r
+signal wr_plt_rd_n      : std_logic;\r
+signal wr_plt_wr_n      : std_logic;\r
+signal wr_plt_addr      : std_logic_vector (4 downto 0);\r
+signal wr_plt_data      : std_logic_vector (7 downto 0);\r
+\r
 signal wr_spr_ce_n      : std_logic;\r
 signal wr_spr_rd_n      : std_logic;\r
 signal wr_spr_wr_n      : std_logic;\r
@@ -204,7 +226,6 @@ signal wr_spr_data      : std_logic_vector (7 downto 0);
 signal wr_pt_ce_n       : std_logic;\r
 signal wr_nt0_ce_n      : std_logic;\r
 signal wr_nt1_ce_n      : std_logic;\r
-signal wr_plt_ce_n      : std_logic;\r
 \r
 signal wr_ppu_ctrl          : std_logic_vector (7 downto 0);\r
 signal wr_ppu_mask          : std_logic_vector (7 downto 0);\r
@@ -258,11 +279,18 @@ begin
             wr_addr(2 downto 0), \r
             wr_d_io,\r
 \r
+            wr_v_ce_n,\r
             wr_v_rd_n,\r
             wr_v_wr_n,\r
             wr_v_addr,\r
             wr_v_data,\r
 \r
+            wr_plt_ce_n,\r
+            wr_plt_rd_n,\r
+            wr_plt_wr_n,\r
+            wr_plt_addr,\r
+            wr_plt_data,\r
+\r
             wr_spr_ce_n,\r
             wr_spr_rd_n,\r
             wr_spr_wr_n,\r
@@ -280,13 +308,13 @@ begin
     --vram chip select (address decode)\r
     vcs_inst : v_chip_selector port map (\r
             pi_rst_n,\r
-            pi_base_clk, \r
+            pi_base_clk,\r
+            wr_v_ce_n,\r
             wr_v_addr,\r
             pi_nt_v_mirror,\r
             wr_pt_ce_n,\r
             wr_nt0_ce_n,\r
-            wr_nt1_ce_n,\r
-            wr_plt_ce_n\r
+            wr_nt1_ce_n\r
             );\r
 \r
     --name table/attr table #0\r
@@ -315,10 +343,10 @@ begin
     vram_plt_inst : palette_ram port map (\r
             pi_base_clk,\r
             wr_plt_ce_n,\r
-            wr_v_rd_n,\r
-            wr_v_wr_n,\r
-            wr_v_addr(4 downto 0),\r
-            wr_v_data\r
+            wr_plt_rd_n,\r
+            wr_plt_wr_n,\r
+            wr_plt_addr,\r
+            wr_plt_data\r
             );\r
 \r
     --pattern table\r
@@ -354,11 +382,19 @@ begin
             wr_ppu_scroll_y,\r
 \r
             --vram i/f\r
+            wr_v_ce_n,\r
             wr_v_rd_n,\r
             wr_v_wr_n,\r
             wr_v_addr,\r
             wr_v_data,\r
 \r
+            --plt i/f\r
+            wr_plt_ce_n,\r
+            wr_plt_rd_n,\r
+            wr_plt_wr_n,\r
+            wr_plt_addr,\r
+            wr_plt_data,\r
+\r
             --sprite i/f\r
             wr_spr_ce_n,\r
             wr_spr_rd_n,\r

diff --git a/de0_cv_nes/ppu/ppu.vhd b/de0_cv_nes/ppu/ppu.vhd
index 702bced..bf50b0c 100644 (file)
--- a/de0_cv_nes/ppu/ppu.vhd
+++ b/de0_cv_nes/ppu/ppu.vhd
@@ -12,11 +12,18 @@ entity ppu is
                 pi_cpu_addr    : in std_logic_vector (2 downto 0);
                 pio_cpu_d      : inout std_logic_vector (7 downto 0);
 
+                po_v_ce_n       : out std_logic;\r
                 po_v_rd_n       : out std_logic;
                 po_v_wr_n       : out std_logic;
                 po_v_addr       : out std_logic_vector (13 downto 0);
                 pio_v_data      : inout std_logic_vector (7 downto 0);
 \r
+                po_plt_ce_n     : out std_logic;\r
+                po_plt_rd_n     : out std_logic;\r
+                po_plt_wr_n     : out std_logic;\r
+                po_plt_addr     : out std_logic_vector (4 downto 0);\r
+                pio_plt_data    : inout std_logic_vector (7 downto 0);\r
+\r
                 po_spr_ce_n     : out std_logic;\r
                 po_spr_rd_n     : out std_logic;\r
                 po_spr_wr_n     : out std_logic;\r
@@ -58,11 +65,14 @@ signal reg_v_next_state     : vac_state;
 signal reg_spr_cur_state    : vac_state;
 signal reg_spr_next_state   : vac_state;
 
-signal reg_v_rd_n       : std_logic;
-signal reg_v_wr_n       : std_logic;
-signal reg_v_addr       : std_logic_vector (13 downto 0);
-signal reg_v_data       : std_logic_vector (7 downto 0);
-
+signal reg_v_ce_n       : std_logic;\r
+signal reg_v_rd_n       : std_logic;\r
+signal reg_v_wr_n       : std_logic;\r
+signal reg_v_addr       : std_logic_vector (13 downto 0);\r
+signal reg_v_data       : std_logic_vector (7 downto 0);\r
+\r
+signal reg_plt_ce_n       : std_logic;\r
+\r
 signal reg_spr_ce_n       : std_logic;\r
 signal reg_spr_rd_n       : std_logic;\r
 signal reg_spr_wr_n       : std_logic;\r
@@ -172,11 +182,18 @@ begin
     end process;
 
     --vram output signal...
-    po_v_rd_n        <= reg_v_rd_n;
-    po_v_wr_n        <= reg_v_wr_n;
-    po_v_addr   <= reg_v_addr;
-    pio_v_data  <= reg_v_data;
+    po_v_ce_n       <= reg_v_ce_n;\r
+    po_v_rd_n       <= reg_v_rd_n;
+    po_v_wr_n       <= reg_v_wr_n;
+    po_v_addr       <= reg_v_addr;
+    pio_v_data      <= reg_v_data;
 
+    po_plt_ce_n     <= reg_plt_ce_n;\r
+    po_plt_rd_n     <= reg_v_rd_n;\r
+    po_plt_wr_n     <= reg_v_wr_n;\r
+    po_plt_addr     <= reg_v_addr(4 downto 0);\r
+    pio_plt_data    <= reg_v_data;\r
+\r
     --vram access state machine (state transition)...
     ac_set_stat_p : process (pi_rst_n, pi_base_clk)
     begin
@@ -233,36 +250,63 @@ begin
     begin
         case reg_v_cur_state is
             when idle =>
-                reg_v_rd_n         <= 'Z';
-                reg_v_wr_n         <= 'Z';
-                reg_v_addr    <= (others => 'Z');
-                reg_v_data    <= (others => 'Z');
+                reg_v_ce_n      <= 'Z';\r
+                reg_v_rd_n      <= 'Z';
+                reg_v_wr_n      <= 'Z';
+                reg_v_addr      <= (others => 'Z');
+                reg_v_data      <= (others => 'Z');\r
+                reg_plt_ce_n    <= 'Z';
             when reg_set =>
                 --register is set in set_ppu_p process.
-                reg_v_rd_n         <= '1';
-                reg_v_wr_n         <= '1';
+                reg_v_ce_n      <= '1';\r
+                reg_v_rd_n      <= '1';
+                reg_v_wr_n      <= '1';
                 reg_v_addr    <= (others => 'Z');
                 reg_v_data    <= (others => 'Z');
+                reg_plt_ce_n    <= '1';\r
             when reg_out =>
-                reg_v_rd_n         <= '1';
-                reg_v_wr_n         <= '1';
+                if (reg_ppu_addr(13 downto 8) = "111111") then\r
+                    reg_v_ce_n      <= '1';\r
+                    reg_plt_ce_n    <= '0';\r
+                else\r
+                    reg_plt_ce_n    <= '1';\r
+                    reg_v_ce_n      <= '0';\r
+                end if;\r
+                reg_v_rd_n      <= '1';
+                reg_v_wr_n      <= '1';
                 reg_v_addr    <= reg_ppu_addr;
                 reg_v_data    <= reg_ppu_data;
             when mem_write =>
-                reg_v_rd_n         <= '1';
-                reg_v_wr_n         <= '0';
+                if (reg_ppu_addr(13 downto 8) = "111111") then\r
+                    reg_v_ce_n      <= '1';\r
+                    reg_plt_ce_n    <= '0';\r
+                else\r
+                    reg_plt_ce_n    <= '1';\r
+                    reg_v_ce_n      <= '0';\r
+                end if;\r
+                reg_v_rd_n      <= '1';
+                reg_v_wr_n      <= '0';
                 reg_v_addr    <= reg_ppu_addr;
                 reg_v_data    <= reg_ppu_data;
             when write_end =>
-                reg_v_rd_n         <= '1';
-                reg_v_wr_n         <= '1';
+                if (reg_ppu_addr(13 downto 8) = "111111") then\r
+                    reg_v_ce_n      <= '1';\r
+                    reg_plt_ce_n    <= '0';\r
+                else\r
+                    reg_plt_ce_n    <= '1';\r
+                    reg_v_ce_n      <= '0';\r
+                end if;\r
+                reg_v_rd_n      <= '1';
+                reg_v_wr_n      <= '1';
                 reg_v_addr    <= reg_ppu_addr;
                 reg_v_data    <= reg_ppu_data;
             when complete =>
-                reg_v_rd_n         <= '1';
-                reg_v_wr_n         <= '1';
+                reg_v_ce_n      <= '1';\r
+                reg_v_rd_n      <= '1';
+                reg_v_wr_n      <= '1';
                 reg_v_addr    <= (others => 'Z');
                 reg_v_data    <= (others => 'Z');
+                reg_plt_ce_n    <= '1';\r
         end case;
     end process;
 

diff --git a/de0_cv_nes/ppu/render.vhd b/de0_cv_nes/ppu/render.vhd
index ce79111..b303adc 100644 (file)
--- a/de0_cv_nes/ppu/render.vhd
+++ b/de0_cv_nes/ppu/render.vhd
@@ -23,11 +23,19 @@ entity render is
         pi_ppu_scroll_y    : in std_logic_vector (7 downto 0);\r
 \r
         --vram i/f\r
-        po_rd_n         : out std_logic;\r
-        po_wr_n         : out std_logic;\r
+        po_v_ce_n       : out std_logic;\r
+        po_v_rd_n       : out std_logic;\r
+        po_v_wr_n       : out std_logic;\r
         po_v_addr       : out std_logic_vector (13 downto 0);\r
         pi_v_data       : in std_logic_vector (7 downto 0);\r
 \r
+        --plt i/f\r
+        po_plt_ce_n     : out std_logic;\r
+        po_plt_rd_n     : out std_logic;\r
+        po_plt_wr_n     : out std_logic;\r
+        po_plt_addr     : out std_logic_vector (4 downto 0);\r
+        pi_plt_data     : in std_logic_vector (7 downto 0);\r
+\r
         --sprite i/f\r
         po_spr_ce_n     : out std_logic;\r
         po_spr_rd_n     : out std_logic;\r
@@ -165,6 +173,21 @@ constant nes_color_palette : nes_color_array := (
         conv_std_logic_vector(16#000#, 12)\r
         );\r
 \r
+function is_bg (\r
+    pm_sbg          : in std_logic;\r
+    pm_nes_x        : in integer range 0 to VGA_W_MAX - 1;\r
+    pm_nes_y        : in integer range 0 to VGA_H_MAX - 1\r
+    )return integer is\r
+begin\r
+    if (pm_sbg = '1'and\r
+        (pm_nes_x <= HSCAN or pm_nes_x >= HSCAN_NEXT_START) and\r
+        (pm_nes_y < VSCAN or pm_nes_y = VSCAN_NEXT_START)) then\r
+        return 1;\r
+    else\r
+        return 0;\r
+    end if;\r
+end;\r
+\r
 signal reg_vga_x        : integer range 0 to VGA_W_MAX - 1;\r
 signal reg_vga_y        : integer range 0 to VGA_H_MAX - 1;\r
 \r
@@ -189,6 +212,7 @@ type vac_state is (
 signal reg_v_cur_state      : vac_state;\r
 signal reg_v_next_state     : vac_state;\r
 \r
+signal reg_v_ce_n       : std_logic;\r
 signal reg_v_rd_n       : std_logic;\r
 signal reg_v_wr_n       : std_logic;\r
 signal reg_v_addr       : std_logic_vector (13 downto 0);\r
@@ -199,6 +223,12 @@ signal reg_disp_attr        : std_logic_vector (7 downto 0);
 signal reg_disp_ptn_l       : std_logic_vector (15 downto 0);\r
 signal reg_disp_ptn_h       : std_logic_vector (15 downto 0);\r
 \r
+signal reg_plt_ce_n       : std_logic;\r
+signal reg_plt_rd_n       : std_logic;\r
+signal reg_plt_wr_n       : std_logic;\r
+signal reg_plt_addr       : std_logic_vector (4 downto 0);\r
+signal reg_plt_data       : std_logic_vector (7 downto 0);\r
+\r
 begin\r
 \r
     --position and sync signal generate.\r
@@ -384,10 +414,16 @@ end;
         end case;\r
     end process;\r
 \r
-    po_rd_n         <= reg_v_rd_n;\r
-    po_wr_n         <= reg_v_wr_n;\r
+    po_v_ce_n       <= reg_v_ce_n;\r
+    po_v_rd_n       <= reg_v_rd_n;\r
+    po_v_wr_n       <= reg_v_wr_n;\r
     po_v_addr       <= reg_v_addr;\r
 \r
+    po_plt_ce_n     <= reg_plt_ce_n;\r
+    po_plt_rd_n     <= reg_plt_rd_n;\r
+    po_plt_wr_n     <= reg_plt_wr_n;\r
+    po_plt_addr     <= reg_plt_addr;\r
+\r
     --vram r/w selector state machine...\r
     vac_main_stat_p : process (reg_v_cur_state)\r
     begin\r
@@ -402,24 +438,23 @@ end;
                 reg_v_rd_n  <= '0';\r
                 reg_v_wr_n  <= '1';\r
         end case;\r
+\r
+        case reg_v_cur_state is\r
+            when IDLE =>\r
+                reg_v_ce_n  <= 'Z';\r
+                reg_plt_ce_n <= 'Z';\r
+                reg_plt_rd_n <= 'Z';\r
+                reg_plt_wr_n <= 'Z'; \r
+            when AD_SET0 | AD_SET1 | REG_SET2 | REG_SET3 | AD_SET2 | AD_SET3 | REG_SET0 | REG_SET1 =>\r
+                reg_v_ce_n  <= '0';\r
+                reg_plt_ce_n <= '0';\r
+                reg_plt_rd_n <= '0';\r
+                reg_plt_wr_n <= '1'; \r
+        end case;\r
     end process;\r
 \r
     --vram address state machine...\r
     vaddr_stat_p : process (pi_rst_n, pi_base_clk)\r
-function is_bg (\r
-    pm_sbg          : in std_logic;\r
-    pm_nes_x        : in integer range 0 to VGA_W_MAX - 1;\r
-    pm_nes_y        : in integer range 0 to VGA_H_MAX - 1\r
-    )return integer is\r
-begin\r
-    if (pm_sbg = '1'and\r
-        (pm_nes_x <= HSCAN or pm_nes_x >= HSCAN_NEXT_START) and\r
-        (pm_nes_y < VSCAN or pm_nes_y = VSCAN_NEXT_START)) then\r
-        return 1;\r
-    else\r
-        return 0;\r
-    end if;\r
-end;\r
     begin\r
         if (pi_rst_n = '0') then\r
             reg_v_addr  <= (others => 'Z');\r
@@ -427,8 +462,9 @@ end;
             reg_disp_nt     <= (others => 'Z');\r
             reg_disp_attr   <= (others => 'Z');\r
         elsif (rising_edge(pi_base_clk)) then\r
-            reg_v_data    <= pi_v_data;\r
-            \r
+            reg_v_data      <= pi_v_data;\r
+            reg_plt_data    <= pi_plt_data;\r
+\r
             if (is_bg(pi_ppu_mask(PPUSBG), reg_nes_x, reg_nes_y) = 1) then\r
                 ----fetch next tile byte.\r
                 if (reg_prf_x mod 8 = 1) then\r
@@ -475,22 +511,8 @@ end;
         end if;--if (pi_rst_n = '0') then\r
     end process;\r
 \r
-    --vram address state machine...\r
+    --pattern table state machine...\r
     bg_ptn_p : process (pi_rst_n, pi_base_clk)\r
-function is_bg (\r
-    pm_sbg          : in std_logic;\r
-    pm_nes_x        : in integer range 0 to VGA_W_MAX - 1;\r
-    pm_nes_y        : in integer range 0 to VGA_H_MAX - 1\r
-    )return integer is\r
-begin\r
-    if (pm_sbg = '1'and\r
-        (pm_nes_x <= HSCAN or pm_nes_x >= HSCAN_NEXT_START) and\r
-        (pm_nes_y < VSCAN or pm_nes_y = VSCAN_NEXT_START)) then\r
-        return 1;\r
-    else\r
-        return 0;\r
-    end if;\r
-end;\r
     begin\r
         if (pi_rst_n = '0') then\r
             reg_disp_ptn_l  <= (others => '0');\r
@@ -520,6 +542,18 @@ end;
         end if;--if (pi_rst_n = '0') then\r
     end process;\r
 \r
+    --palette table state machine...\r
+    plt_ac_p : process (pi_rst_n, pi_base_clk)\r
+    begin\r
+        if (pi_rst_n = '0') then\r
+        elsif (rising_edge(pi_base_clk)) then\r
+            if (is_bg(pi_ppu_mask(PPUSBG), reg_nes_x, reg_nes_y) = 1) then\r
+            end if;\r
+        end if;--if (pi_rst_n = '0') then\r
+    end process;\r
+\r
+    reg_plt_addr <= (others => 'Z');\r
+\r
     po_ppu_status   <= (others => '0');\r
 \r
     po_spr_ce_n     <= 'Z';\r

diff --git a/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do b/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
index da8999f..5593567 100644 (file)
--- a/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
+++ b/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
@@ -69,7 +69,7 @@ add wave -label g       sim:/testbench_motones_sim/sim_board/po_g;
 add wave -label b       sim:/testbench_motones_sim/sim_board/po_b;\r
 \r
 \r
-#add wave -radix hex sim:/testbench_motones_sim/sim_board/vram_plt_inst/*;\r
+#add wave -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg*;\r
 \r
 \r
 view structure\r

diff --git a/doc/mos6502-bus.xlsx b/doc/mos6502-bus.xlsx
index 6d52d42..0610114 100644 (file)
Binary files a/doc/mos6502-bus.xlsx and b/doc/mos6502-bus.xlsx differ