Mark II
+
*/
:- use_module(library(assoc)).
:- use_module(library(clpfd)).
asm(mov_imm(TEMP3, 4)), % Factored out of the loop. Used for linking.
repeat_until(if_zero(TEMP0), [ % TEMP0 = Address of the quoted program.
load(TERM, TEMP0),
+ label(iball, _),
unpack_pair(TERM, TEMP1, TEMP2, TEMP0),
% TEMP1 is the address of head item, TEMP2 is the tail
asm(mov(TEMP0, TEMP2)), % update temp0 to point to rest of quoted program.
% TERM is the last item in the quoted program.
% The expr should point to a cell that has TEMP1 head and tail
% of the rest of the expression.
- [merge_and_store(TEMP1, TEMP3, SP)]
+ [sub_base_from_offset(TEMP1, SP), merge_and_store(TEMP1, TEMP3, SP)]
% TERM has at least one more item after it.
% We know that we will be writing that item in a
% cell immediately after this one, so it has TEMP1
merge_and_store(TEMP3, TEMP0, SP), % Push second item onto stack.
jump(Main),
+ % ======================================
definition(unit, Unit, [New, Cons], DoDef, TOS),
definition(x, X, [Dup, I], DoDef, TOS),
definition(swons, Swons, [Swap, Cons], DoDef, TOS),
+ % ======================================
- label(dodef, DoDef), % TOS points to body expr, set by definition.
+ label(dodef, DoDef), % ======================================
+ % TOS points to body expr, set by definition.
asm(mov_imm(TEMP1, 4)), % Used for linking to previous cell.
incr(SP),
sub_base_from_offset(TOS, SP),
label(Label)].
⟐(unpack_pair(From, HeadAddr, TailAddr, Base)) -->
- [lsl_imm(HeadAddr, From, 2)], % Trim off the type tag 00 bits.
+ [label('unpack[', _), lsl_imm(HeadAddr, From, 2)], % Trim off the type tag 00 bits.
⟐(roll_down_add_base_if_not_zero(HeadAddr, Base)),
[lsl_imm(TailAddr, From, 17)], % Trim off tag and head address.
- ⟐(roll_down_add_base_if_not_zero(TailAddr, Base)).
+ ⟐(roll_down_add_base_if_not_zero(TailAddr, Base)),
+ [label(']unpack', _)].
⟐(roll_down_add_base_if_not_zero(Addr, Base)) -->
[asr_imm(Addr, Addr, 17), % Preserving sign.
asm([(N, Instruction)|Rest]) --> !, asm(N, Instruction), asm(Rest).
asm(Here, expr_cell(Func, NextCell)) --> !,
- {Data is ((Func - Here) << 15) \/ NextCell}, asm(Here, word(Data)).
+ {Data is (((Func - Here) /\ 0x7fff) << 15) \/ NextCell},
+ asm(Here, word(Data)).
asm(_, symbol(Sym)) --> !, {Data is (Sym + 4) \/ 0x80000000}, asm(_, word(Data)).
% The symbol is at the beginning of the function machine code, so the pointer it
=========================\r
\r
\r
+\r
+This (and the previous incarnation) is really more of a "macro assembler"\r
+than a compiler, and nothing like what I want it to be. It should be\r
+tracking the "types" of registers in some enviroment that gets carried\r
+along and picking primitives and making optimizations based on that\r
+information.\r
+\r
+\r
TO replace the crude first draft I want to expand the representation of\r
data types.\r
\r
ペ, write_cell(TOS, SP)\r
\r
\r
+--------------------------------------\r
+\r
+Debugging definitions\r
+\r
+ swons 0xd2 load R[0] <- ram[R[0] + 0x34c]\r
+> 0xd3 mov R[2] <- 0x354\r
+ 0xd4 BR T 0x2 immediate \r
+ 0xd5 BR F -0x69fffc immediate and R[15] <- PC + 1\r
+ 0xd6 BR GT -0x4c0000 immediate and R[15] <- PC + 1\r
+ dodef 0xd7 mov R[7] <- 0x4\r
+ 0xd8 sub R[0] <- R[0] 0x4 immediate\r
+\r
+Q: Is 0x354 >> 2 == 0xd5 ?\r
+\r
+In [1]: 0x354 >> 2 == 0xd5\r
+Out[1]: True\r
+\r
+Okay then.\r
+\r
+\r
+> dodef 0xd7 mov R[7] <- 0x4\r
+ 0xd8 sub R[0] <- R[0] 0x4 immediate\r
+ 0xd9 sub R[2] <- R[2] 0x0 immediate\r
+ 0xda BR EQ 0x2 immediate \r
+ 0xdb sub R[2] <- R[2] R[0]\r
+ 0xdc and R[2] <- R[2] 0x7fff immediate\r
+\r
+\r
+0xff4 r0\r
+0x354 r2\r
+\r
+\r
+> 0xde ior R[2] <- R[2] R[7]\r
+ 0xdf store R[2] -> ram[R[0]]\r
+ 0xe0 mov R[7] <- 0x168\r
+ 0xe1 add R[7] <- R[7] 0x4 immediate\r
+ 0xe2 BR T R[7]\r
+ expressi 0xe3 BR F 0x740004 immediate and R[15] <- PC + 1\r
+\r
+0x39b00004 r2\r
+\r
+ 0xe0 mov R[7] <- 0x168\r
+> 0xe1 add R[7] <- R[7] 0x4 immediate\r
+ 0xe2 BR T R[7]\r
+ expressi 0xe3 BR F 0x740004 immediate and R[15] <- PC + 1\r
+\r
+\r
+0x16c r7 = 364 decimal\r
+\r
+0x5b I machine code in words\r
+\r
+In [8]: 0x16c >> 2 == 0x5b\r
+Out[8]: True\r
+\r
+ i 0x5a load R[0] <- ram[R[0] + 0x16c]\r
+> 0x5b lsl R[6] <- R[2] 0x2 immediate\r
+ 0x5c asr R[6] <- R[6] 0x11 immediate\r
+ 0x5d BR EQ 0x1 immediate \r
+ 0x5e add R[6] <- R[6] R[0]\r
+ 0x5f lsl R[2] <- R[2] 0x11 immediate\r
+ 0x60 asr R[2] <- R[2] 0x11 immediate\r
+\r
+and then...\r
+\r
+ i 0x5a load R[0] <- ram[R[0] + 0x16c]\r
+ 0x5b lsl R[6] <- R[2] 0x2 immediate\r
+ 0x5c asr R[6] <- R[6] 0x11 immediate\r
+ 0x5d BR EQ 0x1 immediate \r
+> 0x5e add R[6] <- R[6] R[0]\r
+ 0x5f lsl R[2] <- R[2] 0x11 immediate\r
+ 0x60 asr R[2] <- R[2] 0x11 immediate\r
+ 0x61 BR EQ 0x1 immediate \r
+ 0x62 add R[2] <- R[2] R[0]\r
+ 0x63 sub R[6] <- R[6] 0x0 immediate\r
+\r
+0x354 r6 check\r
+\r
+ 0x5e add R[6] <- R[6] R[0]\r
+ 0x5f lsl R[2] <- R[2] 0x11 immediate\r
+ 0x60 asr R[2] <- R[2] 0x11 immediate\r
+ 0x61 BR EQ 0x1 immediate \r
+> 0x62 add R[2] <- R[2] R[0]\r
+ 0x63 sub R[6] <- R[6] 0x0 immediate\r
+ 0x64 BR EQ 0x22 immediate \r
+ 0x65 sub R[10] <- R[0] 0x4 immediate\r
+\r
+0xff8 r2\r
+\r
+ 0x61 BR EQ 0x1 immediate \r
+ 0x62 add R[2] <- R[2] R[0]\r
+ 0x63 sub R[6] <- R[6] 0x0 immediate\r
+#117 0x64 BR EQ 0x22 immediate \r
+> 0x65 sub R[10] <- R[0] 0x4 immediate\r
+ 0x66 mov R[9] <- 0x4\r
+ 0x67 load R[3] <- ram[R[6]]\r
+ iball 0x68 lsl R[7] <- R[3] 0x2 immediate\r
+ 0x69 asr R[7] <- R[7] 0x11 immediate\r
+ 0x6a BR EQ 0x1 immediate \r
+\r
+line 120\r
+\r
+#120 0x65 sub R[10] <- R[0] 0x4 immediate\r
+ 0x66 mov R[9] <- 0x4\r
+> 0x67 load R[3] <- ram[R[6]]\r
+ iball 0x68 lsl R[7] <- R[3] 0x2 immediate\r
+ 0x69 asr R[7] <- R[7] 0x11 immediate\r
+ 0x6a BR EQ 0x1 immediate \r
+ 0x6b add R[7] <- R[7] R[6]\r
+ 0x6c lsl R[8] <- R[3] 0x11 immediate\r
+\r
+line 123\r
+\r
+0xff960004 r3\r
+\r
+ iball 0x68 lsl R[7] <- R[3] 0x2 immediate\r
+ 0x69 asr R[7] <- R[7] 0x11 immediate\r
+ 0x6a BR EQ 0x1 immediate \r
+> 0x6b add R[7] <- R[7] R[6]\r
+ 0x6c lsl R[8] <- R[3] 0x11 immediate\r
+ 0x6d asr R[8] <- R[8] 0x11 immediate\r
+ 0x6e BR EQ 0x1 immediate \r
+ 0x6f add R[8] <- R[8] R[6]\r
+ 0x70 mov R[6] <- R[8]\r
+\r
+0x280 r7 Address of swons def list? of swap symbol?\r
+\r
+ In [4]: w.cpu.R[7]\r
+ Out[4]: 640L\r
+\r
+ In [5]: hex(_)\r
+ Out[5]: '0x280L'\r
+\r
+ In [6]: w.cpu.ram[w.cpu.R[7]]\r
+ Out[6]: 2147484292L\r
+\r
+ In [7]: bin(_)\r
+ Out[7]: '0b10000000000000000000001010000100'\r
+\r
+ In [8]: w.syms.keys()\r
+ Out[8]: [160, 35, 7, 104, 44, 45, 14, 205, 48, 200, 210, 227, 86, 215, 90, 157]\r
+\r
+ In [9]: 640 >> 2\r
+ Out[9]: 160\r
+\r
+ In [10]: w.syms[160]\r
+ Out[10]: 'swap'\r
+\r
+0x280 r7 points to swap symbol record.\r
+===================================================\r
+\r
+ 0x6b add R[7] <- R[7] R[6]\r
+ 0x6c lsl R[8] <- R[3] 0x11 immediate\r
+ 0x6d asr R[8] <- R[8] 0x11 immediate\r
+ 0x6e BR EQ 0x1 immediate \r
+> 0x6f add R[8] <- R[8] R[6]\r
+#127 0x70 mov R[6] <- R[8]\r
+ 0x71 sub R[0] <- R[0] 0x4 immediate\r
+ 0x72 sub R[8] <- R[8] 0x0 immediate\r
+ 0x73 BR EQ 0x4 immediate \r
+\r
+0x358 r8\r
+\r
+> 0x70 mov R[6] <- R[8]\r
+\r
+line 127\r
+\r
+ 0x70 mov R[6] <- R[8]\r
+ 0x71 sub R[0] <- R[0] 0x4 immediate\r
+ 0x72 sub R[8] <- R[8] 0x0 immediate\r
+> 0x73 BR EQ 0x4 immediate \r
+ 0x74 lsl R[7] <- R[7] 0xf immediate\r
+ 0x75 ior R[7] <- R[7] R[9]\r
+ 0x76 store R[7] -> ram[R[0]]\r
+ 0x77 BR T 0xb immediate \r
+ 0x78 sub R[7] <- R[7] 0x0 immediate\r
+\r
+line 129\r
+\r
+ 0x73 BR EQ 0x4 immediate \r
+ 0x74 lsl R[7] <- R[7] 0xf immediate\r
+ 0x75 ior R[7] <- R[7] R[9]\r
+> 0x76 store R[7] -> ram[R[0]]\r
+ 0x77 BR T 0xb immediate \r
+\r
+0x1400004 r7 -> ram[r[0]] w/ r0 = 0xff0\r
+\r
+saved foobar1\r
+\r
+I think I found it. Not subtracting SP from r7 address\r
+before merge_and_store(TEMP1, TEMP3, SP) on line #134.\r
+!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\r
+\r
+jmp @ 0x77 to 0xb -> 0x83\r
+repeat\r
+> 0x83 sub R[6] <- R[6] 0x0 immediate\r
+ 0x84 BR EQ 0x1 immediate \r
+ 0x85 BR T -0x1f immediate \r
+ 0x86 mov R[1] <- R[10]\r
+ 0x87 load R[7] <- ram[R[2]]\r
+ 0x88 lsl R[6] <- R[7] 0x2 immediate\r
+\r
+\r
+0x85 + -0x1f\r
+\r
+> 0x67 load R[3] <- ram[R[6]]\r
+ iball 0x68 lsl R[7] <- R[3] 0x2 immediate\r
+ 0x69 asr R[7] <- R[7] 0x11 immediate\r
+ 0x6a BR EQ 0x1 immediate \r
+ 0x6b add R[7] <- R[7] R[6]\r
+ 0x6c lsl R[8] <- R[3] 0x11 immediate\r
+\r
+back to line 123\r
+\r
+ iball 0x68 lsl R[7] <- R[3] 0x2 immediate\r
+ 0x69 asr R[7] <- R[7] 0x11 immediate\r
+ 0x6a BR EQ 0x1 immediate \r
+ 0x6b add R[7] <- R[7] R[6]\r
+ 0x6c lsl R[8] <- R[3] 0x11 immediate\r
+ 0x6d asr R[8] <- R[8] 0x11 immediate\r
+> 0x6e BR EQ 0x1 immediate \r
+ 0x6f add R[8] <- R[8] R[6]\r
+ 0x70 mov R[6] <- R[8]\r
+ 0x71 sub R[0] <- R[0] 0x4 immediate\r
+ 0x72 sub R[8] <- R[8] 0x0 immediate\r
+ 0x73 BR EQ 0x4 immediate \r
+\r
+0xc0 r7\r
+0x0 r8\r
+\r
+ 0x6e BR EQ 0x1 immediate \r
+ 0x6f add R[8] <- R[8] R[6]\r
+ 0x70 mov R[6] <- R[8]\r
+ 0x71 sub R[0] <- R[0] 0x4 immediate\r
+ 0x72 sub R[8] <- R[8] 0x0 immediate\r
+> 0x73 BR EQ 0x4 immediate \r
+ 0x74 lsl R[7] <- R[7] 0xf immediate\r
+ 0x75 ior R[7] <- R[7] R[9]\r
+ 0x76 store R[7] -> ram[R[0]]\r
+ 0x77 BR T 0xb immediate \r
+ 0x78 sub R[7] <- R[7] 0x0 immediate\r
+\r
+We take the high road this time\r
+\r
+ 0x73 BR EQ 0x4 immediate \r
+ 0x74 lsl R[7] <- R[7] 0xf immediate\r
+ 0x75 ior R[7] <- R[7] R[9]\r
+ 0x76 store R[7] -> ram[R[0]]\r
+ 0x77 BR T 0xb immediate \r
+> 0x78 sub R[7] <- R[7] 0x0 immediate\r
+ 0x79 BR EQ 0x2 immediate \r
+ 0x7a sub R[7] <- R[7] R[0]\r
+ 0x7b and R[7] <- R[7] 0x7fff immediate\r
+ 0x7c sub R[1] <- R[1] 0x0 immediate\r
+ 0x7d BR EQ 0x2 immediate \r
+\r
+\r
+r7 = 0xc0\r
+r0 = 0xfec\r
+\r
+so, @0x7a, r7 <- r7 - r0 -> -3884 or -0xf2c\r
+Hmm...\r
+\r
+ 0x78 sub R[7] <- R[7] 0x0 immediate\r
+ 0x79 BR EQ 0x2 immediate \r
+ 0x7a sub R[7] <- R[7] R[0]\r
+> 0x7b and R[7] <- R[7] 0x7fff immediate\r
+ 0x7c sub R[1] <- R[1] 0x0 immediate\r
+ 0x7d BR EQ 0x2 immediate \r
+ 0x7e sub R[1] <- R[1] R[0]\r
+ 0x7f and R[1] <- R[1] 0x7fff immediate\r
+ 0x80 lsl R[7] <- R[7] 0xf immediate\r
+\r
+\r
+\r
+ 0x7b and R[7] <- R[7] 0x7fff immediate\r
+ 0x7c sub R[1] <- R[1] 0x0 immediate\r
+ 0x7d BR EQ 0x2 immediate \r
+> 0x7e sub R[1] <- R[1] R[0]\r
+ 0x7f and R[1] <- R[1] 0x7fff immediate\r
+ 0x80 lsl R[7] <- R[7] 0xf immediate\r
+ 0x81 ior R[7] <- R[7] R[1]\r
+ 0x82 store R[7] -> ram[R[0]]\r
+\r
+0xfffff3ac r1 ... 0x73ac\r
+\r
+ 0x7e sub R[1] <- R[1] R[0]\r
+ 0x7f and R[1] <- R[1] 0x7fff immediate\r
+ 0x80 lsl R[7] <- R[7] 0xf immediate\r
+ 0x81 ior R[7] <- R[7] R[1]\r
+> 0x82 store R[7] -> ram[R[0]]\r
+ 0x83 sub R[6] <- R[6] 0x0 immediate\r
+ 0x84 BR EQ 0x1 immediate \r
+ 0x85 BR T -0x1f immediate \r
+ 0x86 mov R[1] <- R[10]\r
+ 0x87 load R[7] <- ram[R[2]]\r
+\r
+0x386a73ac r7 !?\r
+\r
+ 0x82 store R[7] -> ram[R[0]]\r
+ 0x83 sub R[6] <- R[6] 0x0 immediate\r
+ 0x84 BR EQ 0x1 immediate \r
+ 0x85 BR T -0x1f immediate \r
+> 0x86 mov R[1] <- R[10]\r
+ 0x87 load R[7] <- ram[R[2]]\r
+ 0x88 lsl R[6] <- R[7] 0x2 immediate\r
+ 0x89 asr R[6] <- R[6] 0x11 immediate\r
+ 0x8a BR EQ 0x1 immediate \r
+ 0x8b add R[6] <- R[6] R[2]\r
+\r
+line 141\r
+\r
+> 0x87 load R[7] <- ram[R[2]]\r
+\r
+line 146\r
+\r
+0x4 r7 "the record of the second stack cell"\r
+empty list followed by the record one cell above\r
+\r
+ 0x87 load R[7] <- ram[R[2]]\r
+* 0x88 lsl R[6] <- R[7] 0x2 immediate\r
+* 0x89 asr R[6] <- R[6] 0x11 immediate\r
+* 0x8a BR EQ 0x1 immediate \r
+* 0x8b add R[6] <- R[6] R[2]\r
+* 0x8c lsl R[7] <- R[7] 0x11 immediate\r
+* 0x8d asr R[7] <- R[7] 0x11 immediate\r
+* 0x8e BR EQ 0x1 immediate \r
+* 0x8f add R[7] <- R[7] R[2]\r
+> 0x90 sub R[0] <- R[0] 0x4 immediate\r
+ 0x91 sub R[6] <- R[6] 0x0 immediate\r
+ 0x92 BR EQ 0x2 immediate \r
+ 0x93 sub R[6] <- R[6] R[0]\r
+ 0x94 and R[6] <- R[6] 0x7fff immediate\r
+ 0x95 sub R[7] <- R[7] 0x0 immediate\r
+\r
+at line 150\r
+0x0 r6\r
+0xffc r7\r
+\r
+TEMP0 = HeadAddr, TEMP1 = TailAddr\r
+\r
+mkII.2.2 saved here.\r
+\r
+ 0x90 sub R[0] <- R[0] 0x4 immediate\r
+ 0x91 sub R[6] <- R[6] 0x0 immediate\r
+ 0x92 BR EQ 0x2 immediate \r
+ 0x93 sub R[6] <- R[6] R[0]\r
+ 0x94 and R[6] <- R[6] 0x7fff immediate\r
+ 0x95 sub R[7] <- R[7] 0x0 immediate\r
+ 0x96 BR EQ 0x2 immediate \r
+ 0x97 sub R[7] <- R[7] R[0]\r
+ 0x98 and R[7] <- R[7] 0x7fff immediate\r
+ 0x99 lsl R[6] <- R[6] 0xf immediate\r
+ 0x9a ior R[6] <- R[6] R[7]\r
+> 0x9b store R[6] -> ram[R[0]]\r
+ 0x9c BR T -0x8f immediate \r
+ new 0x9d load R[0] <- ram[R[0] + 0x278]\r
+ 0x9e mov R[5] <- 0x0\r
+ 0x9f BR T -0x7d immediate \r
+ swap 0xa0 load R[0] <- ram[R[0] + 0x284]\r
+\r
+\r
+lie 151-152 end of I machine code\r
+\r
+0x14 r6 20 decimal 5 words/cells above\r
+0xfe8 r0\r
+\r
+> main 0xe sub R[1] <- R[1] 0x0 immediate\r
+ 0xf BR EQ 0x1f immediate \r
+ 0x10 load R[4] <- ram[R[1]]\r
+ 0x11 lsl R[5] <- R[4] 0x2 immediate\r
+ 0x12 asr R[5] <- R[5] 0x11 immediate\r
+ 0x13 BR EQ 0x1 immediate \r
+\r
+0xff0 r1\r
+\r
+\r
+\r
+saved mkII.2.3\r
+\r
+ main 0xe sub R[1] <- R[1] 0x0 immediate\r
+ 0xf BR EQ 0x1f immediate \r
+> 0x10 load R[4] <- ram[R[1]]\r
+ 0x11 lsl R[5] <- R[4] 0x2 immediate\r
+ 0x12 asr R[5] <- R[5] 0x11 immediate\r
+ 0x13 BR EQ 0x1 immediate \r
+ 0x14 add R[5] <- R[5] R[1]\r
+ 0x15 lsl R[6] <- R[4] 0x11 immediate\r
+\r
+line 50 \r
+0x1400004 r4\r
+\r
+ main 0xe sub R[1] <- R[1] 0x0 immediate\r
+ 0xf BR EQ 0x1f immediate \r
+ 0x10 load R[4] <- ram[R[1]]\r
+ 0x11 lsl R[5] <- R[4] 0x2 immediate\r
+ 0x12 asr R[5] <- R[5] 0x11 immediate\r
+ 0x13 BR EQ 0x1 immediate \r
+> 0x14 add R[5] <- R[5] R[1]\r
+ 0x15 lsl R[6] <- R[4] 0x11 immediate\r
+ 0x16 asr R[6] <- R[6] 0x11 immediate\r
+ 0x17 BR EQ 0x1 immediate \r
+ 0x18 add R[6] <- R[6] R[1]\r
+ 0x19 load R[3] <- ram[R[5]]\r
+\r
+0x1270 r5\r
+\r
+ 0x14 add R[5] <- R[5] R[1]\r
+ 0x15 lsl R[6] <- R[4] 0x11 immediate\r
+ 0x16 asr R[6] <- R[6] 0x11 immediate\r
+ 0x17 BR EQ 0x1 immediate \r
+> 0x18 add R[6] <- R[6] R[1]\r
+ 0x19 load R[3] <- ram[R[5]]\r
+ 0x1a mov R[1] <- R[6]\r
+ 0x1b asr R[6] <- R[3] 0x1e immediate\r
+ 0x1c and R[6] <- R[6] 0x2 immediate\r
+ 0x1d sub R[6] <- R[6] 0x2 immediate\r
+\r
+0xff4 r6\r
+\r
+> 0x19 load R[3] <- ram[R[5]]\r
+\r
+line 53\r
+0x0 r3 ram[0x1270] \r
+\r
+> 0x1a mov R[1] <- R[6]\r
+\r
+line 56\r
+\r
+0xff4 r1\r
+\r
+\r
+ 0x1d sub R[6] <- R[6] 0x2 immediate\r
+ 0x1e BR NE 0x4 immediate \r
+ 0x1f mov R[6] <- 0x3fff0000\r
+ 0x20 ior R[6] <- R[6] 0xffff immediate\r
+ 0x21 and R[6] <- R[6] R[3]\r
+ 0x22 BR T R[6]\r
+> push 0x23 sub R[0] <- R[0] 0x4 immediate\r
+ 0x24 sub R[5] <- R[5] 0x0 immediate\r
+ 0x25 BR EQ 0x6 immediate \r
+ 0x26 sub R[2] <- R[5] R[0]\r
+ 0x27 BR HI 0x1 immediate \r
+ 0x28 and R[2] <- R[2] 0x7fff immediate\r
+\r
+Not a literal, 0x0 (but it should be, it should point to swap)\r
+\r
+ push 0x23 sub R[0] <- R[0] 0x4 immediate\r
+ 0x24 sub R[5] <- R[5] 0x0 immediate\r
+ 0x25 BR EQ 0x6 immediate \r
+> 0x26 sub R[2] <- R[5] R[0]\r
+ 0x27 BR HI 0x1 immediate \r
+ 0x28 and R[2] <- R[2] 0x7fff immediate\r
+ 0x29 lsl R[2] <- R[2] 0xf immediate\r
+ 0x2a ior R[2] <- R[2] 0x4 immediate\r
+ 0x2b BR T 0x1 immediate \r
+\r
+line 68\r
+\r
+0xfe4 r0 SP\r
+0x28c r2 TOS\r
+0x1270 r5 TermAddr\r
+\r
+ push 0x23 sub R[0] <- R[0] 0x4 immediate\r
+ 0x24 sub R[5] <- R[5] 0x0 immediate\r
+ 0x25 BR EQ 0x6 immediate \r
+ 0x26 sub R[2] <- R[5] R[0]\r
+ 0x27 BR HI 0x1 immediate \r
+ 0x28 and R[2] <- R[2] 0x7fff immediate\r
+> 0x29 lsl R[2] <- R[2] 0xf immediate\r
+ 0x2a ior R[2] <- R[2] 0x4 immediate\r
+ 0x2b BR T 0x1 immediate \r
+ jpel 0x2c mov R[2] <- 0x4\r
+ done 0x2d store R[2] -> ram[R[0]]\r
+ 0x2e BR T -0x21 immediate \r
+\r
+line 75\r
+\r
+\r
+\r
+\r
+==================================================\r
+\r
+iball * 2\r
+\r
+0xfeac0000 r2\r
+\r
+\r
+0xc0 r7\r
+\r
+ 0x67 load R[3] <- ram[R[6]]\r
+ iball 0x68 lsl R[7] <- R[3] 0x2 immediate\r
+ 0x69 asr R[7] <- R[7] 0x11 immediate\r
+ 0x6a BR EQ 0x1 immediate \r
+> 0x6b add R[7] <- R[7] R[6]\r
+ 0x6c lsl R[8] <- R[3] 0x11 immediate\r
+ 0x6d asr R[8] <- R[8] 0x11 immediate\r
+ 0x6e BR EQ 0x1 immediate \r
+ 0x6f add R[8] <- R[8] R[6]\r
+ 0x70 mov R[6] <- R[8]\r
+\r
+0x0 r8\r
+\r
+ 0x70 mov R[6] <- R[8]\r
+> 0x71 sub R[0] <- R[0] 0x4 immediate\r
+ 0x72 sub R[8] <- R[8] 0x0 immediate\r
+ 0x73 BR EQ 0x8 immediate \r
+ 0x74 sub R[7] <- R[7] 0x0 immediate\r
+ 0x75 BR EQ 0x2 immediate \r
+ 0x76 sub R[7] <- R[7] R[0]\r
+ 0x77 and R[7] <- R[7] 0x7fff immediate\r
+ 0x78 lsl R[7] <- R[7] 0xf immediate\r
+ 0x79 ior R[7] <- R[7] R[9]\r
+ 0x7a store R[7] -> ram[R[0]]\r
+ 0x7b BR T 0xb immediate \r
+> 0x7c sub R[7] <- R[7] 0x0 immediate\r
+ 0x7d BR EQ 0x2 immediate \r
+ 0x7e sub R[7] <- R[7] R[0]\r
+ 0x7f and R[7] <- R[7] 0x7fff immediate\r
+ 0x80 sub R[1] <- R[1] 0x0 immediate\r
+ 0x81 BR EQ 0x2 immediate \r
+\r
+\r
+\r
+===================================================\r
+\r
+Looksgood so far...\r
+\r
+but we just loaded\r
+> 0x67 load R[3] <- ram[R[6]]\r
+\r
+and the value in r3 is malformed:\r
+\r
+In [14]: x = 0xfeac0000\r
+\r
+In [15]: bin(x)\r
+Out[15]: '0b11111110101011000000000000000000'\r
+\r
+In [16]: len(_)-2\r
+Out[16]: 32\r
+\r
+We just loaded that at line 123\r
+load(TERM, TEMP0),\r
+\r
+Ah!\r
+\r
+I think it's that expr_cell/2 doesn't zero out the top two bits for\r
+records that have negative head offsets.\r
+\r
+\r
+\r
\r
\r
\r