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astoria-d [Tue, 14 May 2013 08:25:48 +0000 (17:25 +0900)]
adc renamed.
and circuit added.
astoria-d [Tue, 14 May 2013 07:56:49 +0000 (16:56 +0900)]
adc test added.
astoria-d [Tue, 14 May 2013 07:25:07 +0000 (16:25 +0900)]
alu changed to use sequential statement.
astoria-d [Mon, 13 May 2013 07:44:19 +0000 (16:44 +0900)]
alu integrated.
astoria-d [Sun, 12 May 2013 01:27:04 +0000 (10:27 +0900)]
structurte >> rtl
astoria-d [Sat, 11 May 2013 10:57:44 +0000 (19:57 +0900)]
alu circuit work started.
astoria-d [Sat, 11 May 2013 09:35:12 +0000 (18:35 +0900)]
testbench updated.
astoria-d [Fri, 10 May 2013 12:25:18 +0000 (21:25 +0900)]
test modified.
astoria-d [Fri, 10 May 2013 10:49:22 +0000 (19:49 +0900)]
adc calcuration ok
astoria-d [Wed, 8 May 2013 11:09:00 +0000 (20:09 +0900)]
start working on cpu simulation
astoria-d [Tue, 7 May 2013 10:53:42 +0000 (19:53 +0900)]
test
astoria-d [Tue, 7 May 2013 10:28:24 +0000 (19:28 +0900)]
8 bit adder test bench ok
astoria-d [Sun, 5 May 2013 06:30:50 +0000 (15:30 +0900)]
8-bit adder
astoria-d [Sun, 5 May 2013 05:21:10 +0000 (14:21 +0900)]
clean up
astoria-d [Sun, 5 May 2013 05:13:59 +0000 (14:13 +0900)]
full adder ok
astoria-d [Sat, 4 May 2013 11:37:08 +0000 (20:37 +0900)]
removed
astoria-d [Sat, 4 May 2013 11:36:15 +0000 (20:36 +0900)]
full adder test
astoria-d [Sat, 4 May 2013 10:20:23 +0000 (19:20 +0900)]
test
astoria-d [Sat, 4 May 2013 10:14:30 +0000 (19:14 +0900)]
test
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