adc renamed.

and circuit added.

diff --git a/simulation/cpu/alu/Makefile b/simulation/cpu/alu/Makefile
index 3f5ce4e..be8f419 100644 (file)
--- a/simulation/cpu/alu/Makefile
+++ b/simulation/cpu/alu/Makefile
@@ -1,6 +1,6 @@
 
 TEST_FILES=testbench_alu.vhd testbench_adc.vhd 
-FILES=alu.vhd adc.vhd $(TEST_FILES)
+FILES=alu.vhd alu_adc.vhd alu_and.vhd $(TEST_FILES)
 TEST_BIN=testbench_alu
 
 GHDL_OPTION=--ieee=synopsys -fexplicit

diff --git a/simulation/cpu/alu/alu.vhd b/simulation/cpu/alu/alu.vhd
index bf092c5..6441040 100644 (file)
--- a/simulation/cpu/alu/alu.vhd
+++ b/simulation/cpu/alu/alu.vhd
@@ -13,7 +13,7 @@ entity alu is
 end alu;
 
 architecture rtl of alu is
-    component adc
+    component alu_adc
         port (  a, b    : in std_logic_vector (7 downto 0);
                 sum       : out std_logic_vector (7 downto 0);
                 cin         : in std_logic;
@@ -21,24 +21,49 @@ architecture rtl of alu is
                 n, v, z : out std_logic
                 );
     end component;
+    component alu_and
+        port (  a, b    : in std_logic_vector (7 downto 0);
+                and_o     : out std_logic_vector (7 downto 0);
+                n, z    : out std_logic
+                );
+    end component;
     signal adc_o : std_logic_vector (7 downto 0);
     signal adc_cout, adc_n, adc_v, adc_z : std_logic;
+    signal and_o : std_logic_vector (7 downto 0);
+    signal and_n, and_z : std_logic;
 begin
-    adc_port : adc port map (a, b, adc_o, cin, adc_cout, adc_n, adc_v, adc_z);
+    adc_port : alu_adc port map (a, b, adc_o, cin, adc_cout, adc_n, adc_v, adc_z);
+    and_port : alu_and port map (a, b, and_o, and_n, and_z);
 
-    p : process (a, b, m, cin, adc_o)
+    p : process (a, b, m, cin, adc_o, and_o)
     begin
-    case m(7 downto 5) is
-        when "011" =>
-          ---case adc.
-            o <= adc_o;
-            n <= adc_n;
-            v <= adc_v;
-            z <= adc_z;
-            cout <= adc_cout;
-        when others =>
-            reset <= '1';
-    end case;
+    -- m is form of  "aaabbbcc"
+    if m(1 downto 0) = "01" then
+    -- case cc == 01
+        case m(7 downto 5) is
+            when "011" =>
+              ---case adc.
+                o <= adc_o;
+                n <= adc_n;
+                v <= adc_v;
+                z <= adc_z;
+                cout <= adc_cout;
+            when "001" =>
+              ---case and.
+                o <= and_o;
+                n <= and_n;
+                z <= and_z;
+            when others =>
+                reset <= '1';
+        end case;
+    elsif m(1 downto 0) = "10" then
+    -- case cc == 10
+    elsif m(1 downto 0) = "00" then
+    -- case cc == 00
+    else
+        reset <= '1';
+    end if;
+
     end process;
 
 end rtl;

diff --git a/simulation/cpu/alu/adc.vhd b/simulation/cpu/alu/alu_adc.vhd
similarity index 93%
rename from simulation/cpu/alu/adc.vhd
rename to simulation/cpu/alu/alu_adc.vhd
index c602696..3ca0417 100644 (file)
--- a/simulation/cpu/alu/adc.vhd
+++ b/simulation/cpu/alu/alu_adc.vhd
@@ -8,16 +8,16 @@ use ieee.std_logic_unsigned.all;
 --* A + M + C -> A
 --* Flags: N, V, Z, C
 
-entity adc is
+entity alu_adc is
     port (  a, b    : in std_logic_vector (7 downto 0);
             sum       : out std_logic_vector (7 downto 0);
             cin         : in std_logic;
             cout        : out std_logic;
             n, v, z : out std_logic
             );
-end adc;
+end alu_adc;
 
-architecture rtl of adc is
+architecture rtl of alu_adc is
 signal adc_work : std_logic_vector (8 downto 0);
 begin
     adc_work <= ('0' & a) + ('0' & b) + ("0000000" & cin);

diff --git a/simulation/cpu/alu/alu_and.vhd b/simulation/cpu/alu/alu_and.vhd
new file mode 100644 (file)
index 0000000..9c92338
--- /dev/null
+++ b/simulation/cpu/alu/alu_and.vhd
@@ -0,0 +1,31 @@
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+
+--* AND Memory with Accumulator: AND
+--* A & M -> A
+--* Flags: N, Z
+
+entity alu_and is
+    port (  a, b    : in std_logic_vector (7 downto 0);
+            and_o     : out std_logic_vector (7 downto 0);
+            n, z    : out std_logic
+            );
+end alu_and;
+
+architecture rtl of alu_and is
+signal and_work : std_logic_vector (7 downto 0);
+begin
+
+    and_work <= a and b;
+
+    n <= '1' when (and_work(7) = '1') else
+         '0';
+    z <= '1' when (and_work(7 downto 0) = "00000000") else
+         '0';
+    and_o <= and_work;
+
+end rtl;
+

diff --git a/simulation/cpu/alu/testbench_adc.vhd b/simulation/cpu/alu/testbench_adc.vhd
index 8a944a9..34be70b 100644 (file)
--- a/simulation/cpu/alu/testbench_adc.vhd
+++ b/simulation/cpu/alu/testbench_adc.vhd
@@ -10,7 +10,7 @@ entity testbench_adc is
 end testbench_adc;
 
 architecture stimulus of testbench_adc is 
-    component adc
+    component alu_adc
     port (  a, b    : in std_logic_vector (7 downto 0);
             sum       : out std_logic_vector (7 downto 0);
             cin         : in std_logic;
@@ -21,7 +21,7 @@ architecture stimulus of testbench_adc is
     signal aa, bb, ssum: std_logic_vector (7 downto 0);
     signal ccin, ccout, nn, vv, zz : std_logic;
 begin
-    dut : adc port map (aa, bb, ssum, ccin, ccout, nn, vv, zz);
+    dut : alu_adc port map (aa, bb, ssum, ccin, ccout, nn, vv, zz);
     ccin <= '0';
 
     p : process

diff --git a/simulation/cpu/alu/testbench_alu.vhd b/simulation/cpu/alu/testbench_alu.vhd
index 84ee253..0979a38 100644 (file)
--- a/simulation/cpu/alu/testbench_alu.vhd
+++ b/simulation/cpu/alu/testbench_alu.vhd
@@ -40,7 +40,7 @@ begin
         writeline(output, out_line);
         aa <= x"74";
         bb <= x"70";
-        mm <= "01100111";
+        mm <= "01100101";
         ccin <= '0';
         wait for interval;
 
@@ -48,7 +48,7 @@ begin
         writeline(output, out_line);
         aa <= x"80";
         bb <= x"84";
-        mm <= "01100000";
+        mm <= "01100001";
         ccin <= '0';
         wait for interval;
 
@@ -56,7 +56,7 @@ begin
         writeline(output, out_line);
         aa <= x"a0";
         bb <= x"cf";
-        mm <= "01100000";
+        mm <= "01100001";
         ccin <= '0';
         wait for interval;
 
@@ -64,7 +64,7 @@ begin
         writeline(output, out_line);
         aa <= conv_std_logic_vector(10#40#, 8);
         bb <= conv_std_logic_vector(10#120#, 8);
-        mm <= "01111111";
+        mm <= "01111101";
         ccin <= '0';
         wait for interval;
 
@@ -72,7 +72,7 @@ begin
         writeline(output, out_line);
         aa <= conv_std_logic_vector(10#40#, 8);
         bb <= conv_std_logic_vector(10#51#, 8);
-        mm <= "01111111";
+        mm <= "01111101";
         ccin <= '0';
         wait for interval;
 
@@ -80,7 +80,31 @@ begin
         writeline(output, out_line);
         aa <= x"f5";
         bb <= x"14";
-        mm <= "01111111";
+        mm <= "01111101";
+        ccin <= '0';
+        wait for interval;
+
+        write(out_line, string'("and test 1"));
+        writeline(output, out_line);
+        aa <= x"55";
+        bb <= x"f0";
+        mm <= "00100001";
+        ccin <= '0';
+        wait for interval;
+
+        write(out_line, string'("and test 2"));
+        writeline(output, out_line);
+        aa <= x"55";
+        bb <= x"aa";
+        mm <= "00100001";
+        ccin <= '0';
+        wait for interval;
+
+        write(out_line, string'("and test 3"));
+        writeline(output, out_line);
+        aa <= x"ef";
+        bb <= x"aa";
+        mm <= "00100001";
         ccin <= '0';
         wait for interval;