1 %default { "naninst":"li rTEMP, -1" }
3 %verify "basic lt, gt, eq */
5 %verify "right arg NaN"
7 * Compare two floating-point values. Puts 0, 1, or -1 into the
8 * destination register based on the results of the comparison.
10 * Provide a "naninst" instruction that puts 1 or -1 into a1 depending
11 * on what value we'd like to return when one of the operands is NaN.
13 * See OP_CMPL_FLOAT for an explanation.
15 * For: cmpl-double, cmpg-double
17 /* op vAA, vBB, vCC */
19 FETCH(a0, 1) # a0 <- CCBB
20 and rOBJ, a0, 255 # s0 <- BB
21 srl rBIX, a0, 8 # t0 <- CC
22 EAS2(rOBJ, rFP, rOBJ) # s0 <- &fp[BB]
23 EAS2(rBIX, rFP, rBIX) # t0 <- &fp[CC]
25 LOAD64(rARG0, rARG1, rOBJ) # a0/a1 <- vBB/vBB+1
26 LOAD64(rARG2, rARG3, rBIX) # a2/a3 <- vCC/vCC+1
27 JAL(__eqdf2) # cmp <=: C clear if <, Z set if eq
29 beqz v0, ${opcode}_finish
31 LOAD64(rARG0, rARG1, rOBJ) # a0/a1 <- vBB/vBB+1
32 LOAD64(rARG2, rARG3, rBIX) # a2/a3 <- vCC/vCC+1
35 bltz v0, ${opcode}_finish
36 LOAD64(rARG0, rARG1, rOBJ) # a0/a1 <- vBB/vBB+1
39 LOAD64_F(fs0, fs0f, rOBJ)
40 LOAD64_F(fs1, fs1f, rBIX)
41 c.olt.d fcc0, fs0, fs1
43 bc1t fcc0, ${opcode}_finish
44 c.olt.d fcc0, fs1, fs0
46 bc1t fcc0, ${opcode}_finish
49 bc1t fcc0, ${opcode}_finish
60 LOAD64(rARG2, rARG3, rBIX) # a2/a3 <- vCC/vCC+1
61 JAL(__gtdf2) # fallthru
62 li rTEMP, 1 # rTEMP = 1 if v0 != 0
63 blez v0, ${opcode}_nan # fall thru for finish
68 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
69 GET_INST_OPCODE(t0) # extract opcode from rINST
70 SET_VREG_GOTO(rTEMP, rOBJ, t0) # vAA <- rTEMP