# limitations under the License.
#
-# Configuration for ARMv4 architecture targets. This is largely pulled
-# from the ARMv5 sources, but we can't use certain instructions introduced
+# Configuration for ARMv4T architecture targets. This is largely pulled
+# from the ARMv5TE sources, but we can't use certain instructions introduced
# in ARMv5 (BLX, CLZ, LDC2, MCR2, MRC2, STC2) or ARMv5TE (PLD, LDRD, MCRR,
# MRRC, QADD, QDADD, QDSUB, QSUB, SMLA, SMLAL, SMLAW, SMUL, SMULW, STRD).
#
# opcode list; argument to op-start is default directory
op-start armv5te
- op OP_AGET_WIDE armv4
- op OP_APUT_WIDE armv4
- op OP_IGET_WIDE armv4
- op OP_IGET_WIDE_QUICK armv4
- op OP_IPUT_WIDE armv4
- op OP_IPUT_WIDE_QUICK armv4
- op OP_SGET_WIDE armv4
- op OP_SPUT_WIDE armv4
+ op OP_AGET_WIDE armv4t
+ op OP_APUT_WIDE armv4t
+ op OP_IGET_WIDE armv4t
+ op OP_IGET_WIDE_QUICK armv4t
+ op OP_IPUT_WIDE armv4t
+ op OP_IPUT_WIDE_QUICK armv4t
+ op OP_SGET_WIDE armv4t
+ op OP_SPUT_WIDE armv4t
op-end
# "helper" code for C; include if you use any of the C stubs (this generates
/*
- * This file was generated automatically by gen-mterp.py for 'armv4'.
+ * This file was generated automatically by gen-mterp.py for 'armv4t'.
*
* --> DO NOT EDIT <--
*/
/* ------------------------------ */
.balign 64
.L_OP_AGET_WIDE: /* 0x45 */
-/* File: armv4/OP_AGET_WIDE.S */
+/* File: armv4t/OP_AGET_WIDE.S */
/*
* Array get, 64 bits. vAA <- vBB[vCC].
*
/* ------------------------------ */
.balign 64
.L_OP_APUT_WIDE: /* 0x4c */
-/* File: armv4/OP_APUT_WIDE.S */
+/* File: armv4t/OP_APUT_WIDE.S */
/*
* Array put, 64 bits. vBB[vCC] <- vAA.
*/
/* ------------------------------ */
.balign 64
.L_OP_IGET_WIDE: /* 0x53 */
-/* File: armv4/OP_IGET_WIDE.S */
+/* File: armv4t/OP_IGET_WIDE.S */
/*
* Wide 32-bit instance field get.
*/
/* ------------------------------ */
.balign 64
.L_OP_IPUT_WIDE: /* 0x5a */
-/* File: armv4/OP_IPUT_WIDE.S */
+/* File: armv4t/OP_IPUT_WIDE.S */
/* iput-wide vA, vB, field@CCCC */
mov r0, rINST, lsr #12 @ r0<- B
ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex
/* ------------------------------ */
.balign 64
.L_OP_SGET_WIDE: /* 0x61 */
-/* File: armv4/OP_SGET_WIDE.S */
+/* File: armv4t/OP_SGET_WIDE.S */
/*
* 64-bit SGET handler.
*/
/* ------------------------------ */
.balign 64
.L_OP_SPUT_WIDE: /* 0x68 */
-/* File: armv4/OP_SPUT_WIDE.S */
+/* File: armv4t/OP_SPUT_WIDE.S */
/*
* 64-bit SPUT handler.
*/
/* ------------------------------ */
.balign 64
.L_OP_IGET_WIDE_QUICK: /* 0xf3 */
-/* File: armv4/OP_IGET_WIDE_QUICK.S */
+/* File: armv4t/OP_IGET_WIDE_QUICK.S */
/* iget-wide-quick vA, vB, offset@CCCC */
mov r2, rINST, lsr #12 @ r2<- B
GET_VREG(r3, r2) @ r3<- object we're operating on
/* ------------------------------ */
.balign 64
.L_OP_IPUT_WIDE_QUICK: /* 0xf6 */
-/* File: armv4/OP_IPUT_WIDE_QUICK.S */
+/* File: armv4t/OP_IPUT_WIDE_QUICK.S */
/* iput-wide-quick vA, vB, offset@CCCC */
mov r0, rINST, lsr #8 @ r0<- A(+)
mov r1, rINST, lsr #12 @ r1<- B