1 # Chelsio T6 Factory Default configuration file.
3 # Copyright (C) 2014-2015 Chelsio Communications. All rights reserved.
5 # DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES. MODIFICATION OF THIS FILE
6 # WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE
10 # This file provides the default, power-on configuration for 2-port T6-based
11 # adapters shipped from the factory. These defaults are designed to address
12 # the needs of the vast majority of Terminator customers. The basic idea is to
13 # have a default configuration which allows a customer to plug a Terminator
14 # adapter in and have it work regardless of OS, driver or application except in
15 # the most unusual and/or demanding customer applications.
17 # Many of the Terminator resources which are described by this configuration
18 # are finite. This requires balancing the configuration/operation needs of
19 # device drivers across OSes and a large number of customer application.
21 # Some of the more important resources to allocate and their constaints are:
22 # 1. Virtual Interfaces: 256.
23 # 2. Ingress Queues with Free Lists: 1024.
24 # 3. Egress Queues: 128K.
25 # 4. MSI-X Vectors: 1088.
26 # 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
27 # address matching on Ingress Packets.
29 # Some of the important OS/Driver resource needs are:
30 # 6. Some OS Drivers will manage all resources through a single Physical
31 # Function (currently PF4 but it could be any Physical Function).
32 # 7. Some OS Drivers will manage different ports and functions (NIC,
33 # storage, etc.) on different Physical Functions. For example, NIC
34 # functions for ports 0-1 on PF0-1, FCoE on PF4, iSCSI on PF5, etc.
36 # Some of the customer application needs which need to be accommodated:
37 # 8. Some customers will want to support large CPU count systems with
38 # good scaling. Thus, we'll need to accommodate a number of
39 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
40 # to be involved per port and per application function. For example,
41 # in the case where all ports and application functions will be
42 # managed via a single Unified PF and we want to accommodate scaling up
43 # to 8 CPUs, we would want:
46 # 3 application functions (NIC, FCoE, iSCSI) per port *
47 # 16 Ingress Queue/MSI-X Vectors per application function
49 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
50 # (Plus a few for Firmware Event Queues, etc.)
52 # 9. Some customers will want to use PCI-E SR-IOV Capability to allow Virtual
53 # Machines to directly access T6 functionality via SR-IOV Virtual Functions
54 # and "PCI Device Passthrough" -- this is especially true for the NIC
55 # application functionality.
59 # Global configuration settings.
62 rss_glb_config_mode = basicvirtual
63 rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp
66 pl_timeout_value = 200 # the timeout value in units of us
68 # The following Scatter Gather Engine (SGE) settings assume a 4KB Host
69 # Page Size and a 64B L1 Cache Line Size. It programs the
70 # EgrStatusPageSize and IngPadBoundary to 64B and the PktShift to 2.
71 # If a Master PF Driver finds itself on a machine with different
72 # parameters, then the Master PF Driver is responsible for initializing
73 # these parameters to appropriate values.
76 # 1. The Free List Buffer Sizes below are raw and the firmware will
77 # round them up to the Ingress Padding Boundary.
78 # 2. The SGE Timer Values below are expressed below in microseconds.
79 # The firmware will convert these values to Core Clock Ticks when
80 # it processes the configuration parameters.
82 reg[0x1008] = 0x40800/0x21c70 # SGE_CONTROL
83 reg[0x100c] = 0x22222222 # SGE_HOST_PAGE_SIZE
84 reg[0x10a0] = 0x01040810 # SGE_INGRESS_RX_THRESHOLD
85 reg[0x1044] = 4096 # SGE_FL_BUFFER_SIZE0
86 reg[0x1048] = 65536 # SGE_FL_BUFFER_SIZE1
87 reg[0x104c] = 1536 # SGE_FL_BUFFER_SIZE2
88 reg[0x1050] = 9024 # SGE_FL_BUFFER_SIZE3
89 reg[0x1054] = 9216 # SGE_FL_BUFFER_SIZE4
90 reg[0x1058] = 2048 # SGE_FL_BUFFER_SIZE5
91 reg[0x105c] = 128 # SGE_FL_BUFFER_SIZE6
92 reg[0x1060] = 8192 # SGE_FL_BUFFER_SIZE7
93 reg[0x1064] = 16384 # SGE_FL_BUFFER_SIZE8
95 sge_timer_value = 5, 10, 20, 50, 100, 200 # SGE_TIMER_VALUE* in usecs
96 reg[0x10c4] = 0x20000000/0x20000000 # GK_CONTROL, enable 5th thread
98 # Set the SGE Doorbell Queue Timer "tick" to 50us and initialize
99 # the Timer Table to a default set of values (which are multiples
100 # of the Timer Tick). Note that the set of Tick Multipliers are
101 # NOT sorted. The Host Drivers are expected to pick amongst them
102 # for (Tick * Multiplier[i]) values which most closely match the Host
103 # Drivers' needs. Also, most Host Drivers will be default start
104 # start with (Tick * Multiplier[0]), so this gives us some flexibility
105 # in terms of picking a Tick and a default Multiplier somewhere in
106 # the middle of the achievable set of (Tick * Multiplier[i]) values.
107 # Thus, the below select for 150us by this default.
109 sge_dbq_timertick = 50
110 sge_dbq_timer = 3, 2, 1, 5, 7, 9, 12, 16
112 # enable TP_OUT_CONFIG.IPIDSPLITMODE
113 reg[0x7d04] = 0x00010000/0x00010000
115 reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT
117 #Tick granularities in kbps
118 tsch_ticks = 100000, 10000, 1000, 10
120 # TP_VLAN_PRI_MAP to select filter tuples and enable ServerSram
121 # filter control: compact, fcoemask
122 # server sram : srvrsram
123 # filter tuples : fragmentation, mpshittype, macmatch, ethertype,
124 # protocol, tos, vlan, vnic_id, port, fcoe
125 # valid filterModes are described the Terminator 5 Data Book
126 # vnicMode = pf_vf #default. Other values are outer_vlan, encapsulation
127 filterMode = fcoemask, srvrsram, fragmentation, mpshittype, protocol, vlan, port, fcoe
129 # filter tuples enforced in LE active region (equal to or subset of filterMode)
130 filterMask = protocol, fcoe
132 # Percentage of dynamic memory (in either the EDRAM or external MEM)
133 # to use for TP RX payload
136 # TP RX payload page size
137 tp_pmrx_pagesize = 64K
139 # TP number of RX channels
140 tp_nrxch = 0 # 0 (auto) = 1
142 # Percentage of dynamic memory (in either the EDRAM or external MEM)
143 # to use for TP TX payload
146 # TP TX payload page size
147 tp_pmtx_pagesize = 64K
149 # TP number of TX channels
150 tp_ntxch = 0 # 0 (auto) = equal number of ports
153 tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600
155 # enable TP_OUT_CONFIG.IPIDSPLITMODE and CRXPKTENC
156 reg[0x7d04] = 0x00010008/0x00010008
159 reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable
162 reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError
165 reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6
167 # ULPRX iSCSI Page Sizes
168 reg[0x19168] = 0x04020100 # 64K, 16K, 8K and 4K
171 reg[0x19c04] = 0x00000000/0x00440000 # LE Server SRAM disabled
172 # LE IPv4 compression disabled
174 reg[0x19c28] = 0x00800000/0x01f00000 # LE Hash bucket size 8,
177 reg[0x8dc0] = 0x00000104/0x00000104 # Enable ITT on PI err
178 # Enable more error msg for ...
181 # ULP_RX_MISC_FEATURE_ENABLE
182 #reg[0x1925c] = 0x01003400/0x01003400 # iscsi tag pi bit
183 # Enable offset decrement after ...
184 # PI extraction and before DDP
185 # ulp insert pi source info in DIF
186 # iscsi_eff_offset_en
188 #Enable iscsi completion moderation feature
189 reg[0x1925c] = 0x000041c0/0x000031c0 # Enable offset decrement after
190 # PI extraction and before DDP.
191 # ulp insert pi source info in
193 # Enable iscsi hdr cmd mode.
194 # iscsi force cmd mode.
195 # Enable iscsi cmp mode.
197 #mc_mode_brc[0] = 1 # mc0 - 1: enable BRC, 0: enable RBC, 2: enable BRBC
200 hma_size = 92 # Size (in MBs) of host memory expected
201 hma_regions = stag,pbl,rq # What all regions to place in host memory
203 # Some "definitions" to make the rest of this a bit more readable. We support
204 # 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets"
205 # per function per port ...
207 # NMSIX = 1088 # available MSI-X Vectors
208 # NVI = 256 # available Virtual Interfaces
209 # NMPSTCAM = 336 # MPS TCAM entries
212 # NCPUS = 16 # CPUs we want to support scalably
213 # NFUNCS = 3 # functions per port (NIC, FCoE, iSCSI)
215 # Breakdown of Virtual Interface/Queue/Interrupt resources for the "Unified
216 # PF" which many OS Drivers will use to manage most or all functions.
218 # Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can
219 # use Forwarded Interrupt Ingress Queues. For these latter, an Ingress Queue
220 # would be created and the Queue ID of a Forwarded Interrupt Ingress Queue
221 # will be specified as the "Ingress Queue Asynchronous Destination Index."
222 # Thus, the number of MSI-X Vectors assigned to the Unified PF will be less
223 # than or equal to the number of Ingress Queues ...
225 # NVI_NIC = 4 # NIC access to NPORTS
226 # NFLIQ_NIC = 32 # NIC Ingress Queues with Free Lists
227 # NETHCTRL_NIC = 32 # NIC Ethernet Control/TX Queues
228 # NEQ_NIC = 64 # NIC Egress Queues (FL, ETHCTRL/TX)
229 # NMPSTCAM_NIC = 16 # NIC MPS TCAM Entries (NPORTS*4)
230 # NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ)
232 # NVI_OFLD = 0 # Offload uses NIC function to access ports
233 # NFLIQ_OFLD = 16 # Offload Ingress Queues with Free Lists
234 # NETHCTRL_OFLD = 0 # Offload Ethernet Control/TX Queues
235 # NEQ_OFLD = 16 # Offload Egress Queues (FL)
236 # NMPSTCAM_OFLD = 0 # Offload MPS TCAM Entries (uses NIC's)
237 # NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ)
239 # NVI_RDMA = 0 # RDMA uses NIC function to access ports
240 # NFLIQ_RDMA = 4 # RDMA Ingress Queues with Free Lists
241 # NETHCTRL_RDMA = 0 # RDMA Ethernet Control/TX Queues
242 # NEQ_RDMA = 4 # RDMA Egress Queues (FL)
243 # NMPSTCAM_RDMA = 0 # RDMA MPS TCAM Entries (uses NIC's)
244 # NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ)
246 # NEQ_WD = 128 # Wire Direct TX Queues and FLs
247 # NETHCTRL_WD = 64 # Wire Direct TX Queues
248 # NFLIQ_WD = 64 ` # Wire Direct Ingress Queues with Free Lists
250 # NVI_ISCSI = 4 # ISCSI access to NPORTS
251 # NFLIQ_ISCSI = 4 # ISCSI Ingress Queues with Free Lists
252 # NETHCTRL_ISCSI = 0 # ISCSI Ethernet Control/TX Queues
253 # NEQ_ISCSI = 4 # ISCSI Egress Queues (FL)
254 # NMPSTCAM_ISCSI = 4 # ISCSI MPS TCAM Entries (NPORTS)
255 # NMSIX_ISCSI = 4 # ISCSI MSI-X Interrupt Vectors (FLIQ)
257 # NVI_FCOE = 4 # FCOE access to NPORTS
258 # NFLIQ_FCOE = 34 # FCOE Ingress Queues with Free Lists
259 # NETHCTRL_FCOE = 32 # FCOE Ethernet Control/TX Queues
260 # NEQ_FCOE = 66 # FCOE Egress Queues (FL)
261 # NMPSTCAM_FCOE = 32 # FCOE MPS TCAM Entries (NPORTS)
262 # NMSIX_FCOE = 34 # FCOE MSI-X Interrupt Vectors (FLIQ)
264 # Two extra Ingress Queues per function for Firmware Events and Forwarded
265 # Interrupts, and two extra interrupts per function for Firmware Events (or a
266 # Forwarded Interrupt Queue) and General Interrupts per function.
268 # NFLIQ_EXTRA = 6 # "extra" Ingress Queues 2*NFUNCS (Firmware and
269 # # Forwarded Interrupts
270 # NMSIX_EXTRA = 6 # extra interrupts 2*NFUNCS (Firmware and
271 # # General Interrupts
273 # Microsoft HyperV resources. The HyperV Virtual Ingress Queues will have
274 # their interrupts forwarded to another set of Forwarded Interrupt Queues.
276 # NVI_HYPERV = 16 # VMs we want to support
277 # NVIIQ_HYPERV = 2 # Virtual Ingress Queues with Free Lists per VM
278 # NFLIQ_HYPERV = 40 # VIQs + NCPUS Forwarded Interrupt Queues
279 # NEQ_HYPERV = 32 # VIQs Free Lists
280 # NMPSTCAM_HYPERV = 16 # MPS TCAM Entries (NVI_HYPERV)
281 # NMSIX_HYPERV = 8 # NCPUS Forwarded Interrupt Queues
283 # Adding all of the above Unified PF resource needs together: (NIC + OFLD +
284 # RDMA + ISCSI + FCOE + EXTRA + HYPERV)
287 # NFLIQ_UNIFIED = 106
288 # NETHCTRL_UNIFIED = 32
290 # NMPSTCAM_UNIFIED = 40
292 # The sum of all the MSI-X resources above is 74 MSI-X Vectors but we'll round
293 # that up to 128 to make sure the Unified PF doesn't run out of resources.
295 # NMSIX_UNIFIED = 128
297 # The Storage PFs could need up to NPORTS*NCPUS + NMSIX_EXTRA MSI-X Vectors
298 # which is 34 but they're probably safe with 32.
302 # Note: The UnifiedPF is PF4 which doesn't have any Virtual Functions
303 # associated with it. Thus, the MSI-X Vector allocations we give to the
304 # UnifiedPF aren't inherited by any Virtual Functions. As a result we can
305 # provision many more Virtual Functions than we can if the UnifiedPF were
309 # All of the below PCI-E parameters are actually stored in various *_init.txt
310 # files. We include them below essentially as comments.
312 # For PF0-3 we assign 8 vectors each for NIC Ingress Queues of the associated
315 # For PF4, the Unified PF, we give it an MSI-X Table Size as outlined above.
317 # For PF5-6 we assign enough MSI-X Vectors to support FCoE and iSCSI
318 # storage applications across all four possible ports.
320 # Additionally, since the UnifiedPF isn't one of the per-port Physical
321 # Functions, we give the UnifiedPF and the PF0-3 Physical Functions
322 # different PCI Device IDs which will allow Unified and Per-Port Drivers
323 # to directly select the type of Physical Function to which they wish to be
326 # Note that the actual values used for the PCI-E Intelectual Property will be
327 # 1 less than those below since that's the way it "counts" things. For
328 # readability, we use the number we actually mean ...
330 # PF0_INT = 8 # NCPUS
331 # PF1_INT = 8 # NCPUS
332 # PF0_3_INT = 32 # PF0_INT + PF1_INT + PF2_INT + PF3_INT
334 # PF4_INT = 128 # NMSIX_UNIFIED
335 # PF5_INT = 32 # NMSIX_STORAGE
336 # PF6_INT = 32 # NMSIX_STORAGE
337 # PF7_INT = 0 # Nothing Assigned
338 # PF4_7_INT = 192 # PF4_INT + PF5_INT + PF6_INT + PF7_INT
340 # PF0_7_INT = 224 # PF0_3_INT + PF4_7_INT
342 # With the above we can get 17 VFs/PF0-3 (limited by 336 MPS TCAM entries)
343 # but we'll lower that to 16 to make our total 64 and a nice power of 2 ...
348 # For those OSes which manage different ports on different PFs, we need
349 # only enough resources to support a single port's NIC application functions
350 # on PF0-3. The below assumes that we're only doing NIC with NCPUS "Queue
351 # Sets" for ports 0-3. The FCoE and iSCSI functions for such OSes will be
352 # managed on the "storage PFs" (see below).
355 nvf = 16 # NVF on this function
356 wx_caps = all # write/execute permissions for all commands
357 r_caps = all # read permissions for all commands
359 niqflint = 8 # NCPUS "Queue Sets"
360 nethctrl = 8 # NCPUS "Queue Sets"
361 neq = 16 # niqflint + nethctrl Egress Queues
362 nexactf = 8 # number of exact MPSTCAM MAC filters
363 cmask = all # access to all channels
364 pmask = 0x1 # access to only one port
368 nvf = 16 # NVF on this function
369 wx_caps = all # write/execute permissions for all commands
370 r_caps = all # read permissions for all commands
372 niqflint = 8 # NCPUS "Queue Sets"
373 nethctrl = 8 # NCPUS "Queue Sets"
374 neq = 16 # niqflint + nethctrl Egress Queues
375 nexactf = 8 # number of exact MPSTCAM MAC filters
376 cmask = all # access to all channels
377 pmask = 0x2 # access to only one port
380 nvf = 16 # NVF on this function
381 wx_caps = all # write/execute permissions for all commands
382 r_caps = all # read permissions for all commands
384 niqflint = 8 # NCPUS "Queue Sets"
385 nethctrl = 8 # NCPUS "Queue Sets"
386 neq = 16 # niqflint + nethctrl Egress Queues
387 nexactf = 8 # number of exact MPSTCAM MAC filters
388 cmask = all # access to all channels
389 pmask = 0x4 # access to only one port
392 nvf = 16 # NVF on this function
393 wx_caps = all # write/execute permissions for all commands
394 r_caps = all # read permissions for all commands
396 niqflint = 8 # NCPUS "Queue Sets"
397 nethctrl = 8 # NCPUS "Queue Sets"
398 neq = 16 # niqflint + nethctrl Egress Queues
399 nexactf = 8 # number of exact MPSTCAM MAC filters
400 cmask = all # access to all channels
401 pmask = 0x8 # access to only one port
404 # Some OS Drivers manage all application functions for all ports via PF4.
405 # Thus we need to provide a large number of resources here. For Egress
406 # Queues we need to account for both TX Queues as well as Free List Queues
407 # (because the host is responsible for producing Free List Buffers for the
408 # hardware to consume).
411 wx_caps = all # write/execute permissions for all commands
412 r_caps = all # read permissions for all commands
413 nvi = 28 # NVI_UNIFIED
414 niqflint = 218 # NFLIQ_UNIFIED + NLFIQ_WD + NFLIQ_CRYPTO (32)
415 nethctrl = 116 # NETHCTRL_UNIFIED + NETHCTRL_WD + ncrypto_lookaside
416 neq = 256 # NEQ_UNIFIED + NEQ_WD
418 nexactf = 40 # NMPSTCAM_UNIFIED
420 cmask = all # access to all channels
421 pmask = all # access to all four ports ...
422 nethofld = 1024 # number of user mode ethernet flow contexts
423 ncrypto_lookaside = 16 # Number of lookaside flow contexts
424 nclip = 320 # number of clip region entries
425 nfilter = 496 # number of filter region entries
426 nserver = 496 # number of server region entries
427 nhash = 12288 # number of hash region entries
428 nhpfilter = 64 # number of high priority filter region entries
429 protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif, tlskeys, crypto_lookaside, ipsec_inline, nic_hashfilter
434 tp_tls_mxrxsize = 17408 # 16384 + 1024, governs max rx data, pm max xfer len, rx coalesce sizes
440 # We have FCoE and iSCSI storage functions on PF5 and PF6 each of which may
441 # need to have Virtual Interfaces on each of the four ports with up to NCPUS
445 wx_caps = all # write/execute permissions for all commands
446 r_caps = all # read permissions for all commands
448 niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA
449 nethctrl = 32 # NPORTS*NCPUS
450 neq = 64 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX)
451 nexactf = 16 # (NPORTS *(no of snmc grp + 1 hw mac) + 1 anmc grp)) rounded to 16.
452 cmask = all # access to all channels
453 pmask = all # access to all four ports ...
458 protocol = iscsi_initiator_fofld
462 iscsi_nconn_per_session = 1
463 iscsi_ninitiator_instance = 64
467 wx_caps = all # write/execute permissions for all commands
468 r_caps = all # read permissions for all commands
470 niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA
471 nethctrl = 32 # NPORTS*NCPUS
472 neq = 66 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) + 2 (EXTRA)
473 nexactf = 32 # NPORTS + adding 28 exact entries for FCoE
474 # which is OK since < MIN(SUM PF0..3, PF4)
475 # and we never load PF0..3 and PF4 concurrently
476 cmask = all # access to all channels
477 pmask = all # access to all four ports ...
480 protocol = fcoe_initiator
487 # The following function, 1023, is not an actual PCIE function but is used to
488 # configure and reserve firmware internal resources that come from the global
492 wx_caps = all # write/execute permissions for all commands
493 r_caps = all # read permissions for all commands
494 nvi = 4 # NVI_UNIFIED
495 cmask = all # access to all channels
496 pmask = all # access to all four ports ...
497 nexactf = 8 # NPORTS + DCBX +
498 nfilter = 16 # number of filter region entries
501 # For Virtual functions, we only allow NIC functionality and we only allow
502 # access to one port (1 << PF). Note that because of limitations in the
503 # Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL
504 # and GTS registers, the number of Ingress and Egress Queues must be a power
507 [function "0/*"] # NVF
508 wx_caps = 0x82 # DMAQ | VF
509 r_caps = 0x86 # DMAQ | VF | PORT
511 niqflint = 6 # 2 "Queue Sets" + NXIQ
512 nethctrl = 4 # 2 "Queue Sets"
513 neq = 8 # 2 "Queue Sets" * 2
515 cmask = all # access to all channels
516 pmask = 0x1 # access to only one port ...
519 [function "1/*"] # NVF
520 wx_caps = 0x82 # DMAQ | VF
521 r_caps = 0x86 # DMAQ | VF | PORT
523 niqflint = 6 # 2 "Queue Sets" + NXIQ
524 nethctrl = 4 # 2 "Queue Sets"
525 neq = 8 # 2 "Queue Sets" * 2
527 cmask = all # access to all channels
528 pmask = 0x2 # access to only one port ...
530 [function "2/*"] # NVF
531 wx_caps = 0x82 # DMAQ | VF
532 r_caps = 0x86 # DMAQ | VF | PORT
534 niqflint = 6 # 2 "Queue Sets" + NXIQ
535 nethctrl = 4 # 2 "Queue Sets"
536 neq = 8 # 2 "Queue Sets" * 2
538 cmask = all # access to all channels
539 pmask = 0x1 # access to only one port ...
542 [function "3/*"] # NVF
543 wx_caps = 0x82 # DMAQ | VF
544 r_caps = 0x86 # DMAQ | VF | PORT
546 niqflint = 6 # 2 "Queue Sets" + NXIQ
547 nethctrl = 4 # 2 "Queue Sets"
548 neq = 8 # 2 "Queue Sets" * 2
550 cmask = all # access to all channels
551 pmask = 0x2 # access to only one port ...
553 # MPS features a 196608 bytes ingress buffer that is used for ingress buffering
554 # for packets from the wire as well as the loopback path of the L2 switch. The
555 # folling params control how the buffer memory is distributed and the L2 flow
558 # bg_mem: %-age of mem to use for port/buffer group
559 # lpbk_mem: %-age of port/bg mem to use for loopback
560 # hwm: high watermark; bytes available when starting to send pause
561 # frames (in units of 0.1 MTU)
562 # lwm: low watermark; bytes remaining when sending 'unpause' frame
563 # (in inuits of 0.1 MTU)
564 # dwm: minimum delta between high and low watermark (in units of 100
568 dcb = ppp, dcbx # configure for DCB PPP and enable DCBX offload
574 dcb_app_tlv[0] = 0x8906, ethertype, 3
575 dcb_app_tlv[1] = 0x8914, ethertype, 3
576 dcb_app_tlv[2] = 3260, socketnum, 5
585 dcb_app_tlv[0] = 0x8906, ethertype, 3
586 dcb_app_tlv[1] = 0x8914, ethertype, 3
587 dcb_app_tlv[2] = 3260, socketnum, 5
591 checksum = 0x14a022cd
593 # Total resources used by above allocations:
594 # Virtual Interfaces: 104
595 # Ingress Queues/w Free Lists and Interrupts: 526
597 # MPS TCAM Entries: 336
599 # Virtual Functions: 64