TODO: Update entries in TODO list

diff --git a/TODO b/TODO
index 09832a9..a0b53ce 100644 (file)
--- a/TODO
+++ b/TODO
@@ -14,36 +14,41 @@ Background
   Higher complexity tasks should be refined into several lower complexity tasks
   once the task is better understood.
 
-NEON instruction set
-====================
+Encoder optimizations
+=====================
 
-- The neon optimization code is split in two parts. Sample reordering and blocks
-encoding. There is a neon optimization for encoding SBC. But mSBC is not
-supported by this optimizer because the reordering has been specifically for
-mSBC.
+- Currently, only the decoder is optimized to take advantage of advanced
+  processor instruction sets. In use cases like HFP 1.6, optimizing the
+  encoder will bring a significant latency, power and performance advantage.
+  For example, the MMX encoder is 3 to 6 time faster than the SIMD encoder.
+
+  Priority: High
+  Complexity: C8
+
+- Use a log2 table for byte integer scale factors calculation (sum log2
+  results for high and low bytes) fill bitpool by 16 bits instead of one
+  at a time in bits allocation/bitpool generation port to the dsp
+
+  Priority: Medium
+  Complexity: C2
+
+- The neon optimization code is split in two parts. Sample reordering and
+  blocks encoding. There is a neon optimization for encoding SBC. But mSBC
+  is not supported by this optimizer because the reordering has been
+  specifically for mSBC.
 
   Priority: Low
   Complexity: C2
 
-SSE instruction set
-===================
+Decoder optimizations
+=====================
 
-- The decoder is optimized to take advantage of advanced processor instruction
-sets. Currently implemented are MMX, arm neon, arm v6 and iwmmxt. SSE3 is
-is available since almost 10 years now, on a large range of Intel processors.
-It should be interesting to implement it and to compare with MMX implementation
-on Intel processors.
+- The decoder is optimized to take advantage of advanced processor
+  instruction sets. Currently implemented are MMX, arm neon, arm v6
+  and iwmmxt. SSE3 is available since almost 10 years now, on a large
+  range of Intel processors. It should be interesting to implement it
+  and to compare with MMX implementation on Intel processors.
 
   Priority: Medium
   Complexity: C4
 
-Decoder improvements
-====================
-
-- Currently, only the decoder is optimized to take advantage of advanced
-processor instruction sets. In use cases like HFP 1.6, optimizing the encoder
-will bring a significant latency, power and performance advantage. For exemple,
-the MMX encoder is 3 to 6 time faster than the SIMD encoder.
-
-  Priority: High
-  Complexity: C8

diff --git a/sbc/sbc.c b/sbc/sbc.c
index f330602..51bca55 100644 (file)
--- a/sbc/sbc.c
+++ b/sbc/sbc.c
@@ -25,14 +25,6 @@
  *
  */
 
-/* todo items:
-
-  use a log2 table for byte integer scale factors calculation (sum log2 results
-  for high and low bytes) fill bitpool by 16 bits instead of one at a time in
-  bits allocation/bitpool generation port to the dsp
-
-*/
-
 #ifdef HAVE_CONFIG_H
 #include <config.h>
 #endif