1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 ******************************************************************************/
21 #ifndef __PHYDMRAINFO_H__
22 #define __PHYDMRAINFO_H__
24 /*#define RAINFO_VERSION "2.0" //2014.11.04*/
25 /*#define RAINFO_VERSION "3.0" //2015.01.13 Dino*/
26 /*#define RAINFO_VERSION "3.1" //2015.01.14 Dino*/
27 #define RAINFO_VERSION "3.2" /*2015.01.14 Dino*/
29 #define HIGH_RSSI_THRESH 50
30 #define LOW_RSSI_THRESH 20
32 #define ACTIVE_TP_THRESHOLD 150
33 #define RA_RETRY_DESCEND_NUM 2
34 #define RA_RETRY_LIMIT_LOW 4
35 #define RA_RETRY_LIMIT_HIGH 32
37 #define PHYDM_IC_8051_SERIES (ODM_RTL8881A|ODM_RTL8812|ODM_RTL8821|ODM_RTL8192S|ODM_RTL8192C|ODM_RTL8192D|ODM_RTL8723A|ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8703B|ODM_RTL8188F)
38 #define PHYDM_IC_3081_SERIES (ODM_RTL8814A|ODM_RTL8821B|ODM_RTL8822B)
40 #define RAINFO_BE_RX_STATE BIT0 // 1:RX //ULDL
41 #define RAINFO_STBC_STATE BIT1
42 //#define RAINFO_LDPC_STATE BIT2
43 #define RAINFO_NOISY_STATE BIT2 // set by Noisy_Detection
44 #define RAINFO_SHURTCUT_STATE BIT3
45 #define RAINFO_SHURTCUT_FLAG BIT4
46 #define RAINFO_INIT_RSSI_RATE_STATE BIT5
47 #define RAINFO_BF_STATE BIT6
48 #define RAINFO_BE_TX_STATE BIT7 // 1:TX
50 #define RA_MASK_CCK 0xf
51 #define RA_MASK_OFDM 0xff0
52 #define RA_MASK_HT1SS 0xff000
53 #define RA_MASK_HT2SS 0xff00000
54 /*#define RA_MASK_MCS3SS */
55 #define RA_MASK_HT4SS 0xff0
56 #define RA_MASK_VHT1SS 0x3ff000
57 #define RA_MASK_VHT2SS 0xffc00000
59 #if(DM_ODM_SUPPORT_TYPE == ODM_AP)
60 #define EXT_RA_INFO_SUPPORT_IC (ODM_RTL8881A |ODM_RTL8192E |ODM_RTL8812 |ODM_RTL8814A|ODM_RTL8822B)
61 #define RA_FIRST_MACID 1
62 #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
63 #define EXT_RA_INFO_SUPPORT_IC (ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8723B | ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8703B)
64 #define RA_FIRST_MACID 0
65 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
66 /*#define EXT_RA_INFO_SUPPORT_IC (ODM_RTL8192E|ODM_RTL8812|ODM_RTL8821|ODM_RTL8723B|ODM_RTL8814A|ODM_RTL8822B|ODM_RTL8703B) */
67 #define RA_FIRST_MACID 0
71 #define AP_InitRateAdaptiveState ODM_RateAdaptiveStateApInit
73 #define DM_RATR_STA_INIT 0
74 #define DM_RATR_STA_HIGH 1
75 #define DM_RATR_STA_MIDDLE 2
76 #define DM_RATR_STA_LOW 3
77 #if(DM_ODM_SUPPORT_TYPE & ODM_AP)
78 #define DM_RATR_STA_ULTRA_LOW 4
81 #define DM_RA_RATE_UP 1
82 #define DM_RA_RATE_DOWN 2
84 typedef enum _phydm_arfr_num {
91 } PHYDM_RA_ARFR_NUM_E;
93 typedef enum _Phydm_ra_dbg_para {
94 RADBG_RTY_PENALTY = 1, //u8
97 RADBG_TRATE_UP_TABLE = 4,
98 RADBG_TRATE_DOWN_TABLE = 5,
99 RADBG_TRYING_NECESSARY = 6,
100 RADBG_TDROPING_NECESSARY = 7,
101 RADBG_RATE_UP_RTY_RATIO = 8, //u8
102 RADBG_RATE_DOWN_RTY_RATIO = 9, //u8
104 RADBG_DEBUG_MONITOR1 = 0xc,
105 RADBG_DEBUG_MONITOR2 = 0xd,
106 RADBG_DEBUG_MONITOR3 = 0xe,
107 RADBG_DEBUG_MONITOR4 = 0xf,
109 } PHYDM_RA_DBG_PARA_E;
112 #if (RATE_ADAPTIVE_SUPPORT == 1)//88E RA
113 typedef struct _ODM_RA_Info_ {
132 u1Byte RAWaitingCounter;
133 u1Byte RAPendingCounter;
134 #if 1 //POWER_TRAINING_ACTIVE == 1 // For compile pass only~!
135 u1Byte PTActive; // on or off
136 u1Byte PTTryState; // 0 trying state, 1 for decision state
137 u1Byte PTStage; // 0~6
138 u1Byte PTStopCount; //Stop PT counter
139 u1Byte PTPreRate; // if rate change do PT
140 u1Byte PTPreRssi; // if RSSI change 5% do PT
141 u1Byte PTModeSS; // decide whitch rate should do PT
142 u1Byte RAstage; // StageRA, decide how many times RA will be done between PT
143 u1Byte PTSmoothFactor;
145 #if (DM_ODM_SUPPORT_TYPE == ODM_AP) && ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
146 u1Byte RateDownCounter;
147 u1Byte RateUpCounter;
148 u1Byte RateDirection;
150 u1Byte BoundingCounter;
151 u1Byte BoundingLearningTime;
152 u1Byte RateDownStartTime;
154 } ODM_RA_INFO_T, *PODM_RA_INFO_T;
158 typedef struct _Rate_Adaptive_Table_ {
160 #if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
161 BOOLEAN PT_collision_pre;
164 #if (defined(CONFIG_RA_DBG_CMD))
165 BOOLEAN is_ra_dbg_init;
167 u1Byte RTY_P[ODM_NUM_RATE_IDX];
168 u1Byte RTY_P_default[ODM_NUM_RATE_IDX];
169 BOOLEAN RTY_P_modify_note[ODM_NUM_RATE_IDX];
171 u1Byte RATE_UP_RTY_RATIO[ODM_NUM_RATE_IDX];
172 u1Byte RATE_UP_RTY_RATIO_default[ODM_NUM_RATE_IDX];
173 BOOLEAN RATE_UP_RTY_RATIO_modify_note[ODM_NUM_RATE_IDX];
175 u1Byte RATE_DOWN_RTY_RATIO[ODM_NUM_RATE_IDX];
176 u1Byte RATE_DOWN_RTY_RATIO_default[ODM_NUM_RATE_IDX];
177 BOOLEAN RATE_DOWN_RTY_RATIO_modify_note[ODM_NUM_RATE_IDX];
179 BOOLEAN RA_Para_feedback_req;
187 u1Byte link_tx_rate[ODM_ASSOCIATE_ENTRY_NUM];
189 #if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT))
190 u1Byte per_rate_retrylimit_20M[ODM_NUM_RATE_IDX];
191 u1Byte per_rate_retrylimit_40M[ODM_NUM_RATE_IDX];
192 u1Byte retry_descend_num;
193 u1Byte retrylimit_low;
194 u1Byte retrylimit_high;
200 typedef struct _ODM_RATE_ADAPTIVE {
201 u1Byte Type; // DM_Type_ByFW/DM_Type_ByDriver
202 u1Byte HighRSSIThresh; // if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH
203 u1Byte LowRSSIThresh; // if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW
204 u1Byte RATRState; // Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW
206 #if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
207 u1Byte LdpcThres; // if RSSI > LdpcThres => switch from LPDC to BCC
208 BOOLEAN bLowerRtsRate;
211 #if(DM_ODM_SUPPORT_TYPE & ODM_WIN)
213 #elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
216 u1Byte UltraLowRSSIThresh;
217 u4Byte LastRATR; // RATR Register Content
220 } ODM_RATE_ADAPTIVE, *PODM_RATE_ADAPTIVE;
223 ODM_C2HRaParaReportHandler(
230 odm_RA_ParaAdjust_Send_H2C(
237 IN u4Byte *const dm_value
241 odm_RA_ParaAdjust_init(
251 phydm_ra_dynamic_retry_count(
256 phydm_ra_dynamic_retry_limit(
261 phydm_ra_dynamic_rate_id_on_assoc(
263 IN u1Byte wireless_mode,
264 IN u1Byte init_rate_id
268 phydm_c2h_ra_report_handler(
285 odm_RSSIMonitorCheck(
289 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
291 phydm_FindMinimumRSSI(
292 IN PDM_ODM_T pDM_Odm,
293 IN PADAPTER pAdapter,
294 IN OUT BOOLEAN *pbLink_temp
300 odm_RSSIMonitorCheckMP(
305 odm_RSSIMonitorCheckCE(
310 odm_RSSIMonitorCheckAP(
316 odm_RateAdaptiveMaskInit(
321 odm_RefreshRateAdaptiveMask(
326 odm_RefreshRateAdaptiveMaskMP(
331 odm_RefreshRateAdaptiveMaskCE(
336 odm_RefreshRateAdaptiveMaskAPADSL(
344 IN BOOLEAN bForceUpdate,
345 OUT pu1Byte pRATRState
349 odm_RefreshBasicRateMask(
353 ODM_RAPostActionOnAssoc(
357 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
363 IN BOOLEAN bErpProtect
367 ODM_UpdateNoisyState(
369 IN BOOLEAN bNoisyStateFromC2H
373 Set_RA_DM_Ratrbitmap_by_Noisy(
375 IN WIRELESS_MODE WirelessMode,
376 IN u4Byte ratr_bitmap,
386 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
389 odm_RSSIDumpToRegister(
394 odm_RefreshLdpcRtsMP(
395 IN PADAPTER pAdapter,
396 IN PDM_ODM_T pDM_Odm,
399 IN s4Byte UndecoratedSmoothedPWDB
403 ODM_DynamicARFBSelect(
406 IN BOOLEAN Collision_State
410 ODM_RateAdaptiveStateApInit(
411 IN PVOID PADAPTER_VOID,
412 IN PRT_WLAN_STA pEntry
414 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
422 PhyDM_Get_Rate_Bitmap_Ex(
426 IN u1Byte rssi_level,
427 OUT u8Byte *dm_RA_Mask,
437 void phydm_ra_rssi_rpt_wk(PVOID pContext);
439 #endif/*#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)*/
441 #endif/*#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN| ODM_CE))*/
443 #endif /*#ifndef __ODMRAINFO_H__*/