rtl8723bu/hal/phydm/phydm_reg.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20 //============================================================
  21 // File Name: odm_reg.h
  22 //
  23 // Description:
  24 //
  25 // This file is for general register definition.
  26 //
  27 //
  28 //============================================================
  29 #ifndef __HAL_ODM_REG_H__
  30 #define __HAL_ODM_REG_H__
  31
  32 //
  33 // Register Definition
  34 //
  35
  36 //MAC REG
  37 #define ODM_BB_RESET                                    0x002
  38 #define ODM_DUMMY                                               0x4fe
  39 #define RF_T_METER_OLD                          0x24
  40 #define RF_T_METER_NEW                          0x42
  41
  42 #define ODM_EDCA_VO_PARAM                       0x500
  43 #define ODM_EDCA_VI_PARAM                       0x504
  44 #define ODM_EDCA_BE_PARAM                       0x508
  45 #define ODM_EDCA_BK_PARAM                       0x50C
  46 #define ODM_TXPAUSE                                     0x522
  47
  48 //BB REG
  49 #define ODM_FPGA_PHY0_PAGE8                     0x800
  50 #define ODM_PSD_SETTING                         0x808
  51 #define ODM_AFE_SETTING                         0x818
  52 #define ODM_TXAGC_B_6_18                                0x830
  53 #define ODM_TXAGC_B_24_54                       0x834
  54 #define ODM_TXAGC_B_MCS32_5                     0x838
  55 #define ODM_TXAGC_B_MCS0_MCS3           0x83c
  56 #define ODM_TXAGC_B_MCS4_MCS7           0x848
  57 #define ODM_TXAGC_B_MCS8_MCS11          0x84c
  58 #define ODM_ANALOG_REGISTER                     0x85c
  59 #define ODM_RF_INTERFACE_OUTPUT         0x860
  60 #define ODM_TXAGC_B_MCS12_MCS15 0x868
  61 #define ODM_TXAGC_B_11_A_2_11           0x86c
  62 #define ODM_AD_DA_LSB_MASK                      0x874
  63 #define ODM_ENABLE_3_WIRE                       0x88c
  64 #define ODM_PSD_REPORT                          0x8b4
  65 #define ODM_R_ANT_SELECT                                0x90c
  66 #define ODM_CCK_ANT_SELECT                      0xa07
  67 #define ODM_CCK_PD_THRESH                       0xa0a
  68 #define ODM_CCK_RF_REG1                         0xa11
  69 #define ODM_CCK_MATCH_FILTER                    0xa20
  70 #define ODM_CCK_RAKE_MAC                                0xa2e
  71 #define ODM_CCK_CNT_RESET                       0xa2d
  72 #define ODM_CCK_TX_DIVERSITY                    0xa2f
  73 #define ODM_CCK_FA_CNT_MSB                      0xa5b
  74 #define ODM_CCK_FA_CNT_LSB                      0xa5c
  75 #define ODM_CCK_NEW_FUNCTION            0xa75
  76 #define ODM_OFDM_PHY0_PAGE_C            0xc00
  77 #define ODM_OFDM_RX_ANT                         0xc04
  78 #define ODM_R_A_RXIQI                                   0xc14
  79 #define ODM_R_A_AGC_CORE1                       0xc50
  80 #define ODM_R_A_AGC_CORE2                       0xc54
  81 #define ODM_R_B_AGC_CORE1                       0xc58
  82 #define ODM_R_AGC_PAR                                   0xc70
  83 #define ODM_R_HTSTF_AGC_PAR                     0xc7c
  84 #define ODM_TX_PWR_TRAINING_A           0xc90
  85 #define ODM_TX_PWR_TRAINING_B           0xc98
  86 #define ODM_OFDM_FA_CNT1                                0xcf0
  87 #define ODM_OFDM_PHY0_PAGE_D            0xd00
  88 #define ODM_OFDM_FA_CNT2                                0xda0
  89 #define ODM_OFDM_FA_CNT3                                0xda4
  90 #define ODM_OFDM_FA_CNT4                                0xda8
  91 #define ODM_TXAGC_A_6_18                                0xe00
  92 #define ODM_TXAGC_A_24_54                       0xe04
  93 #define ODM_TXAGC_A_1_MCS32                     0xe08
  94 #define ODM_TXAGC_A_MCS0_MCS3           0xe10
  95 #define ODM_TXAGC_A_MCS4_MCS7           0xe14
  96 #define ODM_TXAGC_A_MCS8_MCS11          0xe18
  97 #define ODM_TXAGC_A_MCS12_MCS15         0xe1c
  98
  99 //RF REG
 100 #define ODM_GAIN_SETTING                                0x00
 101 #define ODM_CHANNEL                                     0x18
 102 #define ODM_RF_T_METER                          0x24
 103 #define ODM_RF_T_METER_92D                      0x42
 104 #define ODM_RF_T_METER_88E                      0x42
 105 #define ODM_RF_T_METER_92E                      0x42
 106 #define ODM_RF_T_METER_8812                     0x42
 107
 108 //Ant Detect Reg
 109 #define ODM_DPDT                                                0x300
 110
 111 //PSD Init
 112 #define ODM_PSDREG                                      0x808
 113
 114 //92D Path Div
 115 #define PATHDIV_REG                                     0xB30
 116 #define PATHDIV_TRI                                     0xBA0
 117
 118
 119 //
 120 // Bitmap Definition
 121 //
 122 #if(DM_ODM_SUPPORT_TYPE & (ODM_AP))
 123 // TX AGC
 124 #define         rTxAGC_A_CCK11_CCK1_JAguar      0xc20
 125 #define         rTxAGC_A_Ofdm18_Ofdm6_JAguar    0xc24
 126 #define         rTxAGC_A_Ofdm54_Ofdm24_JAguar   0xc28
 127 #define         rTxAGC_A_MCS3_MCS0_JAguar       0xc2c
 128 #define         rTxAGC_A_MCS7_MCS4_JAguar       0xc30
 129 #define         rTxAGC_A_MCS11_MCS8_JAguar      0xc34
 130 #define         rTxAGC_A_MCS15_MCS12_JAguar     0xc38
 131 #define         rTxAGC_A_Nss1Index3_Nss1Index0_JAguar   0xc3c
 132 #define         rTxAGC_A_Nss1Index7_Nss1Index4_JAguar   0xc40
 133 #define         rTxAGC_A_Nss2Index1_Nss1Index8_JAguar   0xc44
 134 #define         rTxAGC_A_Nss2Index5_Nss2Index2_JAguar   0xc48
 135 #define         rTxAGC_A_Nss2Index9_Nss2Index6_JAguar   0xc4c
 136 #if defined(CONFIG_WLAN_HAL_8814AE)
 137 #define         rTxAGC_A_MCS19_MCS16_JAguar     0xcd8
 138 #define         rTxAGC_A_MCS23_MCS20_JAguar     0xcdc
 139 #define         rTxAGC_A_Nss3Index3_Nss3Index0_JAguar   0xce0
 140 #define         rTxAGC_A_Nss3Index7_Nss3Index4_JAguar   0xce4
 141 #define         rTxAGC_A_Nss3Index9_Nss3Index8_JAguar   0xce8
 142 #endif
 143 #define         rTxAGC_B_CCK11_CCK1_JAguar      0xe20
 144 #define         rTxAGC_B_Ofdm18_Ofdm6_JAguar    0xe24
 145 #define         rTxAGC_B_Ofdm54_Ofdm24_JAguar   0xe28
 146 #define         rTxAGC_B_MCS3_MCS0_JAguar       0xe2c
 147 #define         rTxAGC_B_MCS7_MCS4_JAguar       0xe30
 148 #define         rTxAGC_B_MCS11_MCS8_JAguar      0xe34
 149 #define         rTxAGC_B_MCS15_MCS12_JAguar     0xe38
 150 #define         rTxAGC_B_Nss1Index3_Nss1Index0_JAguar   0xe3c
 151 #define         rTxAGC_B_Nss1Index7_Nss1Index4_JAguar   0xe40
 152 #define         rTxAGC_B_Nss2Index1_Nss1Index8_JAguar   0xe44
 153 #define         rTxAGC_B_Nss2Index5_Nss2Index2_JAguar   0xe48
 154 #define         rTxAGC_B_Nss2Index9_Nss2Index6_JAguar   0xe4c
 155 #if defined(CONFIG_WLAN_HAL_8814AE)
 156 #define         rTxAGC_B_MCS19_MCS16_JAguar     0xed8
 157 #define         rTxAGC_B_MCS23_MCS20_JAguar     0xedc
 158 #define         rTxAGC_B_Nss3Index3_Nss3Index0_JAguar   0xee0
 159 #define         rTxAGC_B_Nss3Index7_Nss3Index4_JAguar   0xee4
 160 #define         rTxAGC_B_Nss3Index9_Nss3Index8_JAguar   0xee8
 161 #define         rTxAGC_C_CCK11_CCK1_JAguar      0x1820
 162 #define         rTxAGC_C_Ofdm18_Ofdm6_JAguar    0x1824
 163 #define         rTxAGC_C_Ofdm54_Ofdm24_JAguar   0x1828
 164 #define         rTxAGC_C_MCS3_MCS0_JAguar       0x182c
 165 #define         rTxAGC_C_MCS7_MCS4_JAguar       0x1830
 166 #define         rTxAGC_C_MCS11_MCS8_JAguar      0x1834
 167 #define         rTxAGC_C_MCS15_MCS12_JAguar     0x1838
 168 #define         rTxAGC_C_Nss1Index3_Nss1Index0_JAguar   0x183c
 169 #define         rTxAGC_C_Nss1Index7_Nss1Index4_JAguar   0x1840
 170 #define         rTxAGC_C_Nss2Index1_Nss1Index8_JAguar   0x1844
 171 #define         rTxAGC_C_Nss2Index5_Nss2Index2_JAguar   0x1848
 172 #define         rTxAGC_C_Nss2Index9_Nss2Index6_JAguar   0x184c
 173 #define         rTxAGC_C_MCS19_MCS16_JAguar     0x18d8
 174 #define         rTxAGC_C_MCS23_MCS20_JAguar     0x18dc
 175 #define         rTxAGC_C_Nss3Index3_Nss3Index0_JAguar   0x18e0
 176 #define         rTxAGC_C_Nss3Index7_Nss3Index4_JAguar   0x18e4
 177 #define         rTxAGC_C_Nss3Index9_Nss3Index8_JAguar   0x18e8
 178 #define         rTxAGC_D_CCK11_CCK1_JAguar      0x1a20
 179 #define         rTxAGC_D_Ofdm18_Ofdm6_JAguar    0x1a24
 180 #define         rTxAGC_D_Ofdm54_Ofdm24_JAguar   0x1a28
 181 #define         rTxAGC_D_MCS3_MCS0_JAguar       0x1a2c
 182 #define         rTxAGC_D_MCS7_MCS4_JAguar       0x1a30
 183 #define         rTxAGC_D_MCS11_MCS8_JAguar      0x1a34
 184 #define         rTxAGC_D_MCS15_MCS12_JAguar     0x1a38
 185 #define         rTxAGC_D_Nss1Index3_Nss1Index0_JAguar   0x1a3c
 186 #define         rTxAGC_D_Nss1Index7_Nss1Index4_JAguar   0x1a40
 187 #define         rTxAGC_D_Nss2Index1_Nss1Index8_JAguar   0x1a44
 188 #define         rTxAGC_D_Nss2Index5_Nss2Index2_JAguar   0x1a48
 189 #define         rTxAGC_D_Nss2Index9_Nss2Index6_JAguar   0x1a4c
 190 #define         rTxAGC_D_MCS19_MCS16_JAguar     0x1ad8
 191 #define         rTxAGC_D_MCS23_MCS20_JAguar     0x1adc
 192 #define         rTxAGC_D_Nss3Index3_Nss3Index0_JAguar   0x1ae0
 193 #define         rTxAGC_D_Nss3Index7_Nss3Index4_JAguar   0x1ae4
 194 #define         rTxAGC_D_Nss3Index9_Nss3Index8_JAguar   0x1ae8
 195 #endif
 196
 197 #define         bTxAGC_byte0_Jaguar     0xff
 198 #define         bTxAGC_byte1_Jaguar     0xff00
 199 #define         bTxAGC_byte2_Jaguar     0xff0000
 200 #define         bTxAGC_byte3_Jaguar     0xff000000
 201 #endif
 202
 203 #define BIT_FA_RESET                                    BIT0
 204
 205
 206
 207 #endif