rtl8723bu/hal/phydm/phydm_rxhp.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20 //============================================================
  21 // include files
  22 //============================================================
  23 #include "mp_precomp.h"
  24 #include "phydm_precomp.h"
  25
  26 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
  27
  28 #define AFH_PSD         1       //0:normal PSD scan, 1: only do 20 pts PSD
  29 #define MODE_40M                0       //0:20M, 1:40M
  30 #define PSD_TH2         3
  31 #define PSD_CHMIN               20   // Minimum channel number for BT AFH
  32 #define SIR_STEP_SIZE   3
  33 #define   Smooth_Size_1         5
  34 #define Smooth_TH_1     3
  35 #define   Smooth_Size_2         10
  36 #define Smooth_TH_2     4
  37 #define   Smooth_Size_3         20
  38 #define Smooth_TH_3     4
  39 #define   Smooth_Step_Size 5
  40 #define Adaptive_SIR    1
  41 #define SCAN_INTERVAL   1500 //ms
  42 #define SYN_Length              5    // for 92D
  43
  44 #define LNA_Low_Gain_1                      0x64
  45 #define LNA_Low_Gain_2                      0x5A
  46 #define LNA_Low_Gain_3                      0x58
  47
  48 #define pw_th_10dB                                      0x0
  49 #define pw_th_16dB                                      0x3
  50
  51 #define FA_RXHP_TH1                           5000
  52 #define FA_RXHP_TH2                           1500
  53 #define FA_RXHP_TH3                             800
  54 #define FA_RXHP_TH4                             600
  55 #define FA_RXHP_TH5                             500
  56
  57 #define Idle_Mode                                       0
  58 #define High_TP_Mode                            1
  59 #define Low_TP_Mode                             2
  60
  61
  62 VOID
  63 odm_PSDMonitorInit(
  64         IN              PVOID                   pDM_VOID
  65         )
  66 {
  67 #if (DEV_BUS_TYPE == RT_PCI_INTERFACE)|(DEV_BUS_TYPE == RT_USB_INTERFACE)
  68         PDM_ODM_T                               pDM_Odm = (PDM_ODM_T)pDM_VOID;
  69
  70         //HAL_DATA_TYPE         *pHalData = GET_HAL_DATA(Adapter);
  71         //PSD Monitor Setting
  72         //Which path in ADC/DAC is turnned on for PSD: both I/Q
  73         ODM_SetBBReg(pDM_Odm, ODM_PSDREG, BIT10|BIT11, 0x3);
  74         //Ageraged number: 8
  75         ODM_SetBBReg(pDM_Odm, ODM_PSDREG, BIT12|BIT13, 0x1);
  76         pDM_Odm->bPSDinProcess = FALSE;
  77         pDM_Odm->bUserAssignLevel = FALSE;
  78         pDM_Odm->bPSDactive = FALSE;
  79         //pDM_Odm->bDMInitialGainEnable=TRUE;           //change the initialization to DIGinit
  80         //Set Debug Port
  81         //PHY_SetBBReg(Adapter, 0x908, bMaskDWord, 0x803);
  82         //PHY_SetBBReg(Adapter, 0xB34, bMaskByte0, 0x00); // pause PSD
  83         //PHY_SetBBReg(Adapter, 0xB38, bMaskByte0, 10); //rescan
  84         //PHY_SetBBReg(Adapter, 0xB38, bMaskByte2|bMaskByte3, 100); //interval
  85
  86         //PlatformSetTimer( Adapter, &pHalData->PSDTriggerTimer, 0); //ms
  87 #endif
  88 }
  89
  90 VOID
  91 PatchDCTone(
  92         IN              PVOID                   pDM_VOID,
  93         pu4Byte         PSD_report,
  94         u1Byte          initial_gain_psd
  95 )
  96 {
  97         PDM_ODM_T                               pDM_Odm = (PDM_ODM_T)pDM_VOID;
  98         //HAL_DATA_TYPE         *pHalData = GET_HAL_DATA(Adapter);
  99         //PADAPTER      pAdapter;
 100
 101         u4Byte  psd_report;
 102
 103         //2 Switch to CH11 to patch CH9 and CH13 DC tone
 104         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, 11);
 105
 106         if(pDM_Odm->SupportICType== ODM_RTL8192D)
 107         {
 108                 if((*(pDM_Odm->pMacPhyMode) == ODM_SMSP)||(*(pDM_Odm->pMacPhyMode) == ODM_DMSP))
 109                 {
 110                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_CHNLBW, 0x3FF, 11);
 111                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x25, 0xfffff, 0x643BC);
 112                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x26, 0xfffff, 0xFC038);
 113                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x27, 0xfffff, 0x77C1A);
 114                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x2B, 0xfffff, 0x41289);
 115                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x2C, 0xfffff, 0x01840);
 116                 }
 117                 else
 118                 {
 119                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x25, 0xfffff, 0x643BC);
 120                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x26, 0xfffff, 0xFC038);
 121                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x27, 0xfffff, 0x77C1A);
 122                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2B, 0xfffff, 0x41289);
 123                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2C, 0xfffff, 0x01840);
 124                 }
 125         }
 126
 127         //Ch9 DC tone patch
 128         psd_report = GetPSDData(pDM_Odm, 96, initial_gain_psd);
 129         PSD_report[50] = psd_report;
 130         //Ch13 DC tone patch
 131         psd_report = GetPSDData(pDM_Odm, 32, initial_gain_psd);
 132         PSD_report[70] = psd_report;
 133
 134         //2 Switch to CH3 to patch CH1 and CH5 DC tone
 135         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, 3);
 136
 137
 138         if(pDM_Odm->SupportICType==ODM_RTL8192D)
 139         {
 140                 if((*(pDM_Odm->pMacPhyMode) == ODM_SMSP)||(*(pDM_Odm->pMacPhyMode) == ODM_DMSP))
 141                 {
 142                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_CHNLBW, 0x3FF, 3);
 143                         //PHY_SetRFReg(Adapter, ODM_RF_PATH_B, 0x25, 0xfffff, 0x643BC);
 144                         //PHY_SetRFReg(Adapter, ODM_RF_PATH_B, 0x26, 0xfffff, 0xFC038);
 145                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x27, 0xfffff, 0x07C1A);
 146                         //PHY_SetRFReg(Adapter, ODM_RF_PATH_B, 0x2B, 0xfffff, 0x61289);
 147                         //PHY_SetRFReg(Adapter, ODM_RF_PATH_B, 0x2C, 0xfffff, 0x01C41);
 148                 }
 149                 else
 150                 {
 151                         //PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x25, 0xfffff, 0x643BC);
 152                         //PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x26, 0xfffff, 0xFC038);
 153                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x27, 0xfffff, 0x07C1A);
 154                         //PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x2B, 0xfffff, 0x61289);
 155                         //PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x2C, 0xfffff, 0x01C41);
 156                 }
 157         }
 158
 159         //Ch1 DC tone patch
 160         psd_report = GetPSDData(pDM_Odm, 96, initial_gain_psd);
 161         PSD_report[10] = psd_report;
 162         //Ch5 DC tone patch
 163         psd_report = GetPSDData(pDM_Odm, 32, initial_gain_psd);
 164         PSD_report[30] = psd_report;
 165
 166 }
 167
 168
 169 VOID
 170 GoodChannelDecision(
 171         IN              PVOID                   pDM_VOID,
 172         pu4Byte         PSD_report,
 173         pu1Byte         PSD_bitmap,
 174         u1Byte          RSSI_BT,
 175         pu1Byte         PSD_bitmap_memory)
 176 {
 177         PDM_ODM_T                               pDM_Odm = (PDM_ODM_T)pDM_VOID;
 178         pRXHP_T                 pRX_HP_Table = &pDM_Odm->DM_RXHP_Table;
 179         //s4Byte        TH1 =  SSBT-0x15;    // modify TH by Neil Chen
 180         s4Byte  TH1= RSSI_BT+0x14;
 181         s4Byte  TH2 = RSSI_BT+85;
 182         //u2Byte    TH3;
 183 //      s4Byte  RegB34;
 184         u1Byte  bitmap, Smooth_size[3], Smooth_TH[3];
 185         //u1Byte        psd_bit;
 186         u4Byte  i,n,j, byte_idx, bit_idx, good_cnt, good_cnt_smoothing, Smooth_Interval[3];
 187         int             start_byte_idx,start_bit_idx,cur_byte_idx, cur_bit_idx,NOW_byte_idx ;
 188
 189 //      RegB34 = PHY_QueryBBReg(Adapter,0xB34, bMaskDWord)&0xFF;
 190
 191         if((pDM_Odm->SupportICType == ODM_RTL8192C)||(pDM_Odm->SupportICType == ODM_RTL8192D))
 192        {
 193             TH1 = RSSI_BT + 0x14;
 194         }
 195
 196         Smooth_size[0]=Smooth_Size_1;
 197         Smooth_size[1]=Smooth_Size_2;
 198         Smooth_size[2]=Smooth_Size_3;
 199         Smooth_TH[0]=Smooth_TH_1;
 200         Smooth_TH[1]=Smooth_TH_2;
 201         Smooth_TH[2]=Smooth_TH_3;
 202         Smooth_Interval[0]=16;
 203         Smooth_Interval[1]=15;
 204         Smooth_Interval[2]=13;
 205         good_cnt = 0;
 206         if(pDM_Odm->SupportICType==ODM_RTL8723A)
 207         {
 208                 //2 Threshold
 209
 210                 if(RSSI_BT >=41)
 211                         TH1 = 113;
 212                 else if(RSSI_BT >=38)   // >= -15dBm
 213                         TH1 = 105;                              //0x69
 214                 else if((RSSI_BT >=33)&(RSSI_BT <38))
 215                         TH1 = 99+(RSSI_BT-33);         //0x63
 216                 else if((RSSI_BT >=26)&(RSSI_BT<33))
 217                         TH1 = 99-(33-RSSI_BT)+2;     //0x5e
 218                 else if((RSSI_BT >=24)&(RSSI_BT<26))
 219                         TH1 = 88-((RSSI_BT-24)*3);   //0x58
 220                 else if((RSSI_BT >=18)&(RSSI_BT<24))
 221                         TH1 = 77+((RSSI_BT-18)*2);
 222                 else if((RSSI_BT >=14)&(RSSI_BT<18))
 223                         TH1 = 63+((RSSI_BT-14)*2);
 224                 else if((RSSI_BT >=8)&(RSSI_BT<14))
 225                         TH1 = 58+((RSSI_BT-8)*2);
 226                 else if((RSSI_BT >=3)&(RSSI_BT<8))
 227                         TH1 = 52+(RSSI_BT-3);
 228                 else
 229                         TH1 = 51;
 230         }
 231
 232         for (i = 0; i< 10; i++)
 233                 PSD_bitmap[i] = 0;
 234
 235
 236          // Add By Gary
 237        for (i=0; i<80; i++)
 238                 pRX_HP_Table->PSD_bitmap_RXHP[i] = 0;
 239         // End
 240
 241
 242
 243         if(pDM_Odm->SupportICType==ODM_RTL8723A)
 244         {
 245                 TH1 =TH1-SIR_STEP_SIZE;
 246         }
 247         while (good_cnt < PSD_CHMIN)
 248         {
 249                 good_cnt = 0;
 250                 if(pDM_Odm->SupportICType==ODM_RTL8723A)
 251                 {
 252                 if(TH1 ==TH2)
 253                         break;
 254                 if((TH1+SIR_STEP_SIZE) < TH2)
 255                         TH1 += SIR_STEP_SIZE;
 256                 else
 257                         TH1 = TH2;
 258                 }
 259                 else
 260                 {
 261                         if(TH1==(RSSI_BT+0x1E))
 262                              break;
 263                         if((TH1+2) < (RSSI_BT+0x1E))
 264                                 TH1+=3;
 265                         else
 266                                 TH1 = RSSI_BT+0x1E;
 267
 268                 }
 269                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD,DBG_LOUD,("PSD: decision threshold is: %d", TH1));
 270
 271                 for (i = 0; i< 80; i++)
 272                 {
 273                         if((s4Byte)(PSD_report[i]) < TH1)
 274                         {
 275                                 byte_idx = i / 8;
 276                                 bit_idx = i -8*byte_idx;
 277                                 bitmap = PSD_bitmap[byte_idx];
 278                                 PSD_bitmap[byte_idx] = bitmap | (u1Byte) (1 << bit_idx);
 279                         }
 280                 }
 281
 282 #if DBG
 283                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD: before smoothing\n"));
 284                 for(n=0;n<10;n++)
 285                 {
 286                         //DbgPrint("PSD_bitmap[%u]=%x\n", n, PSD_bitmap[n]);
 287                         for (i = 0; i<8; i++)
 288                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD_bitmap[%u] =   %d\n", 2402+n*8+i, (PSD_bitmap[n]&BIT(i))>>i));
 289                 }
 290 #endif
 291
 292                 //1 Start of smoothing function
 293
 294                 for (j=0;j<3;j++)
 295                 {
 296                         start_byte_idx=0;
 297                         start_bit_idx=0;
 298                         for(n=0; n<Smooth_Interval[j]; n++)
 299                         {
 300                                 good_cnt_smoothing = 0;
 301                                 cur_bit_idx = start_bit_idx;
 302                                 cur_byte_idx = start_byte_idx;
 303                                 for ( i=0; i < Smooth_size[j]; i++)
 304                                 {
 305                                         NOW_byte_idx = cur_byte_idx + (i+cur_bit_idx)/8;
 306                                         if ( (PSD_bitmap[NOW_byte_idx]& BIT( (cur_bit_idx + i)%8)) != 0)
 307                                                 good_cnt_smoothing++;
 308
 309                                 }
 310
 311                                 if( good_cnt_smoothing < Smooth_TH[j] )
 312                                 {
 313                                         cur_bit_idx = start_bit_idx;
 314                                         cur_byte_idx = start_byte_idx;
 315                                         for ( i=0; i< Smooth_size[j] ; i++)
 316                                         {
 317                                                 NOW_byte_idx = cur_byte_idx + (i+cur_bit_idx)/8;
 318                                                 PSD_bitmap[NOW_byte_idx] = PSD_bitmap[NOW_byte_idx] & (~BIT( (cur_bit_idx + i)%8));
 319                                         }
 320                                 }
 321                                 start_bit_idx =  start_bit_idx + Smooth_Step_Size;
 322                                 while ( (start_bit_idx)  > 7 )
 323                                 {
 324                                         start_byte_idx= start_byte_idx+start_bit_idx/8;
 325                                         start_bit_idx = start_bit_idx%8;
 326                                 }
 327                         }
 328
 329                         ODM_RT_TRACE(   pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD: after %u smoothing", j+1));
 330                         for(n=0;n<10;n++)
 331                         {
 332                                 for (i = 0; i<8; i++)
 333                                 {
 334                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD_bitmap[%u] =   %d\n", 2402+n*8+i, (PSD_bitmap[n]&BIT(i))>>i));
 335
 336                                         if ( ((PSD_bitmap[n]&BIT(i))>>i) ==1)  //----- Add By Gary
 337                                         {
 338                                            pRX_HP_Table->PSD_bitmap_RXHP[8*n+i] = 1;
 339                                         }                                                  // ------end by Gary
 340                                 }
 341                         }
 342
 343                 }
 344
 345
 346                 good_cnt = 0;
 347                 for ( i = 0; i < 10; i++)
 348                 {
 349                         for (n = 0; n < 8; n++)
 350                                 if((PSD_bitmap[i]& BIT(n)) != 0)
 351                                         good_cnt++;
 352                 }
 353                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, ODM_COMP_PSD,("PSD: good channel cnt = %u",good_cnt));
 354         }
 355
 356         //RT_TRACE(ODM_COMP_PSD, DBG_LOUD,("PSD: SSBT=%d, TH2=%d, TH1=%d",SSBT,TH2,TH1));
 357         for (i = 0; i <10; i++)
 358                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD: PSD_bitmap[%u]=%x",i,PSD_bitmap[i]));
 359 /*
 360         //Update bitmap memory
 361         for(i = 0; i < 80; i++)
 362         {
 363                 byte_idx = i / 8;
 364                 bit_idx = i -8*byte_idx;
 365                 psd_bit = (PSD_bitmap[byte_idx] & BIT(bit_idx)) >> bit_idx;
 366                 bitmap = PSD_bitmap_memory[i];
 367                 PSD_bitmap_memory[i] = (bitmap << 1) |psd_bit;
 368         }
 369 */
 370 }
 371
 372
 373
 374 VOID
 375 odm_PSD_Monitor(
 376         IN              PVOID                   pDM_VOID
 377 )
 378 {
 379         PDM_ODM_T                               pDM_Odm = (PDM_ODM_T)pDM_VOID;
 380         //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
 381         //PDM_ODM_T             pDM_Odm = &pHalData->DM_OutSrc;
 382
 383         unsigned int            pts, start_point, stop_point;
 384         u1Byte                  initial_gain ;
 385         static u1Byte           PSD_bitmap_memory[80], init_memory = 0;
 386         static u1Byte           psd_cnt=0;
 387         static u4Byte           PSD_report[80], PSD_report_tmp;
 388         static u8Byte           lastTxOkCnt=0, lastRxOkCnt=0;
 389         u1Byte                  H2C_PSD_DATA[5]={0,0,0,0,0};
 390         static u1Byte           H2C_PSD_DATA_last[5] ={0,0,0,0,0};
 391         u1Byte                  idx[20]={96,99,102,106,109,112,115,118,122,125,
 392                                         0,3,6,10,13,16,19,22,26,29};
 393         u1Byte                  n, i, channel, BBReset,tone_idx;
 394         u1Byte                  PSD_bitmap[10], SSBT=0,initial_gain_psd=0, RSSI_BT=0, initialGainUpper;
 395         s4Byte                          PSD_skip_start, PSD_skip_stop;
 396         u4Byte                  CurrentChannel, RXIQI, RxIdleLowPwr, wlan_channel;
 397         u4Byte                  ReScan, Interval, Is40MHz;
 398         u8Byte                  curTxOkCnt, curRxOkCnt;
 399         int                             cur_byte_idx, cur_bit_idx;
 400         PADAPTER                Adapter = pDM_Odm->Adapter;
 401         PMGNT_INFO              pMgntInfo = &Adapter->MgntInfo;
 402
 403
 404         if(*pDM_Odm->pbDriverIsGoingToPnpSetPowerSleep)
 405         {
 406                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("pbDriverIsGoingToPnpSetPowerSleep!!!!!!!!!!!!!!!\n"));
 407                 return;
 408         }
 409
 410
 411         if( (*(pDM_Odm->pbScanInProcess)) ||
 412                 pDM_Odm->bLinkInProcess)
 413         {
 414                 if((pDM_Odm->SupportICType==ODM_RTL8723A)&(pDM_Odm->SupportInterface==ODM_ITRF_PCIE))
 415                 {
 416                         ODM_SetTimer( pDM_Odm, &pDM_Odm->PSDTimer, 1500); //ms
 417                         //psd_cnt=0;
 418                 }
 419                 return;
 420         }
 421
 422         if(pDM_Odm->bBtHsOperation)
 423         {
 424                 ReScan = 1;
 425                 Interval = SCAN_INTERVAL;
 426         }
 427         else
 428         {
 429         ReScan = PSD_RESCAN;
 430         Interval = SCAN_INTERVAL;
 431         }
 432
 433         //1 Initialization
 434         if(init_memory == 0)
 435         {
 436                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("Init memory\n"));
 437                 for(i = 0; i < 80; i++)
 438                         PSD_bitmap_memory[i] = 0xFF; // channel is always good
 439                 init_memory = 1;
 440         }
 441         if(psd_cnt == 0)
 442         {
 443                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("Enter dm_PSD_Monitor\n"));
 444                 for(i = 0; i < 80; i++)
 445                         PSD_report[i] = 0;
 446         }
 447
 448         //1 Backup Current Settings
 449         CurrentChannel = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask);
 450 /*
 451         if(pDM_Odm->SupportICType==ODM_RTL8192D)
 452         {
 453                 //2 Record Current synthesizer parameters based on current channel
 454                 if((*pDM_Odm->MacPhyMode92D == SINGLEMAC_SINGLEPHY)||(*pDM_Odm->MacPhyMode92D == DUALMAC_SINGLEPHY))
 455                 {
 456                         SYN_RF25 = ODM_GetRFReg(Adapter, ODM_RF_PATH_B, 0x25, bMaskDWord);
 457                         SYN_RF26 = ODM_GetRFReg(Adapter, ODM_RF_PATH_B, 0x26, bMaskDWord);
 458                         SYN_RF27 = ODM_GetRFReg(Adapter, ODM_RF_PATH_B, 0x27, bMaskDWord);
 459                         SYN_RF2B = ODM_GetRFReg(Adapter, ODM_RF_PATH_B, 0x2B, bMaskDWord);
 460                         SYN_RF2C = ODM_GetRFReg(Adapter, ODM_RF_PATH_B, 0x2C, bMaskDWord);
 461         }
 462                 else     // DualMAC_DualPHY 2G
 463                 {
 464                         SYN_RF25 = ODM_GetRFReg(Adapter, ODM_RF_PATH_A, 0x25, bMaskDWord);
 465                         SYN_RF26 = ODM_GetRFReg(Adapter, ODM_RF_PATH_A, 0x26, bMaskDWord);
 466                         SYN_RF27 = ODM_GetRFReg(Adapter, ODM_RF_PATH_A, 0x27, bMaskDWord);
 467                         SYN_RF2B = ODM_GetRFReg(Adapter, ODM_RF_PATH_A, 0x2B, bMaskDWord);
 468                         SYN_RF2C = ODM_GetRFReg(Adapter, ODM_RF_PATH_A, 0x2C, bMaskDWord);
 469                 }
 470         }
 471 */
 472         //RXIQI = PHY_QueryBBReg(Adapter, 0xC14, bMaskDWord);
 473         RXIQI = ODM_GetBBReg(pDM_Odm, 0xC14, bMaskDWord);
 474
 475         //RxIdleLowPwr = (PHY_QueryBBReg(Adapter, 0x818, bMaskDWord)&BIT28)>>28;
 476         RxIdleLowPwr = (ODM_GetBBReg(pDM_Odm, 0x818, bMaskDWord)&BIT28)>>28;
 477
 478         //2???
 479         if(CHNL_RUN_ABOVE_40MHZ(pMgntInfo))
 480                 Is40MHz = TRUE;
 481         else
 482                 Is40MHz = FALSE;
 483
 484         ODM_RT_TRACE(pDM_Odm,   ODM_COMP_PSD, DBG_LOUD,("PSD Scan Start\n"));
 485         //1 Turn off CCK
 486         //PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT24, 0);
 487         ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0);
 488         //1 Turn off TX
 489         //Pause TX Queue
 490         //PlatformEFIOWrite1Byte(Adapter, REG_TXPAUSE, 0xFF);
 491         ODM_Write1Byte(pDM_Odm,REG_TXPAUSE, 0xFF);
 492
 493         //Force RX to stop TX immediately
 494         //PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x32E13);
 495
 496         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x32E13);
 497         //1 Turn off RX
 498         //Rx AGC off  RegC70[0]=0, RegC7C[20]=0
 499         //PHY_SetBBReg(Adapter, 0xC70, BIT0, 0);
 500         //PHY_SetBBReg(Adapter, 0xC7C, BIT20, 0);
 501
 502         ODM_SetBBReg(pDM_Odm, 0xC70, BIT0, 0);
 503         ODM_SetBBReg(pDM_Odm, 0xC7C, BIT20, 0);
 504
 505
 506         //Turn off CCA
 507         //PHY_SetBBReg(Adapter, 0xC14, bMaskDWord, 0x0);
 508         ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, 0x0);
 509
 510         //BB Reset
 511         //BBReset = PlatformEFIORead1Byte(Adapter, 0x02);
 512         BBReset = ODM_Read1Byte(pDM_Odm, 0x02);
 513
 514         //PlatformEFIOWrite1Byte(Adapter, 0x02, BBReset&(~BIT0));
 515         //PlatformEFIOWrite1Byte(Adapter, 0x02, BBReset|BIT0);
 516         ODM_SetBBReg(pDM_Odm, 0x87C, BIT31, 1); //clock gated to prevent from AGC table mess
 517         ODM_Write1Byte(pDM_Odm,  0x02, BBReset&(~BIT0));
 518         ODM_Write1Byte(pDM_Odm,  0x02, BBReset|BIT0);
 519         ODM_SetBBReg(pDM_Odm, 0x87C, BIT31, 0);
 520
 521         //1 Leave RX idle low power
 522         //PHY_SetBBReg(Adapter, 0x818, BIT28, 0x0);
 523
 524         ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0);
 525         //1 Fix initial gain
 526         //if (IS_HARDWARE_TYPE_8723AE(Adapter))
 527         //RSSI_BT = pHalData->RSSI_BT;
 528        //else if((IS_HARDWARE_TYPE_8192C(Adapter))||(IS_HARDWARE_TYPE_8192D(Adapter)))      // Add by Gary
 529        //    RSSI_BT = RSSI_BT_new;
 530
 531         if((pDM_Odm->SupportICType==ODM_RTL8723A)&(pDM_Odm->SupportInterface==ODM_ITRF_PCIE))
 532         RSSI_BT=pDM_Odm->RSSI_BT;               //need to check C2H to pDM_Odm RSSI BT
 533
 534         if(RSSI_BT>=47)
 535                 RSSI_BT=47;
 536
 537         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD: RSSI_BT= %d\n", RSSI_BT));
 538
 539         if(pDM_Odm->SupportICType==ODM_RTL8723A)
 540         {
 541                //Neil add--2011--10--12
 542                 //2 Initial Gain index
 543                 if(RSSI_BT >=35)   // >= -15dBm
 544                         initial_gain_psd = RSSI_BT*2;
 545                 else if((RSSI_BT >=33)&(RSSI_BT<35))
 546                         initial_gain_psd = RSSI_BT*2+6;
 547                 else if((RSSI_BT >=24)&(RSSI_BT<33))
 548                         initial_gain_psd = 70-(33-RSSI_BT);
 549                 else if((RSSI_BT >=19)&(RSSI_BT<24))
 550                         initial_gain_psd = 64-((24-RSSI_BT)*4);
 551                 else if((RSSI_BT >=14)&(RSSI_BT<19))
 552                         initial_gain_psd = 44-((18-RSSI_BT)*2);
 553                 else if((RSSI_BT >=8)&(RSSI_BT<14))
 554                         initial_gain_psd = 35-(14-RSSI_BT);
 555                 else
 556                         initial_gain_psd = 0x1B;
 557         }
 558         else
 559         {
 560
 561                 //need to do
 562                 initial_gain_psd = pDM_Odm->RSSI_Min;    // PSD report based on RSSI
 563                 //}
 564         }
 565         //if(RSSI_BT<0x17)
 566         //      RSSI_BT +=3;
 567         //DbgPrint("PSD: RSSI_BT= %d\n", RSSI_BT);
 568         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD: RSSI_BT= %d\n", RSSI_BT));
 569
 570         //initialGainUpper = 0x5E;  //Modify by neil chen
 571
 572         if(pDM_Odm->bUserAssignLevel)
 573         {
 574                 pDM_Odm->bUserAssignLevel = FALSE;
 575                 initialGainUpper = 0x7f;
 576         }
 577         else
 578         {
 579                 initialGainUpper = 0x5E;
 580         }
 581
 582         /*
 583         if (initial_gain_psd < 0x1a)
 584                 initial_gain_psd = 0x1a;
 585         if (initial_gain_psd > initialGainUpper)
 586                 initial_gain_psd = initialGainUpper;
 587         */
 588
 589         //if(pDM_Odm->SupportICType==ODM_RTL8723A)
 590         SSBT = RSSI_BT  * 2 +0x3E;
 591
 592
 593         //if(IS_HARDWARE_TYPE_8723AE(Adapter))
 594         //      SSBT = RSSI_BT  * 2 +0x3E;
 595         //else if((IS_HARDWARE_TYPE_8192C(Adapter))||(IS_HARDWARE_TYPE_8192D(Adapter)))   // Add by Gary
 596         //{
 597         //      RSSI_BT = initial_gain_psd;
 598         //      SSBT = RSSI_BT;
 599         //}
 600         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD: SSBT= %d\n", SSBT));
 601         ODM_RT_TRACE(   pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD: initial gain= 0x%x\n", initial_gain_psd));
 602         //DbgPrint("PSD: SSBT= %d", SSBT);
 603         //need to do
 604         pDM_Odm->bDMInitialGainEnable = FALSE;
 605         initial_gain =(u1Byte) (ODM_GetBBReg(pDM_Odm, 0xc50, bMaskDWord) & 0x7F);
 606
 607         // make sure the initial gain is under the correct range.
 608         //initial_gain_psd &= 0x7f;
 609         ODM_Write_DIG(pDM_Odm, initial_gain_psd);
 610         //1 Turn off 3-wire
 611         ODM_SetBBReg(pDM_Odm, 0x88c, BIT20|BIT21|BIT22|BIT23, 0xF);
 612
 613         //pts value = 128, 256, 512, 1024
 614         pts = 128;
 615
 616         if(pts == 128)
 617         {
 618                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x0);
 619                 start_point = 64;
 620                 stop_point = 192;
 621         }
 622         else if(pts == 256)
 623         {
 624                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x1);
 625                 start_point = 128;
 626                 stop_point = 384;
 627         }
 628         else if(pts == 512)
 629         {
 630                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x2);
 631                 start_point = 256;
 632                 stop_point = 768;
 633         }
 634         else
 635         {
 636                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x3);
 637                 start_point = 512;
 638                 stop_point = 1536;
 639         }
 640
 641
 642 //3 Skip WLAN channels if WLAN busy
 643
 644         curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast) - lastTxOkCnt;
 645         curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast) - lastRxOkCnt;
 646         lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast);
 647         lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast);
 648
 649         PSD_skip_start=80;
 650         PSD_skip_stop = 0;
 651         wlan_channel = CurrentChannel & 0x0f;
 652
 653         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD,DBG_LOUD,("PSD: current channel: %x, BW:%d \n", wlan_channel, Is40MHz));
 654         if(pDM_Odm->SupportICType==ODM_RTL8723A)
 655         {
 656                 if(pDM_Odm->bBtHsOperation)
 657                 {
 658                         if(pDM_Odm->bLinked)
 659                         {
 660                                 if(Is40MHz)
 661                                 {
 662                                         PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-2;  // Modify by Neil to add 10 chs to mask
 663                                         PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+4;
 664                                 }
 665                                 else
 666                                 {
 667                                         PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-10;  // Modify by Neil to add 10 chs to mask
 668                                         PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+18;
 669                                 }
 670                         }
 671                         else
 672                         {
 673                                 // mask for 40MHz
 674                                 PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-2;  // Modify by Neil to add 10 chs to mask
 675                                 PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+4;
 676                         }
 677                         if(PSD_skip_start < 0)
 678                                 PSD_skip_start = 0;
 679                         if(PSD_skip_stop >80)
 680                                 PSD_skip_stop = 80;
 681                 }
 682                 else
 683                 {
 684                         if((curRxOkCnt+curTxOkCnt) > 5)
 685                         {
 686                                 if(Is40MHz)
 687                                 {
 688                                         PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-2;  // Modify by Neil to add 10 chs to mask
 689                                         PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+4;
 690                                 }
 691                                 else
 692                                 {
 693                                         PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-10;  // Modify by Neil to add 10 chs to mask
 694                                         PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+18;
 695                                 }
 696
 697                                 if(PSD_skip_start < 0)
 698                                         PSD_skip_start = 0;
 699                                 if(PSD_skip_stop >80)
 700                                         PSD_skip_stop = 80;
 701                         }
 702                 }
 703         }
 704 #if 0
 705         else
 706         {
 707                 if((curRxOkCnt+curTxOkCnt) > 1000)
 708                 {
 709                         PSD_skip_start = (wlan_channel-1)*5 -Is40MHz*10;
 710                         PSD_skip_stop = PSD_skip_start + (1+Is40MHz)*20;
 711                 }
 712         }
 713 #endif  //Reove RXHP Issue
 714         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD,DBG_LOUD,("PSD: Skip tone from %d to %d \n", PSD_skip_start, PSD_skip_stop));
 715
 716         for (n=0;n<80;n++)
 717         {
 718                 if((n%20)==0)
 719                 {
 720                         channel = (n/20)*4 + 1;
 721
 722                                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, channel);
 723                                 }
 724                 tone_idx = n%20;
 725                 if ((n>=PSD_skip_start) && (n<PSD_skip_stop))
 726                 {
 727                         PSD_report[n] = SSBT;
 728                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD,DBG_LOUD,("PSD:Tone %d skipped \n", n));
 729                 }
 730                 else
 731                 {
 732                         PSD_report_tmp =  GetPSDData(pDM_Odm, idx[tone_idx], initial_gain_psd);
 733
 734                         if ( PSD_report_tmp > PSD_report[n])
 735                                 PSD_report[n] = PSD_report_tmp;
 736
 737                 }
 738         }
 739
 740         PatchDCTone(pDM_Odm, PSD_report, initial_gain_psd);
 741
 742        //----end
 743         //1 Turn on RX
 744         //Rx AGC on
 745         ODM_SetBBReg(pDM_Odm, 0xC70, BIT0, 1);
 746         ODM_SetBBReg(pDM_Odm, 0xC7C, BIT20, 1);
 747         //CCK on
 748         ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 1);
 749         //1 Turn on TX
 750         //Resume TX Queue
 751
 752         ODM_Write1Byte(pDM_Odm,REG_TXPAUSE, 0x00);
 753         //Turn on 3-wire
 754         ODM_SetBBReg(pDM_Odm, 0x88c, BIT20|BIT21|BIT22|BIT23, 0x0);
 755         //1 Restore Current Settings
 756         //Resume DIG
 757         pDM_Odm->bDMInitialGainEnable = TRUE;
 758
 759         ODM_Write_DIG(pDM_Odm, initial_gain);
 760
 761         // restore originl center frequency
 762         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, CurrentChannel);
 763
 764         //Turn on CCA
 765         ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, RXIQI);
 766         //Restore RX idle low power
 767         if(RxIdleLowPwr == TRUE)
 768                 ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 1);
 769
 770         psd_cnt++;
 771         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD:psd_cnt = %d \n",psd_cnt));
 772         if (psd_cnt < ReScan)
 773                 ODM_SetTimer(pDM_Odm, &pDM_Odm->PSDTimer, Interval);
 774         else
 775         {
 776                 psd_cnt = 0;
 777                 for(i=0;i<80;i++)
 778                         //DbgPrint("psd_report[%d]=     %d \n", 2402+i, PSD_report[i]);
 779                         RT_TRACE(       ODM_COMP_PSD, DBG_LOUD,("psd_report[%d]=     %d \n", 2402+i, PSD_report[i]));
 780
 781
 782                 GoodChannelDecision(pDM_Odm, PSD_report, PSD_bitmap,RSSI_BT, PSD_bitmap_memory);
 783
 784                 if(pDM_Odm->SupportICType==ODM_RTL8723A)
 785                 {
 786                         cur_byte_idx=0;
 787                         cur_bit_idx=0;
 788
 789                         //2 Restore H2C PSD Data to Last Data
 790                         H2C_PSD_DATA_last[0] = H2C_PSD_DATA[0];
 791                         H2C_PSD_DATA_last[1] = H2C_PSD_DATA[1];
 792                         H2C_PSD_DATA_last[2] = H2C_PSD_DATA[2];
 793                         H2C_PSD_DATA_last[3] = H2C_PSD_DATA[3];
 794                         H2C_PSD_DATA_last[4] = H2C_PSD_DATA[4];
 795
 796
 797                         //2 Translate 80bit channel map to 40bit channel
 798                         for ( i=0;i<5;i++)
 799                         {
 800                                 for(n=0;n<8;n++)
 801                                 {
 802                                         cur_byte_idx = i*2 + n/4;
 803                                         cur_bit_idx = (n%4)*2;
 804                                         if ( ((PSD_bitmap[cur_byte_idx]& BIT(cur_bit_idx)) != 0) && ((PSD_bitmap[cur_byte_idx]& BIT(cur_bit_idx+1)) != 0))
 805                                                 H2C_PSD_DATA[i] = H2C_PSD_DATA[i] | (u1Byte) (1 << n);
 806                                 }
 807                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("H2C_PSD_DATA[%d]=0x%x\n" ,i, H2C_PSD_DATA[i]));
 808                         }
 809
 810                         //3 To Compare the difference
 811                         for ( i=0;i<5;i++)
 812                         {
 813                                 if(H2C_PSD_DATA[i] !=H2C_PSD_DATA_last[i])
 814                                 {
 815                                         FillH2CCmd92C(Adapter, H2C_92C_PSD_RESULT, 5, H2C_PSD_DATA);
 816                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_PSD, DBG_LOUD,("Need to Update the AFH Map \n"));
 817                                         break;
 818                                 }
 819                                 else
 820                                 {
 821                                         if(i==5)
 822                                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("Not need to Update\n"));
 823                                 }
 824                         }
 825                         if(pDM_Odm->bBtHsOperation)
 826                         {
 827                                 ODM_SetTimer(pDM_Odm, &pDM_Odm->PSDTimer, 10000);
 828                                 ODM_RT_TRACE(   pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("Leave dm_PSD_Monitor\n"));
 829                         }
 830                         else
 831                         {
 832                                 ODM_SetTimer(pDM_Odm, &pDM_Odm->PSDTimer, 1500);
 833                                 ODM_RT_TRACE(   pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("Leave dm_PSD_Monitor\n"));
 834                 }
 835         }
 836     }
 837 }
 838 /*
 839 //Neil for Get BT RSSI
 840 // Be Triggered by BT C2H CMD
 841 VOID
 842 ODM_PSDGetRSSI(
 843         IN      u1Byte  RSSI_BT)
 844 {
 845
 846
 847 }
 848
 849 */
 850
 851 VOID
 852 ODM_PSDMonitor(
 853         IN              PVOID                   pDM_VOID
 854         )
 855 {
 856         PDM_ODM_T                               pDM_Odm = (PDM_ODM_T)pDM_VOID;
 857         //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
 858
 859         //if(IS_HARDWARE_TYPE_8723AE(Adapter))
 860
 861         if(pDM_Odm->SupportICType == ODM_RTL8723A)   //may need to add other IC type
 862         {
 863                 if(pDM_Odm->SupportInterface==ODM_ITRF_PCIE)
 864                 {
 865                         if(!pDM_Odm->bBtEnabled) //need to check upper layer connection
 866                         {
 867                                 pDM_Odm->bPSDactive=FALSE;
 868                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD, ("odm_PSDMonitor, return for BT is disabled!!!\n"));
 869                                 return;
 870                         }
 871
 872                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD, ("odm_PSDMonitor\n"));
 873                 //{
 874                         pDM_Odm->bPSDinProcess = TRUE;
 875                         pDM_Odm->bPSDactive=TRUE;
 876                         odm_PSD_Monitor(pDM_Odm);
 877                         pDM_Odm->bPSDinProcess = FALSE;
 878                 }
 879         }
 880
 881 }
 882 VOID
 883 odm_PSDMonitorCallback(
 884         PRT_TIMER               pTimer
 885 )
 886 {
 887         PADAPTER                Adapter = (PADAPTER)pTimer->Adapter;
 888        HAL_DATA_TYPE    *pHalData = GET_HAL_DATA(Adapter);
 889
 890         PlatformScheduleWorkItem(&pHalData->PSDMonitorWorkitem);
 891 }
 892
 893 VOID
 894 odm_PSDMonitorWorkItemCallback(
 895     IN PVOID            pContext
 896     )
 897 {
 898         PADAPTER        Adapter = (PADAPTER)pContext;
 899         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 900         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;
 901
 902         ODM_PSDMonitor(pDM_Odm);
 903 }
 904
 905
 906  //cosa debug tool need to modify
 907
 908 VOID
 909 ODM_PSDDbgControl(
 910         IN      PADAPTER        Adapter,
 911         IN      u4Byte          mode,
 912         IN      u4Byte          btRssi
 913         )
 914 {
 915 #if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
 916         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 917         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;
 918
 919         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD, (" Monitor mode=%d, btRssi=%d\n", mode, btRssi));
 920         if(mode)
 921         {
 922                 pDM_Odm->RSSI_BT = (u1Byte)btRssi;
 923                 pDM_Odm->bUserAssignLevel = TRUE;
 924                 ODM_SetTimer( pDM_Odm, &pDM_Odm->PSDTimer, 0); //ms
 925         }
 926         else
 927         {
 928                 ODM_CancelTimer(pDM_Odm, &pDM_Odm->PSDTimer);
 929         }
 930 #endif
 931 }
 932
 933
 934 //#if(DEV_BUS_TYPE == RT_PCI_INTERFACE)|(DEV_BUS_TYPE == RT_USB_INTERFACE)
 935
 936 void    odm_RXHPInit(
 937         IN              PVOID                   pDM_VOID)
 938 {
 939 #if (DEV_BUS_TYPE == RT_PCI_INTERFACE)|(DEV_BUS_TYPE == RT_USB_INTERFACE)
 940         PDM_ODM_T                               pDM_Odm = (PDM_ODM_T)pDM_VOID;
 941         pRXHP_T                 pRX_HP_Table  = &pDM_Odm->DM_RXHP_Table;
 942         u1Byte                  index;
 943
 944         pRX_HP_Table->RXHP_enable = TRUE;
 945         pRX_HP_Table->RXHP_flag = 0;
 946         pRX_HP_Table->PSD_func_trigger = 0;
 947         pRX_HP_Table->Pre_IGI = 0x20;
 948         pRX_HP_Table->Cur_IGI = 0x20;
 949         pRX_HP_Table->Cur_pw_th = pw_th_10dB;
 950         pRX_HP_Table->Pre_pw_th = pw_th_10dB;
 951         for(index=0; index<80; index++)
 952                 pRX_HP_Table->PSD_bitmap_RXHP[index] = 1;
 953
 954 #if(DEV_BUS_TYPE == RT_USB_INTERFACE)
 955         pRX_HP_Table->TP_Mode = Idle_Mode;
 956 #endif
 957 #endif
 958 }
 959
 960 VOID
 961 odm_PSD_RXHP(
 962         IN              PVOID                   pDM_VOID
 963 )
 964 {
 965         PDM_ODM_T                               pDM_Odm = (PDM_ODM_T)pDM_VOID;
 966         pRXHP_T                 pRX_HP_Table  = &pDM_Odm->DM_RXHP_Table;
 967         PADAPTER                Adapter =  pDM_Odm->Adapter;
 968         PMGNT_INFO              pMgntInfo = &(Adapter->MgntInfo);
 969         unsigned int            pts, start_point, stop_point, initial_gain ;
 970         static u1Byte           PSD_bitmap_memory[80], init_memory = 0;
 971         static u1Byte           psd_cnt=0;
 972         static u4Byte           PSD_report[80], PSD_report_tmp;
 973         static u8Byte           lastTxOkCnt=0, lastRxOkCnt=0;
 974         u1Byte                  idx[20]={96,99,102,106,109,112,115,118,122,125,
 975                                         0,3,6,10,13,16,19,22,26,29};
 976         u1Byte                  n, i, channel, BBReset,tone_idx;
 977         u1Byte                  PSD_bitmap[10]/*, SSBT=0*/,initial_gain_psd=0, RSSI_BT=0, initialGainUpper;
 978         s4Byte                          PSD_skip_start, PSD_skip_stop;
 979         u4Byte                  CurrentChannel, RXIQI, RxIdleLowPwr, wlan_channel;
 980         u4Byte                  ReScan, Interval, Is40MHz;
 981         u8Byte                  curTxOkCnt, curRxOkCnt;
 982         //--------------2G band synthesizer for 92D switch RF channel using-----------------
 983         u1Byte                  group_idx=0;
 984         u4Byte                  SYN_RF25=0, SYN_RF26=0, SYN_RF27=0, SYN_RF2B=0, SYN_RF2C=0;
 985         u4Byte                  SYN[5] = {0x25, 0x26, 0x27, 0x2B, 0x2C};    // synthesizer RF register for 2G channel
 986         u4Byte                  SYN_group[3][5] = {{0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840},     // For CH1,2,4,9,10.11.12   {0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840}
 987                                                                             {0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840},     // For CH3,13,14
 988                                                                             {0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41}};   // For Ch5,6,7,8
 989        //--------------------- Add by Gary for Debug setting ----------------------
 990         u1Byte                 RSSI_BT_new = (u1Byte) ODM_GetBBReg(pDM_Odm, 0xB9C, 0xFF);
 991        u1Byte                 rssi_ctrl = (u1Byte) ODM_GetBBReg(pDM_Odm, 0xB38, 0xFF);
 992        //---------------------------------------------------------------------
 993
 994         if(pMgntInfo->bScanInProgress)
 995         {
 996                 return;
 997         }
 998
 999         ReScan = PSD_RESCAN;
1000         Interval = SCAN_INTERVAL;
1001
1002
1003         //1 Initialization
1004         if(init_memory == 0)
1005         {
1006                 RT_TRACE(       ODM_COMP_PSD, DBG_LOUD,("Init memory\n"));
1007                 for(i = 0; i < 80; i++)
1008                         PSD_bitmap_memory[i] = 0xFF; // channel is always good
1009                 init_memory = 1;
1010         }
1011         if(psd_cnt == 0)
1012         {
1013                 RT_TRACE(ODM_COMP_PSD, DBG_LOUD,("Enter dm_PSD_Monitor\n"));
1014                 for(i = 0; i < 80; i++)
1015                         PSD_report[i] = 0;
1016         }
1017
1018         //1 Backup Current Settings
1019         CurrentChannel = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask);
1020         if(pDM_Odm->SupportICType == ODM_RTL8192D)
1021         {
1022                 //2 Record Current synthesizer parameters based on current channel
1023                 if((*(pDM_Odm->pMacPhyMode)==ODM_SMSP)||(*(pDM_Odm->pMacPhyMode)==ODM_DMSP))
1024                 {
1025                         SYN_RF25 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x25, bMaskDWord);
1026                         SYN_RF26 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x26, bMaskDWord);
1027                         SYN_RF27 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x27, bMaskDWord);
1028                         SYN_RF2B = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x2B, bMaskDWord);
1029                         SYN_RF2C = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x2C, bMaskDWord);
1030         }
1031                 else     // DualMAC_DualPHY 2G
1032                 {
1033                         SYN_RF25 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x25, bMaskDWord);
1034                         SYN_RF26 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x26, bMaskDWord);
1035                         SYN_RF27 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x27, bMaskDWord);
1036                         SYN_RF2B = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2B, bMaskDWord);
1037                         SYN_RF2C = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2C, bMaskDWord);
1038                 }
1039         }
1040         RXIQI = ODM_GetBBReg(pDM_Odm, 0xC14, bMaskDWord);
1041         RxIdleLowPwr = (ODM_GetBBReg(pDM_Odm, 0x818, bMaskDWord)&BIT28)>>28;
1042         Is40MHz = *(pDM_Odm->pBandWidth);
1043         ODM_RT_TRACE(pDM_Odm,   ODM_COMP_PSD, DBG_LOUD,("PSD Scan Start\n"));
1044         //1 Turn off CCK
1045         ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0);
1046         //1 Turn off TX
1047         //Pause TX Queue
1048         ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF);
1049         //Force RX to stop TX immediately
1050         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x32E13);
1051         //1 Turn off RX
1052         //Rx AGC off  RegC70[0]=0, RegC7C[20]=0
1053         ODM_SetBBReg(pDM_Odm, 0xC70, BIT0, 0);
1054         ODM_SetBBReg(pDM_Odm, 0xC7C, BIT20, 0);
1055         //Turn off CCA
1056         ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, 0x0);
1057         //BB Reset
1058         ODM_SetBBReg(pDM_Odm, 0x87C, BIT31, 1); //clock gated to prevent from AGC table mess
1059         BBReset = ODM_Read1Byte(pDM_Odm, 0x02);
1060         ODM_Write1Byte(pDM_Odm, 0x02, BBReset&(~BIT0));
1061         ODM_Write1Byte(pDM_Odm, 0x02, BBReset|BIT0);
1062         ODM_SetBBReg(pDM_Odm, 0x87C, BIT31, 0);
1063         //1 Leave RX idle low power
1064         ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0);
1065         //1 Fix initial gain
1066         RSSI_BT = RSSI_BT_new;
1067         RT_TRACE(ODM_COMP_PSD, DBG_LOUD,("PSD: RSSI_BT= %d\n", RSSI_BT));
1068
1069         if(rssi_ctrl == 1)        // just for debug!!
1070                 initial_gain_psd = RSSI_BT_new;
1071         else
1072                 initial_gain_psd = pDM_Odm->RSSI_Min;    // PSD report based on RSSI
1073
1074         RT_TRACE(ODM_COMP_PSD, DBG_LOUD,("PSD: RSSI_BT= %d\n", RSSI_BT));
1075
1076         initialGainUpper = 0x54;
1077
1078         RSSI_BT = initial_gain_psd;
1079         //SSBT = RSSI_BT;
1080
1081         //RT_TRACE(     ODM_COMP_PSD, DBG_LOUD,("PSD: SSBT= %d\n", SSBT));
1082         RT_TRACE(       ODM_COMP_PSD, DBG_LOUD,("PSD: initial gain= 0x%x\n", initial_gain_psd));
1083
1084         pDM_Odm->bDMInitialGainEnable = FALSE;
1085         initial_gain = ODM_GetBBReg(pDM_Odm, 0xc50, bMaskDWord) & 0x7F;
1086         //ODM_SetBBReg(pDM_Odm, 0xc50, 0x7F, initial_gain_psd);
1087         ODM_Write_DIG(pDM_Odm, initial_gain_psd);
1088         //1 Turn off 3-wire
1089         ODM_SetBBReg(pDM_Odm, 0x88c, BIT20|BIT21|BIT22|BIT23, 0xF);
1090
1091         //pts value = 128, 256, 512, 1024
1092         pts = 128;
1093
1094         if(pts == 128)
1095         {
1096                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x0);
1097                 start_point = 64;
1098                 stop_point = 192;
1099         }
1100         else if(pts == 256)
1101         {
1102                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x1);
1103                 start_point = 128;
1104                 stop_point = 384;
1105         }
1106         else if(pts == 512)
1107         {
1108                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x2);
1109                 start_point = 256;
1110                 stop_point = 768;
1111         }
1112         else
1113         {
1114                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x3);
1115                 start_point = 512;
1116                 stop_point = 1536;
1117         }
1118
1119
1120 //3 Skip WLAN channels if WLAN busy
1121         curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast) - lastTxOkCnt;
1122         curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast) - lastRxOkCnt;
1123         lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast);
1124         lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast);
1125
1126         PSD_skip_start=80;
1127         PSD_skip_stop = 0;
1128         wlan_channel = CurrentChannel & 0x0f;
1129
1130         RT_TRACE(ODM_COMP_PSD,DBG_LOUD,("PSD: current channel: %x, BW:%d \n", wlan_channel, Is40MHz));
1131
1132         if((curRxOkCnt+curTxOkCnt) > 1000)
1133         {
1134                 PSD_skip_start = (wlan_channel-1)*5 -Is40MHz*10;
1135                 PSD_skip_stop = PSD_skip_start + (1+Is40MHz)*20;
1136         }
1137
1138         RT_TRACE(ODM_COMP_PSD,DBG_LOUD,("PSD: Skip tone from %d to %d \n", PSD_skip_start, PSD_skip_stop));
1139
1140         for (n=0;n<80;n++)
1141         {
1142                 if((n%20)==0)
1143                 {
1144                         channel = (n/20)*4 + 1;
1145                         if(pDM_Odm->SupportICType == ODM_RTL8192D)
1146                         {
1147                                 switch(channel)
1148                                 {
1149                                         case 1:
1150                                         case 9:
1151                                                 group_idx = 0;
1152                                                 break;
1153                                         case 5:
1154                                                 group_idx = 2;
1155                                                 break;
1156                                         case 13:
1157                                                 group_idx = 1;
1158                                                 break;
1159                                 }
1160                                 if((*(pDM_Odm->pMacPhyMode)==ODM_SMSP)||(*(pDM_Odm->pMacPhyMode)==ODM_DMSP))
1161                 {
1162                                         for(i = 0; i < SYN_Length; i++)
1163                                                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, SYN[i], bMaskDWord, SYN_group[group_idx][i]);
1164
1165                                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, channel);
1166                                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_CHNLBW, 0x3FF, channel);
1167                                 }
1168                                 else  // DualMAC_DualPHY 2G
1169                         {
1170                                         for(i = 0; i < SYN_Length; i++)
1171                                                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, SYN[i], bMaskDWord, SYN_group[group_idx][i]);
1172
1173                                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, channel);
1174                                 }
1175                         }
1176                         else
1177                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, channel);
1178                         }
1179                 tone_idx = n%20;
1180                 if ((n>=PSD_skip_start) && (n<PSD_skip_stop))
1181                 {
1182                         PSD_report[n] = initial_gain_psd;//SSBT;
1183                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD,DBG_LOUD,("PSD:Tone %d skipped \n", n));
1184                 }
1185                 else
1186                 {
1187                         PSD_report_tmp =  GetPSDData(pDM_Odm, idx[tone_idx], initial_gain_psd);
1188
1189                         if ( PSD_report_tmp > PSD_report[n])
1190                                 PSD_report[n] = PSD_report_tmp;
1191
1192                 }
1193         }
1194
1195         PatchDCTone(pDM_Odm, PSD_report, initial_gain_psd);
1196
1197        //----end
1198         //1 Turn on RX
1199         //Rx AGC on
1200         ODM_SetBBReg(pDM_Odm, 0xC70, BIT0, 1);
1201         ODM_SetBBReg(pDM_Odm, 0xC7C, BIT20, 1);
1202         //CCK on
1203         ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 1);
1204         //1 Turn on TX
1205         //Resume TX Queue
1206         ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00);
1207         //Turn on 3-wire
1208         ODM_SetBBReg(pDM_Odm, 0x88c, BIT20|BIT21|BIT22|BIT23, 0x0);
1209         //1 Restore Current Settings
1210         //Resume DIG
1211         pDM_Odm->bDMInitialGainEnable= TRUE;
1212         //ODM_SetBBReg(pDM_Odm, 0xc50, 0x7F, initial_gain);
1213         ODM_Write_DIG(pDM_Odm,(u1Byte) initial_gain);
1214         // restore originl center frequency
1215         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, CurrentChannel);
1216         if(pDM_Odm->SupportICType == ODM_RTL8192D)
1217         {
1218                 if((*(pDM_Odm->pMacPhyMode)==ODM_SMSP)||(*(pDM_Odm->pMacPhyMode)==ODM_DMSP))
1219                 {
1220                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_CHNLBW, bMaskDWord, CurrentChannel);
1221                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x25, bMaskDWord, SYN_RF25);
1222                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x26, bMaskDWord, SYN_RF26);
1223                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x27, bMaskDWord, SYN_RF27);
1224                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x2B, bMaskDWord, SYN_RF2B);
1225                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x2C, bMaskDWord, SYN_RF2C);
1226                 }
1227                 else     // DualMAC_DualPHY
1228                 {
1229                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x25, bMaskDWord, SYN_RF25);
1230                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x26, bMaskDWord, SYN_RF26);
1231                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x27, bMaskDWord, SYN_RF27);
1232                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2B, bMaskDWord, SYN_RF2B);
1233                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2C, bMaskDWord, SYN_RF2C);
1234                 }
1235         }
1236         //Turn on CCA
1237         ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, RXIQI);
1238         //Restore RX idle low power
1239         if(RxIdleLowPwr == TRUE)
1240                 ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 1);
1241
1242         psd_cnt++;
1243         //gPrint("psd cnt=%d\n", psd_cnt);
1244         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD:psd_cnt = %d \n",psd_cnt));
1245         if (psd_cnt < ReScan)
1246         {
1247                 ODM_SetTimer(pDM_Odm, &pRX_HP_Table->PSDTimer, Interval);  //ms
1248         }
1249         else
1250         {
1251                 psd_cnt = 0;
1252                 for(i=0;i<80;i++)
1253                         RT_TRACE(       ODM_COMP_PSD, DBG_LOUD,("psd_report[%d]=     %d \n", 2402+i, PSD_report[i]));
1254                         //DbgPrint("psd_report[%d]=     %d \n", 2402+i, PSD_report[i]);
1255
1256                 GoodChannelDecision(pDM_Odm, PSD_report, PSD_bitmap,RSSI_BT, PSD_bitmap_memory);
1257
1258         }
1259 }
1260
1261 void odm_Write_RXHP(
1262         IN              PVOID                   pDM_VOID)
1263 {
1264         PDM_ODM_T                               pDM_Odm = (PDM_ODM_T)pDM_VOID;
1265         pRXHP_T         pRX_HP_Table = &pDM_Odm->DM_RXHP_Table;
1266         u4Byte          currentIGI;
1267
1268         if(pRX_HP_Table->Cur_IGI != pRX_HP_Table->Pre_IGI)
1269         {
1270                 ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0, pRX_HP_Table->Cur_IGI);
1271                 ODM_SetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0, pRX_HP_Table->Cur_IGI);
1272         }
1273
1274         if(pRX_HP_Table->Cur_pw_th != pRX_HP_Table->Pre_pw_th)
1275 {
1276                 ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore2, BIT8|BIT9, pRX_HP_Table->Cur_pw_th);  // RegC54[9:8]=2'b11:  AGC Flow 3
1277         }
1278
1279         if(pRX_HP_Table->RXHP_flag == 0)
1280         {
1281                 pRX_HP_Table->Cur_IGI = 0x20;
1282         }
1283         else
1284         {
1285                 currentIGI = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0);
1286                 if(currentIGI<0x50)
1287                 {
1288                         ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0, pRX_HP_Table->Cur_IGI);
1289                         ODM_SetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0, pRX_HP_Table->Cur_IGI);
1290                 }
1291         }
1292         pRX_HP_Table->Pre_IGI = pRX_HP_Table->Cur_IGI;
1293         pRX_HP_Table->Pre_pw_th = pRX_HP_Table->Cur_pw_th;
1294
1295 }
1296
1297
1298 void odm_RXHP(
1299         IN              PVOID                   pDM_VOID)
1300 {
1301 #if( DM_ODM_SUPPORT_TYPE & (ODM_WIN))
1302 #if (DEV_BUS_TYPE == RT_PCI_INTERFACE) | (DEV_BUS_TYPE == RT_USB_INTERFACE)
1303         PDM_ODM_T                               pDM_Odm = (PDM_ODM_T)pDM_VOID;
1304         PADAPTER        Adapter =  pDM_Odm->Adapter;
1305         PMGNT_INFO      pMgntInfo = &(Adapter->MgntInfo);
1306         pDIG_T          pDM_DigTable = &pDM_Odm->DM_DigTable;
1307         pRXHP_T         pRX_HP_Table  = &pDM_Odm->DM_RXHP_Table;
1308         PFALSE_ALARM_STATISTICS         FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_FALSEALMCNT);
1309
1310         u1Byte                  i, j, sum;
1311         u1Byte                  Is40MHz;
1312         s1Byte                  Intf_diff_idx, MIN_Intf_diff_idx = 16;
1313        s4Byte                   cur_channel;
1314        u1Byte                   ch_map_intf_5M[17] = {0};
1315        static u4Byte            FA_TH = 0;
1316         static u1Byte           psd_intf_flag = 0;
1317         static s4Byte           curRssi = 0;
1318        static s4Byte            preRssi = 0;
1319         static u1Byte           PSDTriggerCnt = 1;
1320
1321         u1Byte                  RX_HP_enable = (u1Byte)(ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore2, bMaskDWord)>>31);   // for debug!!
1322
1323 #if(DEV_BUS_TYPE == RT_USB_INTERFACE)
1324         static s8Byte           lastTxOkCnt = 0, lastRxOkCnt = 0;
1325        s8Byte                   curTxOkCnt, curRxOkCnt;
1326         s8Byte                  curTPOkCnt;
1327         s8Byte                  TP_Acc3, TP_Acc5;
1328         static s8Byte           TP_Buff[5] = {0};
1329         static u1Byte           pre_state = 0, pre_state_flag = 0;
1330         static u1Byte           Intf_HighTP_flag = 0, De_counter = 16;
1331         static u1Byte           TP_Degrade_flag = 0;
1332 #endif
1333         static u1Byte           LatchCnt = 0;
1334
1335         if(pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8188E))
1336                 return;
1337         //AGC RX High Power Mode is only applied on 2G band in 92D!!!
1338         if(pDM_Odm->SupportICType == ODM_RTL8192D)
1339         {
1340                 if(*(pDM_Odm->pBandType) != ODM_BAND_2_4G)
1341                         return;
1342         }
1343
1344         if(!(pDM_Odm->SupportAbility & ODM_BB_RXHP))
1345                 return;
1346
1347
1348         //RX HP ON/OFF
1349         if(RX_HP_enable == 1)
1350                 pRX_HP_Table->RXHP_enable = FALSE;
1351         else
1352                 pRX_HP_Table->RXHP_enable = TRUE;
1353
1354         if(pRX_HP_Table->RXHP_enable == FALSE)
1355         {
1356                 if(pRX_HP_Table->RXHP_flag == 1)
1357                 {
1358                         pRX_HP_Table->RXHP_flag = 0;
1359                         psd_intf_flag = 0;
1360                 }
1361                 return;
1362         }
1363
1364 #if(DEV_BUS_TYPE == RT_USB_INTERFACE)
1365         //2 Record current TP for USB interface
1366         curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast)-lastTxOkCnt;
1367         curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast)-lastRxOkCnt;
1368         lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast);
1369         lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast);
1370
1371         curTPOkCnt = curTxOkCnt+curRxOkCnt;
1372         TP_Buff[0] = curTPOkCnt;    // current TP
1373         TP_Acc3 = PlatformDivision64((TP_Buff[1]+TP_Buff[2]+TP_Buff[3]), 3);
1374         TP_Acc5 = PlatformDivision64((TP_Buff[0]+TP_Buff[1]+TP_Buff[2]+TP_Buff[3]+TP_Buff[4]), 5);
1375
1376         if(TP_Acc5 < 1000)
1377                 pRX_HP_Table->TP_Mode = Idle_Mode;
1378         else if((1000 < TP_Acc5)&&(TP_Acc5 < 3750000))
1379                 pRX_HP_Table->TP_Mode = Low_TP_Mode;
1380         else
1381                 pRX_HP_Table->TP_Mode = High_TP_Mode;
1382
1383         ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP TP Mode = %d\n", pRX_HP_Table->TP_Mode));
1384         // Since TP result would be sampled every 2 sec, it needs to delay 4sec to wait PSD processing.
1385         // When LatchCnt = 0, we would Get PSD result.
1386         if(TP_Degrade_flag == 1)
1387         {
1388                 LatchCnt--;
1389                 if(LatchCnt == 0)
1390                 {
1391                         TP_Degrade_flag = 0;
1392                 }
1393         }
1394         // When PSD function triggered by TP degrade 20%, and Interference Flag = 1
1395         // Set a De_counter to wait IGI = upper bound. If time is UP, the Interference flag will be pull down.
1396         if(Intf_HighTP_flag == 1)
1397         {
1398                 De_counter--;
1399                 if(De_counter == 0)
1400                 {
1401                         Intf_HighTP_flag = 0;
1402                         psd_intf_flag = 0;
1403                 }
1404         }
1405 #endif
1406
1407         //2 AGC RX High Power Mode by PSD only applied to STA Mode
1408         //3 NOT applied 1. Ad Hoc Mode.
1409         //3 NOT applied 2. AP Mode
1410         if ((pMgntInfo->mAssoc) && (!pMgntInfo->mIbss) && (!ACTING_AS_AP(Adapter)))
1411         {
1412                 Is40MHz = *(pDM_Odm->pBandWidth);
1413                 curRssi = pDM_Odm->RSSI_Min;
1414                 cur_channel = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x0fff) & 0x0f;
1415
1416                 /* check illegal channel and bandwidth */
1417                 if (Is40MHz && ((cur_channel < 3) || (cur_channel > 12))) {
1418                         ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("illegal channel setting, 40MHz channel = %d\n", cur_channel));
1419                         return;
1420                 }
1421
1422                 ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP RX HP flag = %d\n", pRX_HP_Table->RXHP_flag));
1423                 ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP FA = %d\n", FalseAlmCnt->Cnt_all));
1424                 ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP cur RSSI = %d, pre RSSI=%d\n", curRssi, preRssi));
1425                 ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP current CH = %d\n", cur_channel));
1426                 ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP Is 40MHz = %d\n", Is40MHz));
1427         //2 PSD function would be triggered
1428         //3 1. Every 4 sec for PCIE
1429         //3 2. Before TP Mode (Idle TP<4kbps) for USB
1430         //3 3. After TP Mode (High TP) for USB
1431                 if((curRssi > 68) && (pRX_HP_Table->RXHP_flag == 0))    // Only RSSI>TH and RX_HP_flag=0 will Do PSD process
1432                 {
1433 #if (DEV_BUS_TYPE == RT_USB_INTERFACE)
1434                         //2 Before TP Mode ==> PSD would be trigger every 4 sec
1435                         if(pRX_HP_Table->TP_Mode == Idle_Mode)          //2.1 less wlan traffic <4kbps
1436                         {
1437 #endif
1438                                 if(PSDTriggerCnt == 1)
1439                                 {
1440                                         odm_PSD_RXHP(pDM_Odm);
1441                                         pRX_HP_Table->PSD_func_trigger = 1;
1442                                         PSDTriggerCnt = 0;
1443                                 }
1444                                 else
1445                                 {
1446                                         PSDTriggerCnt++;
1447                                 }
1448 #if(DEV_BUS_TYPE == RT_USB_INTERFACE)
1449                         }
1450                         //2 After TP Mode ==> Check if TP degrade larger than 20% would trigger PSD function
1451                         if(pRX_HP_Table->TP_Mode == High_TP_Mode)
1452                         {
1453                                 if((pre_state_flag == 0)&&(LatchCnt == 0))
1454                                 {
1455                                         // TP var < 5%
1456                                         if((((curTPOkCnt-TP_Acc3)*20)<(TP_Acc3))&&(((curTPOkCnt-TP_Acc3)*20)>(-TP_Acc3)))
1457                                         {
1458                                                 pre_state++;
1459                                                 if(pre_state == 3)      // hit pre_state condition => consecutive 3 times
1460                                                 {
1461                                                         pre_state_flag = 1;
1462                                                         pre_state = 0;
1463                                                 }
1464
1465                                         }
1466                                         else
1467                                         {
1468                                                 pre_state = 0;
1469                                         }
1470                                 }
1471                                 //3 If pre_state_flag=1 ==> start to monitor TP degrade 20%
1472                                 if(pre_state_flag == 1)
1473                                 {
1474                                         if(((TP_Acc3-curTPOkCnt)*5)>(TP_Acc3))      // degrade 20%
1475                                         {
1476                                                 odm_PSD_RXHP(pDM_Odm);
1477                                                 pRX_HP_Table->PSD_func_trigger = 1;
1478                                                 TP_Degrade_flag = 1;
1479                                                 LatchCnt = 2;
1480                                                 pre_state_flag = 0;
1481                                         }
1482                                         else if(((TP_Buff[2]-curTPOkCnt)*5)>TP_Buff[2])
1483                                         {
1484                                                 odm_PSD_RXHP(pDM_Odm);
1485                                                 pRX_HP_Table->PSD_func_trigger = 1;
1486                                                 TP_Degrade_flag = 1;
1487                                                 LatchCnt = 2;
1488                                                 pre_state_flag = 0;
1489                                         }
1490                                         else if(((TP_Buff[3]-curTPOkCnt)*5)>TP_Buff[3])
1491                                         {
1492                                                 odm_PSD_RXHP(pDM_Odm);
1493                                                 pRX_HP_Table->PSD_func_trigger = 1;
1494                                                 TP_Degrade_flag = 1;
1495                                                 LatchCnt = 2;
1496                                                 pre_state_flag = 0;
1497                                         }
1498                                 }
1499                         }
1500 #endif
1501 }
1502
1503 #if (DEV_BUS_TYPE == RT_USB_INTERFACE)
1504                 for (i=0;i<4;i++)
1505                 {
1506                         TP_Buff[4-i] = TP_Buff[3-i];
1507                 }
1508 #endif
1509                 //2 Update PSD bitmap according to PSD report
1510                 if((pRX_HP_Table->PSD_func_trigger == 1)&&(LatchCnt == 0))
1511                 {
1512                         //2 Separate 80M bandwidth into 16 group with smaller 5M BW.
1513                         for (i = 0 ; i < 16 ; i++)
1514                         {
1515                                 sum = 0;
1516                                 for(j = 0; j < 5 ; j++)
1517                                         sum += pRX_HP_Table->PSD_bitmap_RXHP[5*i + j];
1518
1519                                 if(sum < 5)
1520                                 {
1521                                         ch_map_intf_5M[i] = 1;  // interference flag
1522                                 }
1523                         }
1524                         //=============just for debug=========================
1525                         //for(i=0;i<16;i++)
1526                                 //DbgPrint("RX HP: ch_map_intf_5M[%d] = %d\n", i, ch_map_intf_5M[i]);
1527                         //===============================================
1528                         //2 Mask target channel 5M index
1529                         for(i = 0; i < (4+4*Is40MHz) ; i++)
1530                         {
1531                                 ch_map_intf_5M[cur_channel - (1+2*Is40MHz) + i] = 0;
1532                         }
1533
1534                         psd_intf_flag = 0;
1535                         for(i = 0; i < 16; i++)
1536                         {
1537                                 if(ch_map_intf_5M[i] == 1)
1538                         {
1539                                 psd_intf_flag = 1;            // interference is detected!!!
1540                                 break;
1541                                 }
1542                         }
1543
1544 #if (DEV_BUS_TYPE == RT_USB_INTERFACE)
1545                         if(pRX_HP_Table->TP_Mode!=Idle_Mode)
1546                         {
1547                                 if(psd_intf_flag == 1)     // to avoid psd_intf_flag always 1
1548                                 {
1549                                         Intf_HighTP_flag = 1;
1550                                         De_counter = 32;     // 0x1E -> 0x3E needs 32 times by each IGI step =1
1551                                 }
1552                         }
1553 #endif
1554                         ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP psd_intf_flag = %d\n", psd_intf_flag));
1555                         //2 Distance between target channel and interference
1556                         for(i = 0; i < 16; i++)
1557                         {
1558                                 if(ch_map_intf_5M[i] == 1)
1559                                 {
1560                                         Intf_diff_idx = ((cur_channel+Is40MHz-(i+1))>0) ? (s1Byte)(cur_channel-2*Is40MHz-(i-2)) : (s1Byte)((i+1)-(cur_channel+2*Is40MHz));
1561                                 if(Intf_diff_idx < MIN_Intf_diff_idx)
1562                                                 MIN_Intf_diff_idx = Intf_diff_idx;    // the min difference index between interference and target
1563                                 }
1564                         }
1565                         ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP MIN_Intf_diff_idx = %d\n", MIN_Intf_diff_idx));
1566                         //2 Choose False Alarm Threshold
1567                         switch (MIN_Intf_diff_idx){
1568                                 case 0:
1569                                 case 1:
1570                                 case 2:
1571                                 case 3:
1572                                         FA_TH = FA_RXHP_TH1;
1573                                 break;
1574                                 case 4:                         // CH5
1575                                 case 5:                         // CH6
1576                                         FA_TH = FA_RXHP_TH2;
1577                                 break;
1578                                 case 6:                         // CH7
1579                                 case 7:                         // CH8
1580                                         FA_TH = FA_RXHP_TH3;
1581                                         break;
1582                         case 8:                         // CH9
1583                                 case 9:                         //CH10
1584                                         FA_TH = FA_RXHP_TH4;
1585                                         break;
1586                                 case 10:
1587                                 case 11:
1588                                 case 12:
1589                                 case 13:
1590                                 case 14:
1591                                 case 15:
1592                                         FA_TH = FA_RXHP_TH5;
1593                                         break;
1594                 }
1595                         ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP FA_TH = %d\n", FA_TH));
1596                         pRX_HP_Table->PSD_func_trigger = 0;
1597                 }
1598                 //1 Monitor RSSI variation to choose the suitable IGI or Exit AGC RX High Power Mode
1599                 if(pRX_HP_Table->RXHP_flag == 1)
1600                 {
1601                 if ((curRssi > 80)&&(preRssi < 80))
1602                 {
1603                                 pRX_HP_Table->Cur_IGI = LNA_Low_Gain_1;
1604                 }
1605                 else if ((curRssi < 80)&&(preRssi > 80))
1606                 {
1607                                 pRX_HP_Table->Cur_IGI = LNA_Low_Gain_2;
1608                         }
1609                 else if ((curRssi > 72)&&(preRssi < 72))
1610                         {
1611                                 pRX_HP_Table->Cur_IGI = LNA_Low_Gain_2;
1612                 }
1613                 else if ((curRssi < 72)&&( preRssi > 72))
1614                         {
1615                                 pRX_HP_Table->Cur_IGI = LNA_Low_Gain_3;
1616                 }
1617                 else if (curRssi < 68)           //RSSI is NOT large enough!!==> Exit AGC RX High Power Mode
1618                 {
1619                                 pRX_HP_Table->Cur_pw_th = pw_th_10dB;
1620                                 pRX_HP_Table->RXHP_flag = 0;    // Back to Normal DIG Mode
1621                                 psd_intf_flag = 0;
1622                         }
1623                 }
1624                 else    // pRX_HP_Table->RXHP_flag == 0
1625                 {
1626                         //1 Decide whether to enter AGC RX High Power Mode
1627                         if ((curRssi > 70) && (psd_intf_flag == 1) && (FalseAlmCnt->Cnt_all > FA_TH) &&
1628                                 (pDM_DigTable->CurIGValue == pDM_DigTable->rx_gain_range_max))
1629                         {
1630                                 if (curRssi > 80)
1631                                 {
1632                                         pRX_HP_Table->Cur_IGI = LNA_Low_Gain_1;
1633                                 }
1634                                 else if (curRssi > 72)
1635                         {
1636                                 pRX_HP_Table->Cur_IGI = LNA_Low_Gain_2;
1637                                 }
1638                                 else
1639                                 {
1640                                         pRX_HP_Table->Cur_IGI = LNA_Low_Gain_3;
1641                                 }
1642                                 pRX_HP_Table->Cur_pw_th = pw_th_16dB;           //RegC54[9:8]=2'b11: to enter AGC Flow 3
1643                                 pRX_HP_Table->First_time_enter = TRUE;
1644                                 pRX_HP_Table->RXHP_flag = 1;    //      RXHP_flag=1: AGC RX High Power Mode, RXHP_flag=0: Normal DIG Mode
1645                         }
1646                 }
1647                 preRssi = curRssi;
1648                 odm_Write_RXHP(pDM_Odm);
1649         }
1650 #endif //#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN))
1651 #endif //#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) | (DEV_BUS_TYPE == RT_USB_INTERFACE)
1652 }
1653
1654
1655 VOID
1656 odm_PSD_RXHPCallback(
1657         PRT_TIMER               pTimer
1658 )
1659 {
1660         PADAPTER                Adapter = (PADAPTER)pTimer->Adapter;
1661         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
1662         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;
1663         pRXHP_T                 pRX_HP_Table  = &pDM_Odm->DM_RXHP_Table;
1664
1665 #if DEV_BUS_TYPE==RT_PCI_INTERFACE
1666         #if USE_WORKITEM
1667         ODM_ScheduleWorkItem(&pRX_HP_Table->PSDTimeWorkitem);
1668         #else
1669         odm_PSD_RXHP(pDM_Odm);
1670         #endif
1671 #else
1672         ODM_ScheduleWorkItem(&pRX_HP_Table->PSDTimeWorkitem);
1673 #endif
1674
1675         }
1676
1677 VOID
1678 odm_PSD_RXHPWorkitemCallback(
1679     IN PVOID            pContext
1680     )
1681 {
1682         PADAPTER        pAdapter = (PADAPTER)pContext;
1683         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
1684         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;
1685
1686         odm_PSD_RXHP(pDM_Odm);
1687 }
1688
1689 #endif //#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)