rtl8723bu/include/hal_com.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20 #ifndef __HAL_COMMON_H__
  21 #define __HAL_COMMON_H__
  22
  23 #include "HalVerDef.h"
  24 #include "hal_pg.h"
  25 #include "hal_phy.h"
  26 #include "hal_phy_reg.h"
  27 #include "hal_com_reg.h"
  28 #include "hal_com_phycfg.h"
  29 #include "../hal/hal_com_c2h.h"
  30
  31 /*------------------------------ Tx Desc definition Macro ------------------------*/
  32 //#pragma mark -- Tx Desc related definition. --
  33 //----------------------------------------------------------------------------
  34 //-----------------------------------------------------------
  35 //      Rate
  36 //-----------------------------------------------------------
  37 // CCK Rates, TxHT = 0
  38 #define DESC_RATE1M                                     0x00
  39 #define DESC_RATE2M                                     0x01
  40 #define DESC_RATE5_5M                           0x02
  41 #define DESC_RATE11M                            0x03
  42
  43 // OFDM Rates, TxHT = 0
  44 #define DESC_RATE6M                                     0x04
  45 #define DESC_RATE9M                                     0x05
  46 #define DESC_RATE12M                            0x06
  47 #define DESC_RATE18M                            0x07
  48 #define DESC_RATE24M                            0x08
  49 #define DESC_RATE36M                            0x09
  50 #define DESC_RATE48M                            0x0a
  51 #define DESC_RATE54M                            0x0b
  52
  53 // MCS Rates, TxHT = 1
  54 #define DESC_RATEMCS0                           0x0c
  55 #define DESC_RATEMCS1                           0x0d
  56 #define DESC_RATEMCS2                           0x0e
  57 #define DESC_RATEMCS3                           0x0f
  58 #define DESC_RATEMCS4                           0x10
  59 #define DESC_RATEMCS5                           0x11
  60 #define DESC_RATEMCS6                           0x12
  61 #define DESC_RATEMCS7                           0x13
  62 #define DESC_RATEMCS8                           0x14
  63 #define DESC_RATEMCS9                           0x15
  64 #define DESC_RATEMCS10                          0x16
  65 #define DESC_RATEMCS11                          0x17
  66 #define DESC_RATEMCS12                          0x18
  67 #define DESC_RATEMCS13                          0x19
  68 #define DESC_RATEMCS14                          0x1a
  69 #define DESC_RATEMCS15                          0x1b
  70 #define DESC_RATEMCS16                          0x1C
  71 #define DESC_RATEMCS17                          0x1D
  72 #define DESC_RATEMCS18                          0x1E
  73 #define DESC_RATEMCS19                          0x1F
  74 #define DESC_RATEMCS20                          0x20
  75 #define DESC_RATEMCS21                          0x21
  76 #define DESC_RATEMCS22                          0x22
  77 #define DESC_RATEMCS23                          0x23
  78 #define DESC_RATEMCS24                          0x24
  79 #define DESC_RATEMCS25                          0x25
  80 #define DESC_RATEMCS26                          0x26
  81 #define DESC_RATEMCS27                          0x27
  82 #define DESC_RATEMCS28                          0x28
  83 #define DESC_RATEMCS29                          0x29
  84 #define DESC_RATEMCS30                          0x2A
  85 #define DESC_RATEMCS31                          0x2B
  86 #define DESC_RATEVHTSS1MCS0             0x2C
  87 #define DESC_RATEVHTSS1MCS1             0x2D
  88 #define DESC_RATEVHTSS1MCS2             0x2E
  89 #define DESC_RATEVHTSS1MCS3             0x2F
  90 #define DESC_RATEVHTSS1MCS4             0x30
  91 #define DESC_RATEVHTSS1MCS5             0x31
  92 #define DESC_RATEVHTSS1MCS6             0x32
  93 #define DESC_RATEVHTSS1MCS7             0x33
  94 #define DESC_RATEVHTSS1MCS8             0x34
  95 #define DESC_RATEVHTSS1MCS9             0x35
  96 #define DESC_RATEVHTSS2MCS0             0x36
  97 #define DESC_RATEVHTSS2MCS1             0x37
  98 #define DESC_RATEVHTSS2MCS2             0x38
  99 #define DESC_RATEVHTSS2MCS3             0x39
 100 #define DESC_RATEVHTSS2MCS4             0x3A
 101 #define DESC_RATEVHTSS2MCS5             0x3B
 102 #define DESC_RATEVHTSS2MCS6             0x3C
 103 #define DESC_RATEVHTSS2MCS7             0x3D
 104 #define DESC_RATEVHTSS2MCS8             0x3E
 105 #define DESC_RATEVHTSS2MCS9             0x3F
 106 #define DESC_RATEVHTSS3MCS0             0x40
 107 #define DESC_RATEVHTSS3MCS1             0x41
 108 #define DESC_RATEVHTSS3MCS2             0x42
 109 #define DESC_RATEVHTSS3MCS3             0x43
 110 #define DESC_RATEVHTSS3MCS4             0x44
 111 #define DESC_RATEVHTSS3MCS5             0x45
 112 #define DESC_RATEVHTSS3MCS6             0x46
 113 #define DESC_RATEVHTSS3MCS7             0x47
 114 #define DESC_RATEVHTSS3MCS8             0x48
 115 #define DESC_RATEVHTSS3MCS9             0x49
 116 #define DESC_RATEVHTSS4MCS0             0x4A
 117 #define DESC_RATEVHTSS4MCS1             0x4B
 118 #define DESC_RATEVHTSS4MCS2             0x4C
 119 #define DESC_RATEVHTSS4MCS3             0x4D
 120 #define DESC_RATEVHTSS4MCS4             0x4E
 121 #define DESC_RATEVHTSS4MCS5             0x4F
 122 #define DESC_RATEVHTSS4MCS6             0x50
 123 #define DESC_RATEVHTSS4MCS7             0x51
 124 #define DESC_RATEVHTSS4MCS8             0x52
 125 #define DESC_RATEVHTSS4MCS9             0x53
 126
 127 #define HDATA_RATE(rate)\
 128 (rate == DESC_RATE1M)?"CCK_1M" :\
 129 (rate == DESC_RATE2M)?"CCK_2M" :\
 130 (rate == DESC_RATE5_5M)?"CCK5_5M" :\
 131 (rate == DESC_RATE11M)?"CCK_11M" :\
 132 (rate == DESC_RATE6M)?"OFDM_6M" :\
 133 (rate == DESC_RATE9M)?"OFDM_9M" :\
 134 (rate == DESC_RATE12M)?"OFDM_12M" :\
 135 (rate == DESC_RATE18M)?"OFDM_18M" :\
 136 (rate == DESC_RATE24M)?"OFDM_24M" :\
 137 (rate == DESC_RATE36M)?"OFDM_36M" :\
 138 (rate == DESC_RATE48M)?"OFDM_48M" :\
 139 (rate == DESC_RATE54M)?"OFDM_54M" :\
 140 (rate == DESC_RATEMCS0)?"MCS0" :\
 141 (rate == DESC_RATEMCS1)?"MCS1" :\
 142 (rate == DESC_RATEMCS2)?"MCS2" :\
 143 (rate == DESC_RATEMCS3)?"MCS3" :\
 144 (rate == DESC_RATEMCS4)?"MCS4" :\
 145 (rate == DESC_RATEMCS5)?"MCS5" :\
 146 (rate == DESC_RATEMCS6)?"MCS6" :\
 147 (rate == DESC_RATEMCS7)?"MCS7" :\
 148 (rate == DESC_RATEMCS8)?"MCS8" :\
 149 (rate == DESC_RATEMCS9)?"MCS9" :\
 150 (rate == DESC_RATEMCS10)?"MCS10" :\
 151 (rate == DESC_RATEMCS11)?"MCS11" :\
 152 (rate == DESC_RATEMCS12)?"MCS12" :\
 153 (rate == DESC_RATEMCS13)?"MCS13" :\
 154 (rate == DESC_RATEMCS14)?"MCS14" :\
 155 (rate == DESC_RATEMCS15)?"MCS15" :\
 156 (rate == DESC_RATEMCS16)?"MCS16" :\
 157 (rate == DESC_RATEMCS17)?"MCS17" :\
 158 (rate == DESC_RATEMCS18)?"MCS18" :\
 159 (rate == DESC_RATEMCS19)?"MCS19" :\
 160 (rate == DESC_RATEMCS20)?"MCS20" :\
 161 (rate == DESC_RATEMCS21)?"MCS21" :\
 162 (rate == DESC_RATEMCS22)?"MCS22" :\
 163 (rate == DESC_RATEMCS23)?"MCS23" :\
 164 (rate == DESC_RATEVHTSS1MCS0)?"VHTSS1MCS0" :\
 165 (rate == DESC_RATEVHTSS1MCS1)?"VHTSS1MCS1" :\
 166 (rate == DESC_RATEVHTSS1MCS2)?"VHTSS1MCS2" :\
 167 (rate == DESC_RATEVHTSS1MCS3)?"VHTSS1MCS3" :\
 168 (rate == DESC_RATEVHTSS1MCS4)?"VHTSS1MCS4" :\
 169 (rate == DESC_RATEVHTSS1MCS5)?"VHTSS1MCS5" :\
 170 (rate == DESC_RATEVHTSS1MCS6)?"VHTSS1MCS6" :\
 171 (rate == DESC_RATEVHTSS1MCS7)?"VHTSS1MCS7" :\
 172 (rate == DESC_RATEVHTSS1MCS8)?"VHTSS1MCS8" :\
 173 (rate == DESC_RATEVHTSS1MCS9)?"VHTSS1MCS9" :\
 174 (rate == DESC_RATEVHTSS2MCS0)?"VHTSS2MCS0" :\
 175 (rate == DESC_RATEVHTSS2MCS1)?"VHTSS2MCS1" :\
 176 (rate == DESC_RATEVHTSS2MCS2)?"VHTSS2MCS2" :\
 177 (rate == DESC_RATEVHTSS2MCS3)?"VHTSS2MCS3" :\
 178 (rate == DESC_RATEVHTSS2MCS4)?"VHTSS2MCS4" :\
 179 (rate == DESC_RATEVHTSS2MCS5)?"VHTSS2MCS5" :\
 180 (rate == DESC_RATEVHTSS2MCS6)?"VHTSS2MCS6" :\
 181 (rate == DESC_RATEVHTSS2MCS7)?"VHTSS2MCS7" :\
 182 (rate == DESC_RATEVHTSS2MCS8)?"VHTSS2MCS8" :\
 183 (rate == DESC_RATEVHTSS2MCS9)?"VHTSS2MCS9" :\
 184 (rate == DESC_RATEVHTSS3MCS0)?"VHTSS3MCS0" :\
 185 (rate == DESC_RATEVHTSS3MCS1)?"VHTSS3MCS1" :\
 186 (rate == DESC_RATEVHTSS3MCS2)?"VHTSS3MCS2" :\
 187 (rate == DESC_RATEVHTSS3MCS3)?"VHTSS3MCS3" :\
 188 (rate == DESC_RATEVHTSS3MCS4)?"VHTSS3MCS4" :\
 189 (rate == DESC_RATEVHTSS3MCS5)?"VHTSS3MCS5" :\
 190 (rate == DESC_RATEVHTSS3MCS6)?"VHTSS3MCS6" :\
 191 (rate == DESC_RATEVHTSS3MCS7)?"VHTSS3MCS7" :\
 192 (rate == DESC_RATEVHTSS3MCS8)?"VHTSS3MCS8" :\
 193 (rate == DESC_RATEVHTSS3MCS9)?"VHTSS3MCS9" : "UNKNOWN"
 194
 195
 196 enum{
 197         UP_LINK,
 198         DOWN_LINK,
 199 };
 200 typedef enum _RT_MEDIA_STATUS {
 201         RT_MEDIA_DISCONNECT = 0,
 202         RT_MEDIA_CONNECT       = 1
 203 } RT_MEDIA_STATUS;
 204
 205 #define MAX_DLFW_PAGE_SIZE                      4096    // @ page : 4k bytes
 206 typedef enum _FIRMWARE_SOURCE {
 207         FW_SOURCE_IMG_FILE = 0,
 208         FW_SOURCE_HEADER_FILE = 1,              //from header file
 209 } FIRMWARE_SOURCE, *PFIRMWARE_SOURCE;
 210
 211 typedef enum _CH_SW_USE_CASE {
 212         CH_SW_USE_CASE_TDLS             = 0,
 213         CH_SW_USE_CASE_MCC              = 1
 214 } CH_SW_USE_CASE;
 215
 216 //
 217 // Queue Select Value in TxDesc
 218 //
 219 #define QSLT_BK                                                 0x2//0x01
 220 #define QSLT_BE                                                 0x0
 221 #define QSLT_VI                                                 0x5//0x4
 222 #define QSLT_VO                                                 0x7//0x6
 223 #define QSLT_BEACON                                             0x10
 224 #define QSLT_HIGH                                               0x11
 225 #define QSLT_MGNT                                               0x12
 226 #define QSLT_CMD                                                0x13
 227
 228 // BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON.
 229 //#define MAX_TX_QUEUE          9
 230
 231 #define TX_SELE_HQ                      BIT(0)          // High Queue
 232 #define TX_SELE_LQ                      BIT(1)          // Low Queue
 233 #define TX_SELE_NQ                      BIT(2)          // Normal Queue
 234 #define TX_SELE_EQ                      BIT(3)          // Extern Queue
 235
 236 #define PageNum_128(_Len)               (u32)(((_Len)>>7) + ((_Len)&0x7F ? 1:0))
 237 #define PageNum_256(_Len)               (u32)(((_Len)>>8) + ((_Len)&0xFF ? 1:0))
 238 #define PageNum_512(_Len)               (u32)(((_Len)>>9) + ((_Len)&0x1FF ? 1:0))
 239 #define PageNum(_Len, _Size)            (u32)(((_Len)/(_Size)) + ((_Len)&((_Size) - 1) ? 1:0))
 240
 241 struct dbg_rx_counter
 242 {
 243         u32     rx_pkt_ok;
 244         u32     rx_pkt_crc_error;
 245         u32     rx_pkt_drop;
 246         u32     rx_ofdm_fa;
 247         u32     rx_cck_fa;
 248         u32     rx_ht_fa;
 249 };
 250 void rtw_dump_mac_rx_counters(_adapter* padapter,struct dbg_rx_counter *rx_counter);
 251 void rtw_dump_phy_rx_counters(_adapter* padapter,struct dbg_rx_counter *rx_counter);
 252 void rtw_reset_mac_rx_counters(_adapter* padapter);
 253 void rtw_reset_phy_rx_counters(_adapter* padapter);
 254
 255 #ifdef DBG_RX_COUNTER_DUMP
 256 #define DUMP_DRV_RX_COUNTER     BIT0
 257 #define DUMP_MAC_RX_COUNTER     BIT1
 258 #define DUMP_PHY_RX_COUNTER     BIT2
 259 #define DUMP_DRV_TRX_COUNTER_DATA       BIT3
 260
 261 void rtw_dump_phy_rxcnts_preprocess(_adapter* padapter,u8 rx_cnt_mode);
 262 void rtw_dump_rx_counters(_adapter* padapter);
 263 #endif
 264
 265 void dump_chip_info(HAL_VERSION ChipVersion);
 266 void rtw_hal_config_rftype(PADAPTER  padapter);
 267
 268 #define BAND_CAP_2G                     BIT0
 269 #define BAND_CAP_5G                     BIT1
 270 #define BAND_CAP_BIT_NUM        2
 271
 272 #define BW_CAP_5M               BIT0
 273 #define BW_CAP_10M              BIT1
 274 #define BW_CAP_20M              BIT2
 275 #define BW_CAP_40M              BIT3
 276 #define BW_CAP_80M              BIT4
 277 #define BW_CAP_160M             BIT5
 278 #define BW_CAP_80_80M   BIT6
 279 #define BW_CAP_BIT_NUM  7
 280
 281 #define PROTO_CAP_11B           BIT0
 282 #define PROTO_CAP_11G           BIT1
 283 #define PROTO_CAP_11N           BIT2
 284 #define PROTO_CAP_11AC          BIT3
 285 #define PROTO_CAP_BIT_NUM       4
 286
 287 #define WL_FUNC_P2P                     BIT0
 288 #define WL_FUNC_MIRACAST        BIT1
 289 #define WL_FUNC_TDLS            BIT2
 290 #define WL_FUNC_FTM                     BIT3
 291 #define WL_FUNC_BIT_NUM         4
 292
 293 int hal_spec_init(_adapter *adapter);
 294 void dump_hal_spec(void *sel, _adapter *adapter);
 295
 296 bool hal_chk_band_cap(_adapter *adapter, u8 cap);
 297 bool hal_chk_bw_cap(_adapter *adapter, u8 cap);
 298 bool hal_chk_proto_cap(_adapter *adapter, u8 cap);
 299 bool hal_is_band_support(_adapter *adapter, u8 band);
 300 bool hal_is_bw_support(_adapter *adapter, u8 bw);
 301 bool hal_is_wireless_mode_support(_adapter *adapter, u8 mode);
 302 u8 hal_largest_bw(_adapter *adapter, u8 in_bw);
 303
 304 bool hal_chk_wl_func(_adapter *adapter, u8 func);
 305
 306 u8 hal_com_config_channel_plan(
 307         IN      PADAPTER padapter,
 308         IN      char *hw_alpha2,
 309         IN      u8 hw_chplan,
 310         IN      char *sw_alpha2,
 311         IN      u8 sw_chplan,
 312         IN      u8 def_chplan,
 313         IN      BOOLEAN AutoLoadFail
 314         );
 315
 316 int hal_config_macaddr(_adapter *adapter, bool autoload_fail);
 317
 318 BOOLEAN
 319 HAL_IsLegalChannel(
 320         IN      PADAPTER        Adapter,
 321         IN      u32                     Channel
 322         );
 323
 324 u8      MRateToHwRate(u8 rate);
 325
 326 u8      HwRateToMRate(u8 rate);
 327
 328 void    HalSetBrateCfg(
 329         IN PADAPTER             Adapter,
 330         IN u8                   *mBratesOS,
 331         OUT u16                 *pBrateCfg);
 332
 333 BOOLEAN
 334 Hal_MappingOutPipe(
 335         IN      PADAPTER        pAdapter,
 336         IN      u8              NumOutPipe
 337         );
 338
 339 void hal_init_macaddr(_adapter *adapter);
 340
 341 void rtw_init_hal_com_default_value(PADAPTER Adapter);
 342
 343 void c2h_evt_clear(_adapter *adapter);
 344 s32 c2h_evt_read(_adapter *adapter, u8 *buf);
 345 s32 c2h_evt_read_88xx(_adapter *adapter, u8 *buf);
 346
 347 u8  rtw_hal_networktype_to_raid(_adapter *adapter, struct sta_info *psta);
 348 u8 rtw_get_mgntframe_raid(_adapter *adapter,unsigned char network_type);
 349 void rtw_hal_update_sta_rate_mask(PADAPTER padapter, struct sta_info *psta);
 350
 351 /* access HW only */
 352 u32 rtw_sec_read_cam(_adapter *adapter, u8 addr);
 353 void rtw_sec_write_cam(_adapter *adapter, u8 addr, u32 wdata);
 354 void rtw_sec_read_cam_ent(_adapter *adapter, u8 id, u8 *ctrl, u8 *mac, u8 *key);
 355 void rtw_sec_write_cam_ent(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key);
 356 bool rtw_sec_read_cam_is_gk(_adapter *adapter, u8 id);
 357
 358 void hw_var_port_switch(_adapter *adapter);
 359
 360 void SetHwReg(PADAPTER padapter, u8 variable, u8 *val);
 361 void GetHwReg(PADAPTER padapter, u8 variable, u8 *val);
 362 void rtw_hal_check_rxfifo_full(_adapter *adapter);
 363
 364 u8 SetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value);
 365 u8 GetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value);
 366
 367 BOOLEAN
 368 eqNByte(
 369         u8*     str1,
 370         u8*     str2,
 371         u32     num
 372         );
 373
 374 u32
 375 MapCharToHexDigit(
 376         IN      char    chTmp
 377 );
 378
 379 BOOLEAN
 380 GetHexValueFromString(
 381         IN              char*                   szStr,
 382         IN OUT  u32*                    pu4bVal,
 383         IN OUT  u32*                    pu4bMove
 384         );
 385
 386 BOOLEAN
 387 GetFractionValueFromString(
 388         IN              char*           szStr,
 389         IN OUT  u8*                     pInteger,
 390         IN OUT  u8*                     pFraction,
 391         IN OUT  u32*            pu4bMove
 392         );
 393
 394 BOOLEAN
 395 IsCommentString(
 396         IN              char*           szStr
 397         );
 398
 399 BOOLEAN
 400 ParseQualifiedString(
 401     IN  char* In,
 402     IN OUT  u32* Start,
 403     OUT char* Out,
 404     IN  char  LeftQualifier,
 405     IN  char  RightQualifier
 406     );
 407
 408 BOOLEAN
 409 GetU1ByteIntegerFromStringInDecimal(
 410         IN              char* Str,
 411         IN OUT  u8* pInt
 412         );
 413
 414 BOOLEAN
 415 isAllSpaceOrTab(
 416         u8*     data,
 417         u8      size
 418         );
 419
 420 void linked_info_dump(_adapter *padapter,u8 benable);
 421 #ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
 422 void rtw_get_raw_rssi_info(void *sel, _adapter *padapter);
 423 void rtw_store_phy_info(_adapter *padapter, union recv_frame *prframe);
 424 void rtw_dump_raw_rssi_info(_adapter *padapter, void *sel);
 425 #endif
 426
 427 #define         HWSET_MAX_SIZE                  512
 428
 429 int check_phy_efuse_tx_power_info_valid(PADAPTER padapter);
 430 int hal_efuse_macaddr_offset(_adapter *adapter);
 431 int Hal_GetPhyEfuseMACAddr(PADAPTER padapter, u8 *mac_addr);
 432
 433 #ifdef CONFIG_RF_GAIN_OFFSET
 434 void rtw_bb_rf_gain_offset(_adapter *padapter);
 435 #endif //CONFIG_RF_GAIN_OFFSET
 436
 437 void dm_DynamicUsbTxAgg(_adapter *padapter, u8 from_timer);
 438 u8 rtw_hal_busagg_qsel_check(_adapter *padapter,u8 pre_qsel,u8 next_qsel);
 439 void GetHalODMVar(
 440         PADAPTER                                Adapter,
 441         HAL_ODM_VARIABLE                eVariable,
 442         PVOID                                   pValue1,
 443         PVOID                                   pValue2);
 444 void SetHalODMVar(
 445         PADAPTER                                Adapter,
 446         HAL_ODM_VARIABLE                eVariable,
 447         PVOID                                   pValue1,
 448         BOOLEAN                                 bSet);
 449
 450 #ifdef CONFIG_BACKGROUND_NOISE_MONITOR
 451 struct noise_info
 452 {
 453         u8              bPauseDIG;
 454         u8              IGIValue;
 455         u32     max_time;//ms
 456         u8              chan;
 457 };
 458 #endif
 459
 460 void rtw_get_noise(_adapter* padapter);
 461 u8 rtw_get_current_tx_rate(_adapter *padapter, u8 macid);
 462 void rtw_hal_set_fw_rsvd_page(_adapter* adapter, bool finished);
 463
 464 #ifdef CONFIG_TDLS
 465 #ifdef CONFIG_TDLS_CH_SW
 466 s32 rtw_hal_ch_sw_oper_offload(_adapter *padapter, u8 channel, u8 channel_offset, u16 bwmode);
 467 #endif
 468 #endif
 469
 470 #ifdef CONFIG_GPIO_API
 471 u8 rtw_hal_get_gpio(_adapter* adapter, u8 gpio_num);
 472 int rtw_hal_set_gpio_output_value(_adapter* adapter, u8 gpio_num, bool isHigh);
 473 int rtw_hal_config_gpio(_adapter* adapter, u8 gpio_num, bool isOutput);
 474 int rtw_hal_register_gpio_interrupt(_adapter* adapter, int gpio_num, void(*callback)(u8 level));
 475 int rtw_hal_disable_gpio_interrupt(_adapter* adapter, int gpio_num);
 476 #endif
 477
 478 s8 rtw_hal_ch_sw_iqk_info_search(_adapter *padapter, u8 central_chnl, u8 bw_mode);
 479 void rtw_hal_ch_sw_iqk_info_backup(_adapter *adapter);
 480 void rtw_hal_ch_sw_iqk_info_restore(_adapter *padapter, u8 ch_sw_use_case);
 481
 482
 483 typedef enum _HAL_PHYDM_OPS {
 484         HAL_PHYDM_DIS_ALL_FUNC,
 485         HAL_PHYDM_FUNC_SET,
 486         HAL_PHYDM_FUNC_CLR,
 487         HAL_PHYDM_ABILITY_BK,
 488         HAL_PHYDM_ABILITY_RESTORE,
 489         HAL_PHYDM_ABILITY_SET,
 490         HAL_PHYDM_ABILITY_GET,
 491 } HAL_PHYDM_OPS;
 492
 493
 494 #define DYNAMIC_FUNC_DISABLE            (0x0)
 495 u32 rtw_phydm_ability_ops(_adapter *adapter, HAL_PHYDM_OPS ops, u32 ability);
 496
 497 #define rtw_phydm_func_disable_all(adapter)     \
 498         rtw_phydm_ability_ops(adapter, HAL_PHYDM_DIS_ALL_FUNC, 0)
 499
 500 #define rtw_phydm_func_for_offchannel(adapter) \
 501         do { \
 502                 rtw_phydm_ability_ops(adapter, HAL_PHYDM_DIS_ALL_FUNC, 0); \
 503                 if (rtw_odm_adaptivity_needed(adapter)) \
 504                         rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_SET, ODM_BB_ADAPTIVITY); \
 505         } while (0)
 506
 507 #define rtw_phydm_func_set(adapter, ability)    \
 508         rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_SET, ability)
 509
 510 #define rtw_phydm_func_clr(adapter, ability)    \
 511         rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_CLR, ability)
 512
 513 #define rtw_phydm_ability_backup(adapter)       \
 514         rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_BK, 0)
 515
 516 #define rtw_phydm_ability_restore(adapter)      \
 517         rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_RESTORE, 0)
 518
 519 #define rtw_phydm_ability_set(adapter, ability) \
 520         rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_SET, ability)
 521
 522 static inline u32 rtw_phydm_ability_get(_adapter *adapter)
 523 {
 524         return rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_GET, 0);
 525 }
 526
 527
 528 #ifdef CONFIG_FW_C2H_DEBUG
 529 void Debug_FwC2H(PADAPTER padapter, u8 *pdata, u8 len);
 530 #endif
 531 /*CONFIG_FW_C2H_DEBUG*/
 532
 533 void update_IOT_info(_adapter *padapter);
 534
 535 #ifdef CONFIG_AUTO_CHNL_SEL_NHM
 536 void rtw_acs_start(_adapter *padapter, bool bStart);
 537 #endif
 538
 539 void hal_set_crystal_cap(_adapter *adapter, u8 crystal_cap);
 540
 541 #endif //__HAL_COMMON_H__