rtl8723bu/include/hal_data.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20 #ifndef __HAL_DATA_H__
  21 #define __HAL_DATA_H__
  22
  23 #if 1//def  CONFIG_SINGLE_IMG
  24
  25 #include "../hal/phydm/phydm_precomp.h"
  26 #ifdef CONFIG_BT_COEXIST
  27 #include <hal_btcoex.h>
  28 #endif
  29
  30 #ifdef CONFIG_SDIO_HCI
  31 #include <hal_sdio.h>
  32 #endif
  33 #ifdef CONFIG_GSPI_HCI
  34 #include <hal_gspi.h>
  35 #endif
  36 //
  37 // <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06.
  38 //
  39 typedef enum _RT_MULTI_FUNC{
  40         RT_MULTI_FUNC_NONE      = 0x00,
  41         RT_MULTI_FUNC_WIFI      = 0x01,
  42         RT_MULTI_FUNC_BT                = 0x02,
  43         RT_MULTI_FUNC_GPS       = 0x04,
  44 }RT_MULTI_FUNC,*PRT_MULTI_FUNC;
  45 //
  46 // <Roger_Notes> For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08.
  47 //
  48 typedef enum _RT_POLARITY_CTL {
  49         RT_POLARITY_LOW_ACT     = 0,
  50         RT_POLARITY_HIGH_ACT    = 1,
  51 } RT_POLARITY_CTL, *PRT_POLARITY_CTL;
  52
  53 // For RTL8723 regulator mode. by tynli. 2011.01.14.
  54 typedef enum _RT_REGULATOR_MODE {
  55         RT_SWITCHING_REGULATOR  = 0,
  56         RT_LDO_REGULATOR                        = 1,
  57 } RT_REGULATOR_MODE, *PRT_REGULATOR_MODE;
  58
  59 //
  60 // Interface type.
  61 //
  62 typedef enum _INTERFACE_SELECT_PCIE{
  63         INTF_SEL0_SOLO_MINICARD                 = 0,            // WiFi solo-mCard
  64         INTF_SEL1_BT_COMBO_MINICARD             = 1,            // WiFi+BT combo-mCard
  65         INTF_SEL2_PCIe                                          = 2,            // PCIe Card
  66 } INTERFACE_SELECT_PCIE, *PINTERFACE_SELECT_PCIE;
  67
  68
  69 typedef enum _INTERFACE_SELECT_USB{
  70         INTF_SEL0_USB                           = 0,            // USB
  71         INTF_SEL1_USB_High_Power        = 1,            // USB with high power PA
  72         INTF_SEL2_MINICARD                      = 2,            // Minicard
  73         INTF_SEL3_USB_Solo              = 3,            // USB solo-Slim module
  74         INTF_SEL4_USB_Combo             = 4,            // USB Combo-Slim module
  75         INTF_SEL5_USB_Combo_MF  = 5,            // USB WiFi+BT Multi-Function Combo, i.e., Proprietary layout(AS-VAU) which is the same as SDIO card
  76 } INTERFACE_SELECT_USB, *PINTERFACE_SELECT_USB;
  77
  78 typedef enum _RT_AMPDU_BRUST_MODE{
  79         RT_AMPDU_BRUST_NONE             = 0,
  80         RT_AMPDU_BRUST_92D              = 1,
  81         RT_AMPDU_BRUST_88E              = 2,
  82         RT_AMPDU_BRUST_8812_4   = 3,
  83         RT_AMPDU_BRUST_8812_8   = 4,
  84         RT_AMPDU_BRUST_8812_12  = 5,
  85         RT_AMPDU_BRUST_8812_15  = 6,
  86         RT_AMPDU_BRUST_8723B            = 7,
  87 }RT_AMPDU_BRUST,*PRT_AMPDU_BRUST_MODE;
  88
  89 /*
  90 #define CHANNEL_MAX_NUMBER                      14+24+21        // 14 is the max channel number
  91 */
  92 #define CHANNEL_GROUP_MAX               (3 + 9) /* ch1~3, ch4~9, ch10~14 total three groups */
  93 #define MAX_PG_GROUP                    13
  94
  95 // Tx Power Limit Table Size
  96 #define MAX_REGULATION_NUM                                              4
  97 #define MAX_RF_PATH_NUM_IN_POWER_LIMIT_TABLE    4
  98 #define MAX_2_4G_BANDWIDTH_NUM                                  2
  99 #define MAX_RATE_SECTION_NUM                                            10
 100 #define MAX_5G_BANDWIDTH_NUM                                            4
 101
 102 #define MAX_BASE_NUM_IN_PHY_REG_PG_2_4G                 10 //  CCK:1,OFDM:1, HT:4, VHT:4
 103 #define MAX_BASE_NUM_IN_PHY_REG_PG_5G                   9 // OFDM:1, HT:4, VHT:4
 104
 105
 106 //###### duplicate code,will move to ODM #########
 107 //#define IQK_MAC_REG_NUM               4
 108 //#define IQK_ADDA_REG_NUM              16
 109
 110 //#define IQK_BB_REG_NUM                        10
 111 #define IQK_BB_REG_NUM_92C      9
 112 #define IQK_BB_REG_NUM_92D      10
 113 #define IQK_BB_REG_NUM_test     6
 114
 115 #define IQK_Matrix_Settings_NUM_92D     1+24+21
 116
 117 //#define HP_THERMAL_NUM                8
 118 //###### duplicate code,will move to ODM #########
 119
 120 #ifdef CONFIG_USB_RX_AGGREGATION
 121 typedef enum _USB_RX_AGG_MODE{
 122         USB_RX_AGG_DISABLE,
 123         USB_RX_AGG_DMA,
 124         USB_RX_AGG_USB,
 125         USB_RX_AGG_MIX
 126 }USB_RX_AGG_MODE;
 127
 128 //#define MAX_RX_DMA_BUFFER_SIZE        10240           // 10K for 8192C RX DMA buffer
 129
 130 #endif
 131
 132 /* For store initial value of BB register */
 133 typedef struct _BB_INIT_REGISTER {
 134         u16     offset;
 135         u32     value;
 136
 137 } BB_INIT_REGISTER, *PBB_INIT_REGISTER;
 138
 139 #define PAGE_SIZE_128   128
 140 #define PAGE_SIZE_256   256
 141 #define PAGE_SIZE_512   512
 142
 143 #define HCI_SUS_ENTER           0
 144 #define HCI_SUS_LEAVING         1
 145 #define HCI_SUS_LEAVE           2
 146 #define HCI_SUS_ENTERING        3
 147 #define HCI_SUS_ERR                     4
 148
 149 #ifdef CONFIG_AUTO_CHNL_SEL_NHM
 150 typedef enum _ACS_OP {
 151         ACS_INIT,               /*ACS - Variable init*/
 152         ACS_RESET,              /*ACS - NHM Counter reset*/
 153         ACS_SELECT,             /*ACS - NHM Counter Statistics */
 154 } ACS_OP;
 155
 156 typedef enum _ACS_STATE {
 157         ACS_DISABLE,
 158         ACS_ENABLE,
 159 } ACS_STATE;
 160
 161 struct auto_chan_sel {
 162         ATOMIC_T state;
 163         u8      ch; /* previous channel*/
 164 };
 165 #endif /*CONFIG_AUTO_CHNL_SEL_NHM*/
 166
 167 #define EFUSE_FILE_UNUSED 0
 168 #define EFUSE_FILE_FAILED 1
 169 #define EFUSE_FILE_LOADED 2
 170
 171 #define MACADDR_FILE_UNUSED 0
 172 #define MACADDR_FILE_FAILED 1
 173 #define MACADDR_FILE_LOADED 2
 174
 175 #define KFREE_FLAG_ON                           BIT0
 176 #define KFREE_FLAG_THERMAL_K_ON         BIT1
 177
 178 #define MAX_IQK_INFO_BACKUP_CHNL_NUM    5
 179 #define MAX_IQK_INFO_BACKUP_REG_NUM             10
 180
 181 struct kfree_data_t {
 182                 u8 flag;
 183                 s8 bb_gain[BB_GAIN_NUM][RF_PATH_MAX];
 184
 185                 s8 thermal;
 186 };
 187
 188 bool kfree_data_is_bb_gain_empty(struct kfree_data_t *data);
 189
 190 struct hal_spec_t {
 191         u8 macid_num;
 192
 193         u8 sec_cam_ent_num;
 194         u8 sec_cap;
 195
 196         u8 nss_num;
 197         u8 band_cap;    /* value of BAND_CAP_XXX */
 198         u8 bw_cap;              /* value of BW_CAP_XXX */
 199         u8 proto_cap;   /* value of PROTO_CAP_XXX */
 200
 201         u8 wl_func;             /* value of WL_FUNC_XXX */
 202 };
 203
 204 struct hal_iqk_reg_backup {
 205         u8 central_chnl;
 206         u8 bw_mode;
 207         u32 reg_backup[MAX_RF_PATH][MAX_IQK_INFO_BACKUP_REG_NUM];
 208 };
 209
 210 typedef struct hal_com_data
 211 {
 212         HAL_VERSION                     VersionID;
 213         RT_MULTI_FUNC           MultiFunc; // For multi-function consideration.
 214         RT_POLARITY_CTL         PolarityCtl; // For Wifi PDn Polarity control.
 215         RT_REGULATOR_MODE       RegulatorMode; // switching regulator or LDO
 216         u8      hw_init_completed;
 217         /****** FW related ******/
 218         u16     FirmwareVersion;
 219         u16     FirmwareVersionRev;
 220         u16     FirmwareSubVersion;
 221         u16     FirmwareSignature;
 222         u8      RegFWOffload;
 223         u8      fw_ractrl;
 224         u8      FwRsvdPageStartOffset; /* 2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ.*/
 225         u8      LastHMEBoxNum;  /* H2C - for host message to fw */
 226
 227         /****** current WIFI_PHY values ******/
 228         WIRELESS_MODE   CurrentWirelessMode;
 229         CHANNEL_WIDTH   CurrentChannelBW;
 230         BAND_TYPE               CurrentBandType;        /* 0:2.4G, 1:5G */
 231         BAND_TYPE               BandSet;
 232         u8                              CurrentChannel;
 233         u8                              CurrentCenterFrequencyIndex1;
 234         u8                              nCur40MhzPrimeSC;       /* Control channel sub-carrier */
 235         u8                              nCur80MhzPrimeSC;   /* used for primary 40MHz of 80MHz mode */
 236         BOOLEAN                 bSwChnlAndSetBWInProgress;
 237         u8                              bDisableSWChannelPlan; /* flag of disable software change channel plan   */
 238         u16                             BasicRateSet;
 239         u32                             ReceiveConfig;
 240         BOOLEAN                 bSwChnl;
 241         BOOLEAN                 bSetChnlBW;
 242         BOOLEAN                 bSWToBW40M;
 243         BOOLEAN                 bSWToBW80M;
 244         BOOLEAN                 bChnlBWInitialized;
 245         u32                             BackUp_BB_REG_4_2nd_CCA[3];
 246 #ifdef CONFIG_AUTO_CHNL_SEL_NHM
 247         struct auto_chan_sel acs;
 248 #endif
 249         /****** rf_ctrl *****/
 250         u8      rf_chip;
 251         u8      rf_type;
 252         u8      PackageType;
 253         u8      NumTotalRFPath;
 254
 255         /****** Debug ******/
 256         u16     ForcedDataRate; /* Force Data Rate. 0: Auto, 0x02: 1M ~ 0x6C: 54M. */
 257         u8      u1ForcedIgiLb;  /* forced IGI lower bound */
 258         u8      bDumpRxPkt;
 259         u8      bDumpTxPkt;
 260         u8      bDisableTXPowerTraining;
 261
 262
 263         /****** EEPROM setting.******/
 264         u8      bautoload_fail_flag;
 265         u8      efuse_file_status;
 266         u8      macaddr_file_status;
 267         u8      EepromOrEfuse;
 268         u8      efuse_eeprom_data[EEPROM_MAX_SIZE]; /*92C:256bytes, 88E:512bytes, we use union set (512bytes)*/
 269         u8      InterfaceSel; /* board type kept in eFuse */
 270         u16     CustomerID;
 271
 272         u16     EEPROMVID;
 273         u16     EEPROMSVID;
 274 #ifdef CONFIG_USB_HCI
 275         u16     EEPROMPID;
 276         u16     EEPROMSDID;
 277 #endif
 278 #ifdef CONFIG_PCI_HCI
 279         u16     EEPROMDID;
 280         u16     EEPROMSMID;
 281 #endif
 282
 283         u8      EEPROMCustomerID;
 284         u8      EEPROMSubCustomerID;
 285         u8      EEPROMVersion;
 286         u8      EEPROMRegulatory;
 287         u8      EEPROMThermalMeter;
 288         u8      EEPROMBluetoothCoexist;
 289         u8      EEPROMBluetoothType;
 290         u8      EEPROMBluetoothAntNum;
 291         u8      EEPROMBluetoothAntIsolation;
 292         u8      EEPROMBluetoothRadioShared;
 293         u8      bTXPowerDataReadFromEEPORM;
 294         u8      EEPROMMACAddr[ETH_ALEN];
 295
 296 #ifdef CONFIG_RF_GAIN_OFFSET
 297         u8      EEPROMRFGainOffset;
 298         u8      EEPROMRFGainVal;
 299         struct kfree_data_t kfree_data;
 300 #endif /*CONFIG_RF_GAIN_OFFSET*/
 301
 302 #if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B)
 303         u8      adjuseVoltageVal;
 304 #endif
 305         u8      EfuseUsedPercentage;
 306         u16     EfuseUsedBytes;
 307         /*u8            EfuseMap[2][HWSET_MAX_SIZE_JAGUAR];*/
 308         EFUSE_HAL       EfuseHal;
 309
 310         /*---------------------------------------------------------------------------------*/
 311         //3 [2.4G]
 312         u8      Index24G_CCK_Base[MAX_RF_PATH][CENTER_CH_2G_NUM];
 313         u8      Index24G_BW40_Base[MAX_RF_PATH][CENTER_CH_2G_NUM];
 314         //If only one tx, only BW20 and OFDM are used.
 315         s8      CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 316         s8      OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 317         s8      BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 318         s8      BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 319         //3 [5G]
 320         u8      Index5G_BW40_Base[MAX_RF_PATH][CENTER_CH_5G_ALL_NUM];
 321         u8      Index5G_BW80_Base[MAX_RF_PATH][CENTER_CH_5G_80M_NUM];
 322         s8      OFDM_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 323         s8      BW20_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 324         s8      BW40_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 325         s8      BW80_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 326
 327         u8      Regulation2_4G;
 328         u8      Regulation5G;
 329
 330         u8      TxPwrInPercentage;
 331
 332         /********************************
 333         *       TX power by rate table at most 4RF path.
 334         *       The register is
 335         *
 336         *       VHT TX power by rate off setArray =
 337         *       Band:-2G&5G = 0 / 1
 338         *       RF: at most 4*4 = ABCD=0/1/2/3
 339         *       CCK=0 OFDM=1/2 HT-MCS 0-15=3/4/56 VHT=7/8/9/10/11
 340         **********************************/
 341         u8      TxPwrByRateTable;
 342         u8      TxPwrByRateBand;
 343         s8      TxPwrByRateOffset[TX_PWR_BY_RATE_NUM_BAND]
 344                                                  [TX_PWR_BY_RATE_NUM_RF]
 345                                                  [TX_PWR_BY_RATE_NUM_RF]
 346                                                  [TX_PWR_BY_RATE_NUM_RATE];
 347         //---------------------------------------------------------------------------------//
 348
 349         /*
 350         //2 Power Limit Table
 351         u8      TxPwrLevelCck[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];
 352         u8      TxPwrLevelHT40_1S[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];     // For HT 40MHZ pwr
 353         u8      TxPwrLevelHT40_2S[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];     // For HT 40MHZ pwr
 354         s8      TxPwrHt20Diff[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff
 355         u8      TxPwrLegacyHtDiff[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff
 356         */
 357
 358         u8 tx_pwr_lmt_5g_20_40_ref;
 359
 360         // Power Limit Table for 2.4G
 361         s8      TxPwrLimit_2_4G[MAX_REGULATION_NUM]
 362                                                 [MAX_2_4G_BANDWIDTH_NUM]
 363                                                 [MAX_RATE_SECTION_NUM]
 364                                                 [CENTER_CH_2G_NUM]
 365                                                 [MAX_RF_PATH];
 366
 367         // Power Limit Table for 5G
 368         s8      TxPwrLimit_5G[MAX_REGULATION_NUM]
 369                                                 [MAX_5G_BANDWIDTH_NUM]
 370                                                 [MAX_RATE_SECTION_NUM]
 371                                                 [CENTER_CH_5G_ALL_NUM]
 372                                                 [MAX_RF_PATH];
 373
 374
 375         // Store the original power by rate value of the base of each rate section of rf path A & B
 376         u8      TxPwrByRateBase2_4G[TX_PWR_BY_RATE_NUM_RF]
 377                                                 [TX_PWR_BY_RATE_NUM_RF]
 378                                                 [MAX_BASE_NUM_IN_PHY_REG_PG_2_4G];
 379         u8      TxPwrByRateBase5G[TX_PWR_BY_RATE_NUM_RF]
 380                                                 [TX_PWR_BY_RATE_NUM_RF]
 381                                                 [MAX_BASE_NUM_IN_PHY_REG_PG_5G];
 382
 383         u8      txpwr_by_rate_loaded:1;
 384         u8      txpwr_by_rate_from_file:1;
 385         u8      txpwr_limit_loaded:1;
 386         u8      txpwr_limit_from_file:1;
 387
 388         // For power group
 389         /*
 390         u8      PwrGroupHT20[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];
 391         u8      PwrGroupHT40[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];
 392         */
 393         u8      PGMaxGroup;
 394
 395         // The current Tx Power Level
 396         u8      CurrentCckTxPwrIdx;
 397         u8      CurrentOfdm24GTxPwrIdx;
 398         u8      CurrentBW2024GTxPwrIdx;
 399         u8      CurrentBW4024GTxPwrIdx;
 400
 401         // Read/write are allow for following hardware information variables
 402         u8      pwrGroupCnt;
 403         u32     MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16];
 404         u32     CCKTxPowerLevelOriginalOffset;
 405
 406         u8      CrystalCap;
 407
 408         u8      PAType_2G;
 409         u8      PAType_5G;
 410         u8      LNAType_2G;
 411         u8      LNAType_5G;
 412         u8      ExternalPA_2G;
 413         u8      ExternalLNA_2G;
 414         u8      ExternalPA_5G;
 415         u8      ExternalLNA_5G;
 416         u16     TypeGLNA;
 417         u16     TypeGPA;
 418         u16     TypeALNA;
 419         u16     TypeAPA;
 420         u16     RFEType;
 421
 422         u8      bLedOpenDrain; /* Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. */
 423         u32     AcParam_BE; /* Original parameter for BE, use for EDCA turbo.   */
 424
 425         BB_REGISTER_DEFINITION_T        PHYRegDef[MAX_RF_PATH]; //Radio A/B/C/D
 426
 427         u32     RfRegChnlVal[MAX_RF_PATH];
 428
 429         //RDG enable
 430         BOOLEAN  bRDGEnable;
 431
 432         u8      RegTxPause;
 433         // Beacon function related global variable.
 434         u8      RegBcnCtrlVal;
 435         u8      RegFwHwTxQCtrl;
 436         u8      RegReg542;
 437         u8      RegCR_1;
 438         u8      Reg837;
 439         u16     RegRRSR;
 440
 441         /****** antenna diversity ******/
 442         u8      AntDivCfg;
 443         u8      AntDetection;
 444         u8      TRxAntDivType;
 445         u8      ant_path; //for 8723B s0/s1 selection
 446         u32     AntennaTxPath;                                  /* Antenna path Tx */
 447         u32     AntennaRxPath;                                  /* Antenna path Rx */
 448         u8 sw_antdiv_bl_state;
 449
 450         /******** PHY DM & DM Section **********/
 451         u8                      DM_Type;
 452         _lock           IQKSpinLock;
 453         u8                      INIDATA_RATE[MACID_NUM_SW_LIMIT];
 454         /* Upper and Lower Signal threshold for Rate Adaptive*/
 455         int                     EntryMinUndecoratedSmoothedPWDB;
 456         int                     EntryMaxUndecoratedSmoothedPWDB;
 457         int                     MinUndecoratedPWDBForDM;
 458         DM_ODM_T        odmpriv;
 459         u8                      bIQKInitialized;
 460         u8                      bNeedIQK;
 461         /******** PHY DM & DM Section **********/
 462
 463
 464
 465         // 2010/08/09 MH Add CU power down mode.
 466         BOOLEAN         pwrdown;
 467
 468         // Add for dual MAC  0--Mac0 1--Mac1
 469         u32     interfaceIndex;
 470
 471 #ifdef CONFIG_P2P
 472         u8      p2p_ps_offload;
 473 #endif
 474         /* Auto FSM to Turn On, include clock, isolation, power control for MAC only */
 475         u8      bMacPwrCtrlOn;
 476         u8 hci_sus_state;
 477
 478         u8      RegIQKFWOffload;
 479         struct submit_ctx       iqk_sctx;
 480
 481         RT_AMPDU_BRUST          AMPDUBurstMode; //92C maybe not use, but for compile successfully
 482
 483         u8      OutEpQueueSel;
 484         u8      OutEpNumber;
 485
 486 #if defined (CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
 487         //
 488         // For SDIO Interface HAL related
 489         //
 490
 491         //
 492         // SDIO ISR Related
 493         //
 494 //      u32                     IntrMask[1];
 495 //      u32                     IntrMaskToSet[1];
 496 //      LOG_INTERRUPT           InterruptLog;
 497         u32                     sdio_himr;
 498         u32                     sdio_hisr;
 499
 500         //
 501         // SDIO Tx FIFO related.
 502         //
 503         // HIQ, MID, LOW, PUB free pages; padapter->xmitpriv.free_txpg
 504         u8                      SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE];
 505         _lock           SdioTxFIFOFreePageLock;
 506         u8                      SdioTxOQTMaxFreeSpace;
 507         u8                      SdioTxOQTFreeSpace;
 508
 509         //
 510         // SDIO Rx FIFO related.
 511         //
 512         u8                      SdioRxFIFOCnt;
 513         u16                     SdioRxFIFOSize;
 514
 515         u32                     sdio_tx_max_len[SDIO_MAX_TX_QUEUE];// H, N, L, used for sdio tx aggregation max length per queue
 516 #endif //CONFIG_SDIO_HCI
 517
 518 #ifdef CONFIG_USB_HCI
 519
 520         // 2010/12/10 MH Add for USB aggreation mode dynamic shceme.
 521         BOOLEAN         UsbRxHighSpeedMode;
 522         BOOLEAN         UsbTxVeryHighSpeedMode;
 523         u32                     UsbBulkOutSize;
 524         BOOLEAN         bSupportUSB3;
 525
 526         // Interrupt relatd register information.
 527         u32                     IntArray[3];//HISR0,HISR1,HSISR
 528         u32                     IntrMask[3];
 529         u8                      C2hArray[16];
 530         #ifdef CONFIG_USB_TX_AGGREGATION
 531         u8                      UsbTxAggMode;
 532         u8                      UsbTxAggDescNum;
 533         #endif // CONFIG_USB_TX_AGGREGATION
 534
 535         #ifdef CONFIG_USB_RX_AGGREGATION
 536         u16                     HwRxPageSize;                           // Hardware setting
 537         u32                     MaxUsbRxAggBlock;
 538
 539         USB_RX_AGG_MODE UsbRxAggMode;
 540         u8                      UsbRxAggBlockCount;             /* FOR USB Mode, USB Block count. Block size is 512-byte in hight speed and 64-byte in full speed */
 541         u8                      UsbRxAggBlockTimeout;
 542         u8                      UsbRxAggPageCount;                      /* FOR DMA Mode, 8192C DMA page count*/
 543         u8                      UsbRxAggPageTimeout;
 544
 545         u8                      RegAcUsbDmaSize;
 546         u8                      RegAcUsbDmaTime;
 547         #endif//CONFIG_USB_RX_AGGREGATION
 548 #endif //CONFIG_USB_HCI
 549
 550
 551 #ifdef CONFIG_PCI_HCI
 552         //
 553         // EEPROM setting.
 554         //
 555         u32                     TransmitConfig;
 556         u32                     IntrMaskToSet[2];
 557         u32                     IntArray[2];
 558         u32                     IntrMask[2];
 559         u32                     SysIntArray[1];
 560         u32                     SysIntrMask[1];
 561         u32                     IntrMaskReg[2];
 562         u32                     IntrMaskDefault[2];
 563
 564         BOOLEAN         bL1OffSupport;
 565         BOOLEAN         bSupportBackDoor;
 566
 567         u8                      bDefaultAntenna;
 568
 569         u8                      bInterruptMigration;
 570         u8                      bDisableTxInt;
 571
 572         u16                     RxTag;
 573 #endif //CONFIG_PCI_HCI
 574
 575
 576 #ifdef DBG_CONFIG_ERROR_DETECT
 577         struct sreset_priv srestpriv;
 578 #endif //#ifdef DBG_CONFIG_ERROR_DETECT
 579
 580 #ifdef CONFIG_BT_COEXIST
 581         // For bluetooth co-existance
 582         BT_COEXIST              bt_coexist;
 583 #endif // CONFIG_BT_COEXIST
 584
 585 #if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) || defined(CONFIG_RTL8188F)
 586         #ifndef CONFIG_PCI_HCI  // mutual exclusive with PCI -- so they're SDIO and GSPI
 587         // Interrupt relatd register information.
 588         u32                     SysIntrStatus;
 589         u32                     SysIntrMask;
 590         #endif
 591 #endif /*endif CONFIG_RTL8723B  */
 592
 593 #ifdef CONFIG_BACKGROUND_NOISE_MONITOR
 594         s16 noise[ODM_MAX_CHANNEL_NUM];
 595 #endif
 596
 597         struct hal_spec_t hal_spec;
 598
 599         u8      RfKFreeEnable;
 600         u8      RfKFree_ch_group;
 601         BOOLEAN                         bCCKinCH14;
 602         BB_INIT_REGISTER        RegForRecover[5];
 603
 604 #if defined(CONFIG_PCI_HCI) && defined(RTL8814AE_SW_BCN)
 605         BOOLEAN bCorrectBCN;
 606 #endif
 607         u32 RxGainOffset[4]; /*{2G, 5G_Low, 5G_Middle, G_High}*/
 608         u8 BackUp_IG_REG_4_Chnl_Section[4]; /*{A,B,C,D}*/
 609
 610         struct hal_iqk_reg_backup iqk_reg_backup[MAX_IQK_INFO_BACKUP_CHNL_NUM];
 611 } HAL_DATA_COMMON, *PHAL_DATA_COMMON;
 612
 613
 614
 615 typedef struct hal_com_data HAL_DATA_TYPE, *PHAL_DATA_TYPE;
 616 #define GET_HAL_DATA(__pAdapter)                        ((HAL_DATA_TYPE *)((__pAdapter)->HalData))
 617 #define GET_HAL_SPEC(__pAdapter)                        (&(GET_HAL_DATA((__pAdapter))->hal_spec))
 618
 619 #define GET_HAL_RFPATH_NUM(__pAdapter)          (((HAL_DATA_TYPE *)((__pAdapter)->HalData))->NumTotalRFPath )
 620 #define RT_GetInterfaceSelection(_Adapter)              (GET_HAL_DATA(_Adapter)->InterfaceSel)
 621 #define GET_RF_TYPE(__pAdapter)                         (GET_HAL_DATA(__pAdapter)->rf_type)
 622 #define GET_KFREE_DATA(_adapter) (&(GET_HAL_DATA((_adapter))->kfree_data))
 623
 624 #define SUPPORT_HW_RADIO_DETECT(Adapter)        (       RT_GetInterfaceSelection(Adapter) == INTF_SEL2_MINICARD ||\
 625                                                                                                 RT_GetInterfaceSelection(Adapter) == INTF_SEL3_USB_Solo ||\
 626                                                                                                 RT_GetInterfaceSelection(Adapter) == INTF_SEL4_USB_Combo)
 627
 628 #define get_hal_mac_addr(adapter)                               (GET_HAL_DATA(adapter)->EEPROMMACAddr)
 629 #define is_boot_from_eeprom(adapter)                    (GET_HAL_DATA(adapter)->EepromOrEfuse)
 630 #define rtw_get_hw_init_completed(adapter)              (GET_HAL_DATA(adapter)->hw_init_completed)
 631 #define rtw_is_hw_init_completed(adapter)               (GET_HAL_DATA(adapter)->hw_init_completed == _TRUE)
 632 #endif
 633
 634 #ifdef CONFIG_AUTO_CHNL_SEL_NHM
 635 #define GET_ACS_STATE(padapter)                                 (ATOMIC_READ(&GET_HAL_DATA(padapter)->acs.state))
 636 #define SET_ACS_STATE(padapter, set_state)                      (ATOMIC_SET(&GET_HAL_DATA(padapter)->acs.state, set_state))
 637 #define rtw_get_acs_channel(padapter)                           (GET_HAL_DATA(padapter)->acs.ch)
 638 #define rtw_set_acs_channel(padapter, survey_ch)        (GET_HAL_DATA(padapter)->acs.ch = survey_ch)
 639 #endif /*CONFIG_AUTO_CHNL_SEL_NHM*/
 640
 641 #endif //__HAL_DATA_H__