2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 * Declare public libdrm_amdgpu API
29 * This file define API exposed by libdrm_amdgpu library.
30 * User wanted to use libdrm_amdgpu functionality must include
44 struct drm_amdgpu_info_hw_ip;
46 /*--------------------------------------------------------------------------*/
47 /* --------------------------- Defines ------------------------------------ */
48 /*--------------------------------------------------------------------------*/
51 * Define max. number of Command Buffers (IB) which could be sent to the single
52 * hardware IP to accommodate CE/DE requirements
54 * \sa amdgpu_cs_ib_info
56 #define AMDGPU_CS_MAX_IBS_PER_SUBMIT 4
59 * Special timeout value meaning that the timeout is infinite.
61 #define AMDGPU_TIMEOUT_INFINITE 0xffffffffffffffffull
64 * Used in amdgpu_cs_query_fence_status(), meaning that the given timeout
67 #define AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE (1 << 0)
69 /*--------------------------------------------------------------------------*/
70 /* ----------------------------- Enums ------------------------------------ */
71 /*--------------------------------------------------------------------------*/
74 * Enum describing possible handle types
76 * \sa amdgpu_bo_import, amdgpu_bo_export
79 enum amdgpu_bo_handle_type {
80 /** GEM flink name (needs DRM authentication, used by DRI2) */
81 amdgpu_bo_handle_type_gem_flink_name = 0,
83 /** KMS handle which is used by all driver ioctls */
84 amdgpu_bo_handle_type_kms = 1,
86 /** DMA-buf fd handle */
87 amdgpu_bo_handle_type_dma_buf_fd = 2,
89 /** KMS handle, but re-importing as a DMABUF handle through
90 * drmPrimeHandleToFD is forbidden. (Glamor does that)
92 amdgpu_bo_handle_type_kms_noimport = 3,
95 /** Define known types of GPU VM VA ranges */
96 enum amdgpu_gpu_va_range
98 /** Allocate from "normal"/general range */
99 amdgpu_gpu_va_range_general = 0
102 enum amdgpu_sw_info {
103 amdgpu_sw_info_address32_hi = 0,
106 /*--------------------------------------------------------------------------*/
107 /* -------------------------- Datatypes ----------------------------------- */
108 /*--------------------------------------------------------------------------*/
111 * Define opaque pointer to context associated with fd.
112 * This context will be returned as the result of
113 * "initialize" function and should be pass as the first
114 * parameter to any API call
116 typedef struct amdgpu_device *amdgpu_device_handle;
119 * Define GPU Context type as pointer to opaque structure
120 * Example of GPU Context is the "rendering" context associated
121 * with OpenGL context (glCreateContext)
123 typedef struct amdgpu_context *amdgpu_context_handle;
126 * Define handle for amdgpu resources: buffer, GDS, etc.
128 typedef struct amdgpu_bo *amdgpu_bo_handle;
131 * Define handle for list of BOs
133 typedef struct amdgpu_bo_list *amdgpu_bo_list_handle;
136 * Define handle to be used to work with VA allocated ranges
138 typedef struct amdgpu_va *amdgpu_va_handle;
141 * Define handle for semaphore
143 typedef struct amdgpu_semaphore *amdgpu_semaphore_handle;
145 /*--------------------------------------------------------------------------*/
146 /* -------------------------- Structures ---------------------------------- */
147 /*--------------------------------------------------------------------------*/
150 * Structure describing memory allocation request
152 * \sa amdgpu_bo_alloc()
155 struct amdgpu_bo_alloc_request {
156 /** Allocation request. It must be aligned correctly. */
160 * It may be required to have some specific alignment requirements
161 * for physical back-up storage (e.g. for displayable surface).
162 * If 0 there is no special alignment requirement
164 uint64_t phys_alignment;
167 * UMD should specify where to allocate memory and how it
168 * will be accessed by the CPU.
170 uint32_t preferred_heap;
172 /** Additional flags passed on allocation */
177 * Special UMD specific information associated with buffer.
179 * It may be need to pass some buffer charactersitic as part
180 * of buffer sharing. Such information are defined UMD and
181 * opaque for libdrm_amdgpu as well for kernel driver.
183 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_query_info,
184 * amdgpu_bo_import(), amdgpu_bo_export
187 struct amdgpu_bo_metadata {
188 /** Special flag associated with surface */
192 * ASIC-specific tiling information (also used by DCE).
193 * The encoding is defined by the AMDGPU_TILING_* definitions.
195 uint64_t tiling_info;
197 /** Size of metadata associated with the buffer, in bytes. */
198 uint32_t size_metadata;
200 /** UMD specific metadata. Opaque for kernel */
201 uint32_t umd_metadata[64];
205 * Structure describing allocated buffer. Client may need
206 * to query such information as part of 'sharing' buffers mechanism
208 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_query_info(),
209 * amdgpu_bo_import(), amdgpu_bo_export()
211 struct amdgpu_bo_info {
212 /** Allocated memory size */
216 * It may be required to have some specific alignment requirements
217 * for physical back-up storage.
219 uint64_t phys_alignment;
221 /** Heap where to allocate memory. */
222 uint32_t preferred_heap;
224 /** Additional allocation flags. */
225 uint64_t alloc_flags;
227 /** Metadata associated with buffer if any. */
228 struct amdgpu_bo_metadata metadata;
232 * Structure with information about "imported" buffer
234 * \sa amdgpu_bo_import()
237 struct amdgpu_bo_import_result {
238 /** Handle of memory/buffer to use */
239 amdgpu_bo_handle buf_handle;
247 * Structure to describe GDS partitioning information.
248 * \note OA and GWS resources are asscoiated with GDS partition
250 * \sa amdgpu_gpu_resource_query_gds_info
253 struct amdgpu_gds_resource_info {
254 uint32_t gds_gfx_partition_size;
255 uint32_t compute_partition_size;
256 uint32_t gds_total_size;
257 uint32_t gws_per_gfx_partition;
258 uint32_t gws_per_compute_partition;
259 uint32_t oa_per_gfx_partition;
260 uint32_t oa_per_compute_partition;
264 * Structure describing CS fence
266 * \sa amdgpu_cs_query_fence_status(), amdgpu_cs_request, amdgpu_cs_submit()
269 struct amdgpu_cs_fence {
271 /** In which context IB was sent to execution */
272 amdgpu_context_handle context;
274 /** To which HW IP type the fence belongs */
277 /** IP instance index if there are several IPs of the same type. */
278 uint32_t ip_instance;
280 /** Ring index of the HW IP */
283 /** Specify fence for which we need to check submission status.*/
288 * Structure describing IB
290 * \sa amdgpu_cs_request, amdgpu_cs_submit()
293 struct amdgpu_cs_ib_info {
297 /** Virtual MC address of the command buffer */
298 uint64_t ib_mc_address;
301 * Size of Command Buffer to be submitted.
302 * - The size is in units of dwords (4 bytes).
309 * Structure describing fence information
311 * \sa amdgpu_cs_request, amdgpu_cs_query_fence,
312 * amdgpu_cs_submit(), amdgpu_cs_query_fence_status()
314 struct amdgpu_cs_fence_info {
315 /** buffer object for the fence */
316 amdgpu_bo_handle handle;
318 /** fence offset in the unit of sizeof(uint64_t) */
323 * Structure describing submission request
325 * \note We could have several IBs as packet. e.g. CE, CE, DE case for gfx
327 * \sa amdgpu_cs_submit()
329 struct amdgpu_cs_request {
330 /** Specify flags with additional information */
333 /** Specify HW IP block type to which to send the IB. */
336 /** IP instance index if there are several IPs of the same type. */
337 unsigned ip_instance;
340 * Specify ring index of the IP. We could have several rings
341 * in the same IP. E.g. 0 for SDMA0 and 1 for SDMA1.
346 * List handle with resources used by this request.
348 amdgpu_bo_list_handle resources;
351 * Number of dependencies this Command submission needs to
352 * wait for before starting execution.
354 uint32_t number_of_dependencies;
357 * Array of dependencies which need to be met before
358 * execution can start.
360 struct amdgpu_cs_fence *dependencies;
362 /** Number of IBs to submit in the field ibs. */
363 uint32_t number_of_ibs;
366 * IBs to submit. Those IBs will be submit together as single entity
368 struct amdgpu_cs_ib_info *ibs;
371 * The returned sequence number for the command submission
376 * The fence information
378 struct amdgpu_cs_fence_info fence_info;
382 * Structure which provide information about GPU VM MC Address space
383 * alignments requirements
385 * \sa amdgpu_query_buffer_size_alignment
387 struct amdgpu_buffer_size_alignments {
388 /** Size alignment requirement for allocation in
393 * Size alignment requirement for allocation in remote memory
395 uint64_t size_remote;
399 * Structure which provide information about heap
401 * \sa amdgpu_query_heap_info()
404 struct amdgpu_heap_info {
405 /** Theoretical max. available memory in the given heap */
409 * Number of bytes allocated in the heap. This includes all processes
410 * and private allocations in the kernel. It changes when new buffers
411 * are allocated, freed, and moved. It cannot be larger than
417 * Theoretical possible max. size of buffer which
418 * could be allocated in the given heap
420 uint64_t max_allocation;
424 * Describe GPU h/w info needed for UMD correct initialization
426 * \sa amdgpu_query_gpu_info()
428 struct amdgpu_gpu_info {
433 /** Chip external revision */
434 uint32_t chip_external_rev;
439 /** max engine clock*/
440 uint64_t max_engine_clk;
441 /** max memory clock */
442 uint64_t max_memory_clk;
443 /** number of shader engines */
444 uint32_t num_shader_engines;
445 /** number of shader arrays per engine */
446 uint32_t num_shader_arrays_per_engine;
447 /** Number of available good shader pipes */
448 uint32_t avail_quad_shader_pipes;
449 /** Max. number of shader pipes.(including good and bad pipes */
450 uint32_t max_quad_shader_pipes;
451 /** Number of parameter cache entries per shader quad pipe */
452 uint32_t cache_entries_per_quad_pipe;
453 /** Number of available graphics context */
454 uint32_t num_hw_gfx_contexts;
455 /** Number of render backend pipes */
457 /** Enabled render backend pipe mask */
458 uint32_t enabled_rb_pipes_mask;
459 /** Frequency of GPU Counter */
460 uint32_t gpu_counter_freq;
461 /** CC_RB_BACKEND_DISABLE.BACKEND_DISABLE per SE */
462 uint32_t backend_disable[4];
463 /** Value of MC_ARB_RAMCFG register*/
464 uint32_t mc_arb_ramcfg;
465 /** Value of GB_ADDR_CONFIG */
466 uint32_t gb_addr_cfg;
467 /** Values of the GB_TILE_MODE0..31 registers */
468 uint32_t gb_tile_mode[32];
469 /** Values of GB_MACROTILE_MODE0..15 registers */
470 uint32_t gb_macro_tile_mode[16];
471 /** Value of PA_SC_RASTER_CONFIG register per SE */
472 uint32_t pa_sc_raster_cfg[4];
473 /** Value of PA_SC_RASTER_CONFIG_1 register per SE */
474 uint32_t pa_sc_raster_cfg1[4];
476 uint32_t cu_active_number;
478 uint32_t cu_bitmap[4][4];
479 /* video memory type info*/
481 /* video memory bit width*/
482 uint32_t vram_bit_width;
483 /** constant engine ram size*/
484 uint32_t ce_ram_size;
485 /* vce harvesting instance */
486 uint32_t vce_harvest_config;
487 /* PCI revision ID */
492 /*--------------------------------------------------------------------------*/
493 /*------------------------- Functions --------------------------------------*/
494 /*--------------------------------------------------------------------------*/
497 * Initialization / Cleanup
503 * \param fd - \c [in] File descriptor for AMD GPU device
504 * received previously as the result of
505 * e.g. drmOpen() call.
506 * For legacy fd type, the DRI2/DRI3
507 * authentication should be done before
508 * calling this function.
509 * \param major_version - \c [out] Major version of library. It is assumed
510 * that adding new functionality will cause
511 * increase in major version
512 * \param minor_version - \c [out] Minor version of library
513 * \param device_handle - \c [out] Pointer to opaque context which should
514 * be passed as the first parameter on each
518 * \return 0 on success\n
519 * <0 - Negative POSIX Error code
522 * \sa amdgpu_device_deinitialize()
524 int amdgpu_device_initialize(int fd,
525 uint32_t *major_version,
526 uint32_t *minor_version,
527 amdgpu_device_handle *device_handle);
531 * When access to such library does not needed any more the special
532 * function must be call giving opportunity to clean up any
533 * resources if needed.
535 * \param device_handle - \c [in] Context associated with file
536 * descriptor for AMD GPU device
537 * received previously as the
538 * result e.g. of drmOpen() call.
540 * \return 0 on success\n
541 * <0 - Negative POSIX Error code
543 * \sa amdgpu_device_initialize()
546 int amdgpu_device_deinitialize(amdgpu_device_handle device_handle);
554 * Allocate memory to be used by UMD for GPU related operations
556 * \param dev - \c [in] Device handle.
557 * See #amdgpu_device_initialize()
558 * \param alloc_buffer - \c [in] Pointer to the structure describing an
560 * \param buf_handle - \c [out] Allocated buffer handle
562 * \return 0 on success\n
563 * <0 - Negative POSIX Error code
565 * \sa amdgpu_bo_free()
567 int amdgpu_bo_alloc(amdgpu_device_handle dev,
568 struct amdgpu_bo_alloc_request *alloc_buffer,
569 amdgpu_bo_handle *buf_handle);
572 * Associate opaque data with buffer to be queried by another UMD
574 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
575 * \param buf_handle - \c [in] Buffer handle
576 * \param info - \c [in] Metadata to associated with buffer
578 * \return 0 on success\n
579 * <0 - Negative POSIX Error code
581 int amdgpu_bo_set_metadata(amdgpu_bo_handle buf_handle,
582 struct amdgpu_bo_metadata *info);
585 * Query buffer information including metadata previusly associated with
588 * \param dev - \c [in] Device handle.
589 * See #amdgpu_device_initialize()
590 * \param buf_handle - \c [in] Buffer handle
591 * \param info - \c [out] Structure describing buffer
593 * \return 0 on success\n
594 * <0 - Negative POSIX Error code
596 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_alloc()
598 int amdgpu_bo_query_info(amdgpu_bo_handle buf_handle,
599 struct amdgpu_bo_info *info);
602 * Allow others to get access to buffer
604 * \param dev - \c [in] Device handle.
605 * See #amdgpu_device_initialize()
606 * \param buf_handle - \c [in] Buffer handle
607 * \param type - \c [in] Type of handle requested
608 * \param shared_handle - \c [out] Special "shared" handle
610 * \return 0 on success\n
611 * <0 - Negative POSIX Error code
613 * \sa amdgpu_bo_import()
616 int amdgpu_bo_export(amdgpu_bo_handle buf_handle,
617 enum amdgpu_bo_handle_type type,
618 uint32_t *shared_handle);
621 * Request access to "shared" buffer
623 * \param dev - \c [in] Device handle.
624 * See #amdgpu_device_initialize()
625 * \param type - \c [in] Type of handle requested
626 * \param shared_handle - \c [in] Shared handle received as result "import"
628 * \param output - \c [out] Pointer to structure with information
629 * about imported buffer
631 * \return 0 on success\n
632 * <0 - Negative POSIX Error code
634 * \note Buffer must be "imported" only using new "fd" (different from
635 * one used by "exporter").
637 * \sa amdgpu_bo_export()
640 int amdgpu_bo_import(amdgpu_device_handle dev,
641 enum amdgpu_bo_handle_type type,
642 uint32_t shared_handle,
643 struct amdgpu_bo_import_result *output);
646 * Request GPU access to user allocated memory e.g. via "malloc"
648 * \param dev - [in] Device handle. See #amdgpu_device_initialize()
649 * \param cpu - [in] CPU address of user allocated memory which we
650 * want to map to GPU address space (make GPU accessible)
651 * (This address must be correctly aligned).
652 * \param size - [in] Size of allocation (must be correctly aligned)
653 * \param buf_handle - [out] Buffer handle for the userptr memory
654 * resource on submission and be used in other operations.
657 * \return 0 on success\n
658 * <0 - Negative POSIX Error code
661 * This call doesn't guarantee that such memory will be persistently
662 * "locked" / make non-pageable. The purpose of this call is to provide
663 * opportunity for GPU get access to this resource during submission.
665 * The maximum amount of memory which could be mapped in this call depends
666 * if overcommit is disabled or not. If overcommit is disabled than the max.
667 * amount of memory to be pinned will be limited by left "free" size in total
668 * amount of memory which could be locked simultaneously ("GART" size).
670 * Supported (theoretical) max. size of mapping is restricted only by
673 * It is responsibility of caller to correctly specify access rights
676 int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev,
677 void *cpu, uint64_t size,
678 amdgpu_bo_handle *buf_handle);
681 * Validate if the user memory comes from BO
683 * \param dev - [in] Device handle. See #amdgpu_device_initialize()
684 * \param cpu - [in] CPU address of user allocated memory which we
685 * want to map to GPU address space (make GPU accessible)
686 * (This address must be correctly aligned).
687 * \param size - [in] Size of allocation (must be correctly aligned)
688 * \param buf_handle - [out] Buffer handle for the userptr memory
689 * if the user memory is not from BO, the buf_handle will be NULL.
690 * \param offset_in_bo - [out] offset in this BO for this user memory
693 * \return 0 on success\n
694 * <0 - Negative POSIX Error code
697 int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev,
700 amdgpu_bo_handle *buf_handle,
701 uint64_t *offset_in_bo);
704 * Free previosuly allocated memory
706 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
707 * \param buf_handle - \c [in] Buffer handle to free
709 * \return 0 on success\n
710 * <0 - Negative POSIX Error code
712 * \note In the case of memory shared between different applications all
713 * resources will be “physically” freed only all such applications
715 * \note If is UMD responsibility to ‘free’ buffer only when there is no
718 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_alloc()
721 int amdgpu_bo_free(amdgpu_bo_handle buf_handle);
724 * Increase the reference count of a buffer object
726 * \param bo - \c [in] Buffer object handle to increase the reference count
728 * \return 0 on success\n
729 * <0 - Negative POSIX Error code
731 * \sa amdgpu_bo_alloc(), amdgpu_bo_free()
734 int amdgpu_bo_inc_ref(amdgpu_bo_handle bo);
737 * Request CPU access to GPU accessable memory
739 * \param buf_handle - \c [in] Buffer handle
740 * \param cpu - \c [out] CPU address to be used for access
742 * \return 0 on success\n
743 * <0 - Negative POSIX Error code
745 * \sa amdgpu_bo_cpu_unmap()
748 int amdgpu_bo_cpu_map(amdgpu_bo_handle buf_handle, void **cpu);
751 * Release CPU access to GPU memory
753 * \param buf_handle - \c [in] Buffer handle
755 * \return 0 on success\n
756 * <0 - Negative POSIX Error code
758 * \sa amdgpu_bo_cpu_map()
761 int amdgpu_bo_cpu_unmap(amdgpu_bo_handle buf_handle);
764 * Wait until a buffer is not used by the device.
766 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
767 * \param buf_handle - \c [in] Buffer handle.
768 * \param timeout_ns - Timeout in nanoseconds.
769 * \param buffer_busy - 0 if buffer is idle, all GPU access was completed
770 * and no GPU access is scheduled.
771 * 1 GPU access is in fly or scheduled
773 * \return 0 - on success
774 * <0 - Negative POSIX Error code
776 int amdgpu_bo_wait_for_idle(amdgpu_bo_handle buf_handle,
781 * Creates a BO list handle for command submission.
783 * \param dev - \c [in] Device handle.
784 * See #amdgpu_device_initialize()
785 * \param number_of_resources - \c [in] Number of BOs in the list
786 * \param resources - \c [in] List of BO handles
787 * \param resource_prios - \c [in] Optional priority for each handle
788 * \param result - \c [out] Created BO list handle
790 * \return 0 on success\n
791 * <0 - Negative POSIX Error code
793 * \sa amdgpu_bo_list_destroy()
795 int amdgpu_bo_list_create(amdgpu_device_handle dev,
796 uint32_t number_of_resources,
797 amdgpu_bo_handle *resources,
798 uint8_t *resource_prios,
799 amdgpu_bo_list_handle *result);
802 * Destroys a BO list handle.
804 * \param handle - \c [in] BO list handle.
806 * \return 0 on success\n
807 * <0 - Negative POSIX Error code
809 * \sa amdgpu_bo_list_create()
811 int amdgpu_bo_list_destroy(amdgpu_bo_list_handle handle);
814 * Update resources for existing BO list
816 * \param handle - \c [in] BO list handle
817 * \param number_of_resources - \c [in] Number of BOs in the list
818 * \param resources - \c [in] List of BO handles
819 * \param resource_prios - \c [in] Optional priority for each handle
821 * \return 0 on success\n
822 * <0 - Negative POSIX Error code
824 * \sa amdgpu_bo_list_update()
826 int amdgpu_bo_list_update(amdgpu_bo_list_handle handle,
827 uint32_t number_of_resources,
828 amdgpu_bo_handle *resources,
829 uint8_t *resource_prios);
832 * GPU Execution context
837 * Create GPU execution Context
839 * For the purpose of GPU Scheduler and GPU Robustness extensions it is
840 * necessary to have information/identify rendering/compute contexts.
841 * It also may be needed to associate some specific requirements with such
842 * contexts. Kernel driver will guarantee that submission from the same
843 * context will always be executed in order (first come, first serve).
846 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
847 * \param priority - \c [in] Context creation flags. See AMDGPU_CTX_PRIORITY_*
848 * \param context - \c [out] GPU Context handle
850 * \return 0 on success\n
851 * <0 - Negative POSIX Error code
853 * \sa amdgpu_cs_ctx_free()
856 int amdgpu_cs_ctx_create2(amdgpu_device_handle dev,
858 amdgpu_context_handle *context);
860 * Create GPU execution Context
862 * Refer to amdgpu_cs_ctx_create2 for full documentation. This call
863 * is missing the priority parameter.
865 * \sa amdgpu_cs_ctx_create2()
868 int amdgpu_cs_ctx_create(amdgpu_device_handle dev,
869 amdgpu_context_handle *context);
873 * Destroy GPU execution context when not needed any more
875 * \param context - \c [in] GPU Context handle
877 * \return 0 on success\n
878 * <0 - Negative POSIX Error code
880 * \sa amdgpu_cs_ctx_create()
883 int amdgpu_cs_ctx_free(amdgpu_context_handle context);
886 * Query reset state for the specific GPU Context
888 * \param context - \c [in] GPU Context handle
889 * \param state - \c [out] One of AMDGPU_CTX_*_RESET
890 * \param hangs - \c [out] Number of hangs caused by the context.
892 * \return 0 on success\n
893 * <0 - Negative POSIX Error code
895 * \sa amdgpu_cs_ctx_create()
898 int amdgpu_cs_query_reset_state(amdgpu_context_handle context,
899 uint32_t *state, uint32_t *hangs);
902 * Command Buffers Management
907 * Send request to submit command buffers to hardware.
909 * Kernel driver could use GPU Scheduler to make decision when physically
910 * sent this request to the hardware. Accordingly this request could be put
911 * in queue and sent for execution later. The only guarantee is that request
912 * from the same GPU context to the same ip:ip_instance:ring will be executed in
915 * The caller can specify the user fence buffer/location with the fence_info in the
916 * cs_request.The sequence number is returned via the 'seq_no' parameter
917 * in ibs_request structure.
920 * \param dev - \c [in] Device handle.
921 * See #amdgpu_device_initialize()
922 * \param context - \c [in] GPU Context
923 * \param flags - \c [in] Global submission flags
924 * \param ibs_request - \c [in/out] Pointer to submission requests.
925 * We could submit to the several
926 * engines/rings simulteniously as
928 * \param number_of_requests - \c [in] Number of submission requests
930 * \return 0 on success\n
931 * <0 - Negative POSIX Error code
933 * \note It is required to pass correct resource list with buffer handles
934 * which will be accessible by command buffers from submission
935 * This will allow kernel driver to correctly implement "paging".
936 * Failure to do so will have unpredictable results.
938 * \sa amdgpu_command_buffer_alloc(), amdgpu_command_buffer_free(),
939 * amdgpu_cs_query_fence_status()
942 int amdgpu_cs_submit(amdgpu_context_handle context,
944 struct amdgpu_cs_request *ibs_request,
945 uint32_t number_of_requests);
948 * Query status of Command Buffer Submission
950 * \param fence - \c [in] Structure describing fence to query
951 * \param timeout_ns - \c [in] Timeout value to wait
952 * \param flags - \c [in] Flags for the query
953 * \param expired - \c [out] If fence expired or not.\n
954 * 0 – if fence is not expired\n
957 * \return 0 on success\n
958 * <0 - Negative POSIX Error code
960 * \note If UMD wants only to check operation status and returned immediately
961 * then timeout value as 0 must be passed. In this case success will be
962 * returned in the case if submission was completed or timeout error
965 * \sa amdgpu_cs_submit()
967 int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence,
973 * Wait for multiple fences
975 * \param fences - \c [in] The fence array to wait
976 * \param fence_count - \c [in] The fence count
977 * \param wait_all - \c [in] If true, wait all fences to be signaled,
978 * otherwise, wait at least one fence
979 * \param timeout_ns - \c [in] The timeout to wait, in nanoseconds
980 * \param status - \c [out] '1' for signaled, '0' for timeout
981 * \param first - \c [out] the index of the first signaled fence from @fences
983 * \return 0 on success
984 * <0 - Negative POSIX Error code
986 * \note Currently it supports only one amdgpu_device. All fences come from
987 * the same amdgpu_device with the same fd.
989 int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences,
990 uint32_t fence_count,
993 uint32_t *status, uint32_t *first);
1001 * Query allocation size alignments
1003 * UMD should query information about GPU VM MC size alignments requirements
1004 * to be able correctly choose required allocation size and implement
1005 * internal optimization if needed.
1007 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
1008 * \param info - \c [out] Pointer to structure to get size alignment
1011 * \return 0 on success\n
1012 * <0 - Negative POSIX Error code
1015 int amdgpu_query_buffer_size_alignment(amdgpu_device_handle dev,
1016 struct amdgpu_buffer_size_alignments
1020 * Query firmware versions
1022 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
1023 * \param fw_type - \c [in] AMDGPU_INFO_FW_*
1024 * \param ip_instance - \c [in] Index of the IP block of the same type.
1025 * \param index - \c [in] Index of the engine. (for SDMA and MEC)
1026 * \param version - \c [out] Pointer to to the "version" return value
1027 * \param feature - \c [out] Pointer to to the "feature" return value
1029 * \return 0 on success\n
1030 * <0 - Negative POSIX Error code
1033 int amdgpu_query_firmware_version(amdgpu_device_handle dev, unsigned fw_type,
1034 unsigned ip_instance, unsigned index,
1035 uint32_t *version, uint32_t *feature);
1038 * Query the number of HW IP instances of a certain type.
1040 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
1041 * \param type - \c [in] Hardware IP block type = AMDGPU_HW_IP_*
1042 * \param count - \c [out] Pointer to structure to get information
1044 * \return 0 on success\n
1045 * <0 - Negative POSIX Error code
1047 int amdgpu_query_hw_ip_count(amdgpu_device_handle dev, unsigned type,
1051 * Query engine information
1053 * This query allows UMD to query information different engines and their
1056 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
1057 * \param type - \c [in] Hardware IP block type = AMDGPU_HW_IP_*
1058 * \param ip_instance - \c [in] Index of the IP block of the same type.
1059 * \param info - \c [out] Pointer to structure to get information
1061 * \return 0 on success\n
1062 * <0 - Negative POSIX Error code
1064 int amdgpu_query_hw_ip_info(amdgpu_device_handle dev, unsigned type,
1065 unsigned ip_instance,
1066 struct drm_amdgpu_info_hw_ip *info);
1069 * Query heap information
1071 * This query allows UMD to query potentially available memory resources and
1072 * adjust their logic if necessary.
1074 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
1075 * \param heap - \c [in] Heap type
1076 * \param info - \c [in] Pointer to structure to get needed information
1078 * \return 0 on success\n
1079 * <0 - Negative POSIX Error code
1082 int amdgpu_query_heap_info(amdgpu_device_handle dev, uint32_t heap,
1083 uint32_t flags, struct amdgpu_heap_info *info);
1086 * Get the CRTC ID from the mode object ID
1088 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
1089 * \param id - \c [in] Mode object ID
1090 * \param result - \c [in] Pointer to the CRTC ID
1092 * \return 0 on success\n
1093 * <0 - Negative POSIX Error code
1096 int amdgpu_query_crtc_from_id(amdgpu_device_handle dev, unsigned id,
1100 * Query GPU H/w Info
1102 * Query hardware specific information
1104 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
1105 * \param heap - \c [in] Heap type
1106 * \param info - \c [in] Pointer to structure to get needed information
1108 * \return 0 on success\n
1109 * <0 - Negative POSIX Error code
1112 int amdgpu_query_gpu_info(amdgpu_device_handle dev,
1113 struct amdgpu_gpu_info *info);
1116 * Query hardware or driver information.
1118 * The return size is query-specific and depends on the "info_id" parameter.
1119 * No more than "size" bytes is returned.
1121 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
1122 * \param info_id - \c [in] AMDGPU_INFO_*
1123 * \param size - \c [in] Size of the returned value.
1124 * \param value - \c [out] Pointer to the return value.
1126 * \return 0 on success\n
1127 * <0 - Negative POSIX error code
1130 int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id,
1131 unsigned size, void *value);
1134 * Query hardware or driver information.
1136 * The return size is query-specific and depends on the "info_id" parameter.
1137 * No more than "size" bytes is returned.
1139 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
1140 * \param info - \c [in] amdgpu_sw_info_*
1141 * \param value - \c [out] Pointer to the return value.
1143 * \return 0 on success\n
1144 * <0 - Negative POSIX error code
1147 int amdgpu_query_sw_info(amdgpu_device_handle dev, enum amdgpu_sw_info info,
1151 * Query information about GDS
1153 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
1154 * \param gds_info - \c [out] Pointer to structure to get GDS information
1156 * \return 0 on success\n
1157 * <0 - Negative POSIX Error code
1160 int amdgpu_query_gds_info(amdgpu_device_handle dev,
1161 struct amdgpu_gds_resource_info *gds_info);
1164 * Query information about sensor.
1166 * The return size is query-specific and depends on the "sensor_type"
1167 * parameter. No more than "size" bytes is returned.
1169 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
1170 * \param sensor_type - \c [in] AMDGPU_INFO_SENSOR_*
1171 * \param size - \c [in] Size of the returned value.
1172 * \param value - \c [out] Pointer to the return value.
1174 * \return 0 on success\n
1175 * <0 - Negative POSIX Error code
1178 int amdgpu_query_sensor_info(amdgpu_device_handle dev, unsigned sensor_type,
1179 unsigned size, void *value);
1182 * Read a set of consecutive memory-mapped registers.
1183 * Not all registers are allowed to be read by userspace.
1185 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize(
1186 * \param dword_offset - \c [in] Register offset in dwords
1187 * \param count - \c [in] The number of registers to read starting
1189 * \param instance - \c [in] GRBM_GFX_INDEX selector. It may have other
1190 * uses. Set it to 0xffffffff if unsure.
1191 * \param flags - \c [in] Flags with additional information.
1192 * \param values - \c [out] The pointer to return values.
1194 * \return 0 on success\n
1195 * <0 - Negative POSIX error code
1198 int amdgpu_read_mm_registers(amdgpu_device_handle dev, unsigned dword_offset,
1199 unsigned count, uint32_t instance, uint32_t flags,
1203 * Flag to request VA address range in the 32bit address space
1205 #define AMDGPU_VA_RANGE_32_BIT 0x1
1206 #define AMDGPU_VA_RANGE_HIGH 0x2
1209 * Allocate virtual address range
1211 * \param dev - [in] Device handle. See #amdgpu_device_initialize()
1212 * \param va_range_type - \c [in] Type of MC va range from which to allocate
1213 * \param size - \c [in] Size of range. Size must be correctly* aligned.
1214 * It is client responsibility to correctly aligned size based on the future
1215 * usage of allocated range.
1216 * \param va_base_alignment - \c [in] Overwrite base address alignment
1217 * requirement for GPU VM MC virtual
1218 * address assignment. Must be multiple of size alignments received as
1219 * 'amdgpu_buffer_size_alignments'.
1220 * If 0 use the default one.
1221 * \param va_base_required - \c [in] Specified required va base address.
1222 * If 0 then library choose available one.
1223 * If !0 value will be passed and those value already "in use" then
1224 * corresponding error status will be returned.
1225 * \param va_base_allocated - \c [out] On return: Allocated VA base to be used
1227 * \param va_range_handle - \c [out] On return: Handle assigned to allocation
1228 * \param flags - \c [in] flags for special VA range
1230 * \return 0 on success\n
1231 * >0 - AMD specific error code\n
1232 * <0 - Negative POSIX Error code
1235 * It is client responsibility to correctly handle VA assignments and usage.
1236 * Neither kernel driver nor libdrm_amdpgu are able to prevent and
1237 * detect wrong va assignemnt.
1239 * It is client responsibility to correctly handle multi-GPU cases and to pass
1240 * the corresponding arrays of all devices handles where corresponding VA will
1244 int amdgpu_va_range_alloc(amdgpu_device_handle dev,
1245 enum amdgpu_gpu_va_range va_range_type,
1247 uint64_t va_base_alignment,
1248 uint64_t va_base_required,
1249 uint64_t *va_base_allocated,
1250 amdgpu_va_handle *va_range_handle,
1254 * Free previously allocated virtual address range
1257 * \param va_range_handle - \c [in] Handle assigned to VA allocation
1259 * \return 0 on success\n
1260 * >0 - AMD specific error code\n
1261 * <0 - Negative POSIX Error code
1264 int amdgpu_va_range_free(amdgpu_va_handle va_range_handle);
1267 * Query virtual address range
1269 * UMD can query GPU VM range supported by each device
1270 * to initialize its own VAM accordingly.
1272 * \param dev - [in] Device handle. See #amdgpu_device_initialize()
1273 * \param type - \c [in] Type of virtual address range
1274 * \param offset - \c [out] Start offset of virtual address range
1275 * \param size - \c [out] Size of virtual address range
1277 * \return 0 on success\n
1278 * <0 - Negative POSIX Error code
1282 int amdgpu_va_range_query(amdgpu_device_handle dev,
1283 enum amdgpu_gpu_va_range type,
1288 * VA mapping/unmapping for the buffer object
1290 * \param bo - \c [in] BO handle
1291 * \param offset - \c [in] Start offset to map
1292 * \param size - \c [in] Size to map
1293 * \param addr - \c [in] Start virtual address.
1294 * \param flags - \c [in] Supported flags for mapping/unmapping
1295 * \param ops - \c [in] AMDGPU_VA_OP_MAP or AMDGPU_VA_OP_UNMAP
1297 * \return 0 on success\n
1298 * <0 - Negative POSIX Error code
1302 int amdgpu_bo_va_op(amdgpu_bo_handle bo,
1310 * VA mapping/unmapping for a buffer object or PRT region.
1312 * This is not a simple drop-in extension for amdgpu_bo_va_op; instead, all
1313 * parameters are treated "raw", i.e. size is not automatically aligned, and
1314 * all flags must be specified explicitly.
1316 * \param dev - \c [in] device handle
1317 * \param bo - \c [in] BO handle (may be NULL)
1318 * \param offset - \c [in] Start offset to map
1319 * \param size - \c [in] Size to map
1320 * \param addr - \c [in] Start virtual address.
1321 * \param flags - \c [in] Supported flags for mapping/unmapping
1322 * \param ops - \c [in] AMDGPU_VA_OP_MAP or AMDGPU_VA_OP_UNMAP
1324 * \return 0 on success\n
1325 * <0 - Negative POSIX Error code
1329 int amdgpu_bo_va_op_raw(amdgpu_device_handle dev,
1330 amdgpu_bo_handle bo,
1340 * \param sem - \c [out] semaphore handle
1342 * \return 0 on success\n
1343 * <0 - Negative POSIX Error code
1346 int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle *sem);
1351 * \param context - \c [in] GPU Context
1352 * \param ip_type - \c [in] Hardware IP block type = AMDGPU_HW_IP_*
1353 * \param ip_instance - \c [in] Index of the IP block of the same type
1354 * \param ring - \c [in] Specify ring index of the IP
1355 * \param sem - \c [in] semaphore handle
1357 * \return 0 on success\n
1358 * <0 - Negative POSIX Error code
1361 int amdgpu_cs_signal_semaphore(amdgpu_context_handle ctx,
1363 uint32_t ip_instance,
1365 amdgpu_semaphore_handle sem);
1370 * \param context - \c [in] GPU Context
1371 * \param ip_type - \c [in] Hardware IP block type = AMDGPU_HW_IP_*
1372 * \param ip_instance - \c [in] Index of the IP block of the same type
1373 * \param ring - \c [in] Specify ring index of the IP
1374 * \param sem - \c [in] semaphore handle
1376 * \return 0 on success\n
1377 * <0 - Negative POSIX Error code
1380 int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx,
1382 uint32_t ip_instance,
1384 amdgpu_semaphore_handle sem);
1389 * \param sem - \c [in] semaphore handle
1391 * \return 0 on success\n
1392 * <0 - Negative POSIX Error code
1395 int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem);
1398 * Get the ASIC marketing name
1400 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
1402 * \return the constant string of the marketing name
1403 * "NULL" means the ASIC is not found
1405 const char *amdgpu_get_marketing_name(amdgpu_device_handle dev);
1408 * Create kernel sync object
1410 * \param dev - \c [in] device handle
1411 * \param flags - \c [in] flags that affect creation
1412 * \param syncobj - \c [out] sync object handle
1414 * \return 0 on success\n
1415 * <0 - Negative POSIX Error code
1418 int amdgpu_cs_create_syncobj2(amdgpu_device_handle dev,
1423 * Create kernel sync object
1425 * \param dev - \c [in] device handle
1426 * \param syncobj - \c [out] sync object handle
1428 * \return 0 on success\n
1429 * <0 - Negative POSIX Error code
1432 int amdgpu_cs_create_syncobj(amdgpu_device_handle dev,
1435 * Destroy kernel sync object
1437 * \param dev - \c [in] device handle
1438 * \param syncobj - \c [in] sync object handle
1440 * \return 0 on success\n
1441 * <0 - Negative POSIX Error code
1444 int amdgpu_cs_destroy_syncobj(amdgpu_device_handle dev,
1448 * Reset kernel sync objects to unsignalled state.
1450 * \param dev - \c [in] device handle
1451 * \param syncobjs - \c [in] array of sync object handles
1452 * \param syncobj_count - \c [in] number of handles in syncobjs
1454 * \return 0 on success\n
1455 * <0 - Negative POSIX Error code
1458 int amdgpu_cs_syncobj_reset(amdgpu_device_handle dev,
1459 const uint32_t *syncobjs, uint32_t syncobj_count);
1462 * Signal kernel sync objects.
1464 * \param dev - \c [in] device handle
1465 * \param syncobjs - \c [in] array of sync object handles
1466 * \param syncobj_count - \c [in] number of handles in syncobjs
1468 * \return 0 on success\n
1469 * <0 - Negative POSIX Error code
1472 int amdgpu_cs_syncobj_signal(amdgpu_device_handle dev,
1473 const uint32_t *syncobjs, uint32_t syncobj_count);
1476 * Wait for one or all sync objects to signal.
1478 * \param dev - \c [in] self-explanatory
1479 * \param handles - \c [in] array of sync object handles
1480 * \param num_handles - \c [in] self-explanatory
1481 * \param timeout_nsec - \c [in] self-explanatory
1482 * \param flags - \c [in] a bitmask of DRM_SYNCOBJ_WAIT_FLAGS_*
1483 * \param first_signaled - \c [in] self-explanatory
1485 * \return 0 on success\n
1487 * <0 - Negative POSIX Error code
1490 int amdgpu_cs_syncobj_wait(amdgpu_device_handle dev,
1491 uint32_t *handles, unsigned num_handles,
1492 int64_t timeout_nsec, unsigned flags,
1493 uint32_t *first_signaled);
1496 * Export kernel sync object to shareable fd.
1498 * \param dev - \c [in] device handle
1499 * \param syncobj - \c [in] sync object handle
1500 * \param shared_fd - \c [out] shared file descriptor.
1502 * \return 0 on success\n
1503 * <0 - Negative POSIX Error code
1506 int amdgpu_cs_export_syncobj(amdgpu_device_handle dev,
1510 * Import kernel sync object from shareable fd.
1512 * \param dev - \c [in] device handle
1513 * \param shared_fd - \c [in] shared file descriptor.
1514 * \param syncobj - \c [out] sync object handle
1516 * \return 0 on success\n
1517 * <0 - Negative POSIX Error code
1520 int amdgpu_cs_import_syncobj(amdgpu_device_handle dev,
1525 * Export kernel sync object to a sync_file.
1527 * \param dev - \c [in] device handle
1528 * \param syncobj - \c [in] sync object handle
1529 * \param sync_file_fd - \c [out] sync_file file descriptor.
1531 * \return 0 on success\n
1532 * <0 - Negative POSIX Error code
1535 int amdgpu_cs_syncobj_export_sync_file(amdgpu_device_handle dev,
1540 * Import kernel sync object from a sync_file.
1542 * \param dev - \c [in] device handle
1543 * \param syncobj - \c [in] sync object handle
1544 * \param sync_file_fd - \c [in] sync_file file descriptor.
1546 * \return 0 on success\n
1547 * <0 - Negative POSIX Error code
1550 int amdgpu_cs_syncobj_import_sync_file(amdgpu_device_handle dev,
1555 * Export an amdgpu fence as a handle (syncobj or fd).
1557 * \param what AMDGPU_FENCE_TO_HANDLE_GET_{SYNCOBJ, FD}
1558 * \param out_handle returned handle
1560 * \return 0 on success\n
1561 * <0 - Negative POSIX Error code
1563 int amdgpu_cs_fence_to_handle(amdgpu_device_handle dev,
1564 struct amdgpu_cs_fence *fence,
1566 uint32_t *out_handle);
1569 * Submit raw command submission to kernel
1571 * \param dev - \c [in] device handle
1572 * \param context - \c [in] context handle for context id
1573 * \param bo_list_handle - \c [in] request bo list handle (0 for none)
1574 * \param num_chunks - \c [in] number of CS chunks to submit
1575 * \param chunks - \c [in] array of CS chunks
1576 * \param seq_no - \c [out] output sequence number for submission.
1578 * \return 0 on success\n
1579 * <0 - Negative POSIX Error code
1582 struct drm_amdgpu_cs_chunk;
1583 struct drm_amdgpu_cs_chunk_dep;
1584 struct drm_amdgpu_cs_chunk_data;
1586 int amdgpu_cs_submit_raw(amdgpu_device_handle dev,
1587 amdgpu_context_handle context,
1588 amdgpu_bo_list_handle bo_list_handle,
1590 struct drm_amdgpu_cs_chunk *chunks,
1593 void amdgpu_cs_chunk_fence_to_dep(struct amdgpu_cs_fence *fence,
1594 struct drm_amdgpu_cs_chunk_dep *dep);
1595 void amdgpu_cs_chunk_fence_info_to_data(struct amdgpu_cs_fence_info *fence_info,
1596 struct drm_amdgpu_cs_chunk_data *data);
1600 * \param context - \c [in] GPU Context
1601 * \param flags - \c [in] TBD
1603 * \return 0 on success otherwise POSIX Error code
1605 int amdgpu_vm_reserve_vmid(amdgpu_device_handle dev, uint32_t flags);
1608 * Free reserved VMID
1609 * \param context - \c [in] GPU Context
1610 * \param flags - \c [in] TBD
1612 * \return 0 on success otherwise POSIX Error code
1614 int amdgpu_vm_unreserve_vmid(amdgpu_device_handle dev, uint32_t flags);
1619 #endif /* #ifdef _AMDGPU_H_ */