2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 * Declare public libdrm_amdgpu API
29 * This file define API exposed by libdrm_amdgpu library.
30 * User wanted to use libdrm_amdgpu functionality must include
40 struct drm_amdgpu_info_hw_ip;
42 /*--------------------------------------------------------------------------*/
43 /* --------------------------- Defines ------------------------------------ */
44 /*--------------------------------------------------------------------------*/
47 * Define max. number of Command Buffers (IB) which could be sent to the single
48 * hardware IP to accommodate CE/DE requirements
50 * \sa amdgpu_cs_ib_info
52 #define AMDGPU_CS_MAX_IBS_PER_SUBMIT 4
55 * Special timeout value meaning that the timeout is infinite.
57 #define AMDGPU_TIMEOUT_INFINITE 0xffffffffffffffffull
60 * Used in amdgpu_cs_query_fence_status(), meaning that the given timeout
63 #define AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE (1 << 0)
65 /*--------------------------------------------------------------------------*/
66 /* ----------------------------- Enums ------------------------------------ */
67 /*--------------------------------------------------------------------------*/
70 * Enum describing possible handle types
72 * \sa amdgpu_bo_import, amdgpu_bo_export
75 enum amdgpu_bo_handle_type {
76 /** GEM flink name (needs DRM authentication, used by DRI2) */
77 amdgpu_bo_handle_type_gem_flink_name = 0,
79 /** KMS handle which is used by all driver ioctls */
80 amdgpu_bo_handle_type_kms = 1,
82 /** DMA-buf fd handle */
83 amdgpu_bo_handle_type_dma_buf_fd = 2
86 /** Define known types of GPU VM VA ranges */
87 enum amdgpu_gpu_va_range
89 /** Allocate from "normal"/general range */
90 amdgpu_gpu_va_range_general = 0
93 /*--------------------------------------------------------------------------*/
94 /* -------------------------- Datatypes ----------------------------------- */
95 /*--------------------------------------------------------------------------*/
98 * Define opaque pointer to context associated with fd.
99 * This context will be returned as the result of
100 * "initialize" function and should be pass as the first
101 * parameter to any API call
103 typedef struct amdgpu_device *amdgpu_device_handle;
106 * Define GPU Context type as pointer to opaque structure
107 * Example of GPU Context is the "rendering" context associated
108 * with OpenGL context (glCreateContext)
110 typedef struct amdgpu_context *amdgpu_context_handle;
113 * Define handle for amdgpu resources: buffer, GDS, etc.
115 typedef struct amdgpu_bo *amdgpu_bo_handle;
118 * Define handle for list of BOs
120 typedef struct amdgpu_bo_list *amdgpu_bo_list_handle;
123 * Define handle to be used to work with VA allocated ranges
125 typedef struct amdgpu_va *amdgpu_va_handle;
127 /*--------------------------------------------------------------------------*/
128 /* -------------------------- Structures ---------------------------------- */
129 /*--------------------------------------------------------------------------*/
132 * Structure describing memory allocation request
134 * \sa amdgpu_bo_alloc()
137 struct amdgpu_bo_alloc_request {
138 /** Allocation request. It must be aligned correctly. */
142 * It may be required to have some specific alignment requirements
143 * for physical back-up storage (e.g. for displayable surface).
144 * If 0 there is no special alignment requirement
146 uint64_t phys_alignment;
149 * UMD should specify where to allocate memory and how it
150 * will be accessed by the CPU.
152 uint32_t preferred_heap;
154 /** Additional flags passed on allocation */
159 * Special UMD specific information associated with buffer.
161 * It may be need to pass some buffer charactersitic as part
162 * of buffer sharing. Such information are defined UMD and
163 * opaque for libdrm_amdgpu as well for kernel driver.
165 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_query_info,
166 * amdgpu_bo_import(), amdgpu_bo_export
169 struct amdgpu_bo_metadata {
170 /** Special flag associated with surface */
174 * ASIC-specific tiling information (also used by DCE).
175 * The encoding is defined by the AMDGPU_TILING_* definitions.
177 uint64_t tiling_info;
179 /** Size of metadata associated with the buffer, in bytes. */
180 uint32_t size_metadata;
182 /** UMD specific metadata. Opaque for kernel */
183 uint32_t umd_metadata[64];
187 * Structure describing allocated buffer. Client may need
188 * to query such information as part of 'sharing' buffers mechanism
190 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_query_info(),
191 * amdgpu_bo_import(), amdgpu_bo_export()
193 struct amdgpu_bo_info {
194 /** Allocated memory size */
198 * It may be required to have some specific alignment requirements
199 * for physical back-up storage.
201 uint64_t phys_alignment;
203 /** Heap where to allocate memory. */
204 uint32_t preferred_heap;
206 /** Additional allocation flags. */
207 uint64_t alloc_flags;
209 /** Metadata associated with buffer if any. */
210 struct amdgpu_bo_metadata metadata;
214 * Structure with information about "imported" buffer
216 * \sa amdgpu_bo_import()
219 struct amdgpu_bo_import_result {
220 /** Handle of memory/buffer to use */
221 amdgpu_bo_handle buf_handle;
229 * Structure to describe GDS partitioning information.
230 * \note OA and GWS resources are asscoiated with GDS partition
232 * \sa amdgpu_gpu_resource_query_gds_info
235 struct amdgpu_gds_resource_info {
236 uint32_t gds_gfx_partition_size;
237 uint32_t compute_partition_size;
238 uint32_t gds_total_size;
239 uint32_t gws_per_gfx_partition;
240 uint32_t gws_per_compute_partition;
241 uint32_t oa_per_gfx_partition;
242 uint32_t oa_per_compute_partition;
246 * Structure describing CS fence
248 * \sa amdgpu_cs_query_fence_status(), amdgpu_cs_request, amdgpu_cs_submit()
251 struct amdgpu_cs_fence {
253 /** In which context IB was sent to execution */
254 amdgpu_context_handle context;
256 /** To which HW IP type the fence belongs */
259 /** IP instance index if there are several IPs of the same type. */
260 uint32_t ip_instance;
262 /** Ring index of the HW IP */
265 /** Specify fence for which we need to check submission status.*/
270 * Structure describing IB
272 * \sa amdgpu_cs_request, amdgpu_cs_submit()
275 struct amdgpu_cs_ib_info {
279 /** Virtual MC address of the command buffer */
280 uint64_t ib_mc_address;
283 * Size of Command Buffer to be submitted.
284 * - The size is in units of dwords (4 bytes).
291 * Structure describing fence information
293 * \sa amdgpu_cs_request, amdgpu_cs_query_fence,
294 * amdgpu_cs_submit(), amdgpu_cs_query_fence_status()
296 struct amdgpu_cs_fence_info {
297 /** buffer object for the fence */
298 amdgpu_bo_handle handle;
300 /** fence offset in the unit of sizeof(uint64_t) */
305 * Structure describing submission request
307 * \note We could have several IBs as packet. e.g. CE, CE, DE case for gfx
309 * \sa amdgpu_cs_submit()
311 struct amdgpu_cs_request {
312 /** Specify flags with additional information */
315 /** Specify HW IP block type to which to send the IB. */
318 /** IP instance index if there are several IPs of the same type. */
319 unsigned ip_instance;
322 * Specify ring index of the IP. We could have several rings
323 * in the same IP. E.g. 0 for SDMA0 and 1 for SDMA1.
328 * List handle with resources used by this request.
330 amdgpu_bo_list_handle resources;
333 * Number of dependencies this Command submission needs to
334 * wait for before starting execution.
336 uint32_t number_of_dependencies;
339 * Array of dependencies which need to be met before
340 * execution can start.
342 struct amdgpu_cs_fence *dependencies;
344 /** Number of IBs to submit in the field ibs. */
345 uint32_t number_of_ibs;
348 * IBs to submit. Those IBs will be submit together as single entity
350 struct amdgpu_cs_ib_info *ibs;
353 * The returned sequence number for the command submission
358 * The fence information
360 struct amdgpu_cs_fence_info fence_info;
364 * Structure which provide information about GPU VM MC Address space
365 * alignments requirements
367 * \sa amdgpu_query_buffer_size_alignment
369 struct amdgpu_buffer_size_alignments {
370 /** Size alignment requirement for allocation in
375 * Size alignment requirement for allocation in remote memory
377 uint64_t size_remote;
381 * Structure which provide information about heap
383 * \sa amdgpu_query_heap_info()
386 struct amdgpu_heap_info {
387 /** Theoretical max. available memory in the given heap */
391 * Number of bytes allocated in the heap. This includes all processes
392 * and private allocations in the kernel. It changes when new buffers
393 * are allocated, freed, and moved. It cannot be larger than
399 * Theoretical possible max. size of buffer which
400 * could be allocated in the given heap
402 uint64_t max_allocation;
406 * Describe GPU h/w info needed for UMD correct initialization
408 * \sa amdgpu_query_gpu_info()
410 struct amdgpu_gpu_info {
415 /** Chip external revision */
416 uint32_t chip_external_rev;
421 /** max engine clock*/
422 uint64_t max_engine_clk;
423 /** max memory clock */
424 uint64_t max_memory_clk;
425 /** number of shader engines */
426 uint32_t num_shader_engines;
427 /** number of shader arrays per engine */
428 uint32_t num_shader_arrays_per_engine;
429 /** Number of available good shader pipes */
430 uint32_t avail_quad_shader_pipes;
431 /** Max. number of shader pipes.(including good and bad pipes */
432 uint32_t max_quad_shader_pipes;
433 /** Number of parameter cache entries per shader quad pipe */
434 uint32_t cache_entries_per_quad_pipe;
435 /** Number of available graphics context */
436 uint32_t num_hw_gfx_contexts;
437 /** Number of render backend pipes */
439 /** Enabled render backend pipe mask */
440 uint32_t enabled_rb_pipes_mask;
441 /** Frequency of GPU Counter */
442 uint32_t gpu_counter_freq;
443 /** CC_RB_BACKEND_DISABLE.BACKEND_DISABLE per SE */
444 uint32_t backend_disable[4];
445 /** Value of MC_ARB_RAMCFG register*/
446 uint32_t mc_arb_ramcfg;
447 /** Value of GB_ADDR_CONFIG */
448 uint32_t gb_addr_cfg;
449 /** Values of the GB_TILE_MODE0..31 registers */
450 uint32_t gb_tile_mode[32];
451 /** Values of GB_MACROTILE_MODE0..15 registers */
452 uint32_t gb_macro_tile_mode[16];
453 /** Value of PA_SC_RASTER_CONFIG register per SE */
454 uint32_t pa_sc_raster_cfg[4];
455 /** Value of PA_SC_RASTER_CONFIG_1 register per SE */
456 uint32_t pa_sc_raster_cfg1[4];
458 uint32_t cu_active_number;
460 uint32_t cu_bitmap[4][4];
461 /* video memory type info*/
463 /* video memory bit width*/
464 uint32_t vram_bit_width;
465 /** constant engine ram size*/
466 uint32_t ce_ram_size;
467 /* vce harvesting instance */
468 uint32_t vce_harvest_config;
469 /* PCI revision ID */
474 /*--------------------------------------------------------------------------*/
475 /*------------------------- Functions --------------------------------------*/
476 /*--------------------------------------------------------------------------*/
479 * Initialization / Cleanup
485 * \param fd - \c [in] File descriptor for AMD GPU device
486 * received previously as the result of
487 * e.g. drmOpen() call.
488 * For legacy fd type, the DRI2/DRI3
489 * authentication should be done before
490 * calling this function.
491 * \param major_version - \c [out] Major version of library. It is assumed
492 * that adding new functionality will cause
493 * increase in major version
494 * \param minor_version - \c [out] Minor version of library
495 * \param device_handle - \c [out] Pointer to opaque context which should
496 * be passed as the first parameter on each
500 * \return 0 on success\n
501 * <0 - Negative POSIX Error code
504 * \sa amdgpu_device_deinitialize()
506 int amdgpu_device_initialize(int fd,
507 uint32_t *major_version,
508 uint32_t *minor_version,
509 amdgpu_device_handle *device_handle);
513 * When access to such library does not needed any more the special
514 * function must be call giving opportunity to clean up any
515 * resources if needed.
517 * \param device_handle - \c [in] Context associated with file
518 * descriptor for AMD GPU device
519 * received previously as the
520 * result e.g. of drmOpen() call.
522 * \return 0 on success\n
523 * <0 - Negative POSIX Error code
525 * \sa amdgpu_device_initialize()
528 int amdgpu_device_deinitialize(amdgpu_device_handle device_handle);
536 * Allocate memory to be used by UMD for GPU related operations
538 * \param dev - \c [in] Device handle.
539 * See #amdgpu_device_initialize()
540 * \param alloc_buffer - \c [in] Pointer to the structure describing an
542 * \param buf_handle - \c [out] Allocated buffer handle
544 * \return 0 on success\n
545 * <0 - Negative POSIX Error code
547 * \sa amdgpu_bo_free()
549 int amdgpu_bo_alloc(amdgpu_device_handle dev,
550 struct amdgpu_bo_alloc_request *alloc_buffer,
551 amdgpu_bo_handle *buf_handle);
554 * Associate opaque data with buffer to be queried by another UMD
556 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
557 * \param buf_handle - \c [in] Buffer handle
558 * \param info - \c [in] Metadata to associated with buffer
560 * \return 0 on success\n
561 * <0 - Negative POSIX Error code
563 int amdgpu_bo_set_metadata(amdgpu_bo_handle buf_handle,
564 struct amdgpu_bo_metadata *info);
567 * Query buffer information including metadata previusly associated with
570 * \param dev - \c [in] Device handle.
571 * See #amdgpu_device_initialize()
572 * \param buf_handle - \c [in] Buffer handle
573 * \param info - \c [out] Structure describing buffer
575 * \return 0 on success\n
576 * <0 - Negative POSIX Error code
578 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_alloc()
580 int amdgpu_bo_query_info(amdgpu_bo_handle buf_handle,
581 struct amdgpu_bo_info *info);
584 * Allow others to get access to buffer
586 * \param dev - \c [in] Device handle.
587 * See #amdgpu_device_initialize()
588 * \param buf_handle - \c [in] Buffer handle
589 * \param type - \c [in] Type of handle requested
590 * \param shared_handle - \c [out] Special "shared" handle
592 * \return 0 on success\n
593 * <0 - Negative POSIX Error code
595 * \sa amdgpu_bo_import()
598 int amdgpu_bo_export(amdgpu_bo_handle buf_handle,
599 enum amdgpu_bo_handle_type type,
600 uint32_t *shared_handle);
603 * Request access to "shared" buffer
605 * \param dev - \c [in] Device handle.
606 * See #amdgpu_device_initialize()
607 * \param type - \c [in] Type of handle requested
608 * \param shared_handle - \c [in] Shared handle received as result "import"
610 * \param output - \c [out] Pointer to structure with information
611 * about imported buffer
613 * \return 0 on success\n
614 * <0 - Negative POSIX Error code
616 * \note Buffer must be "imported" only using new "fd" (different from
617 * one used by "exporter").
619 * \sa amdgpu_bo_export()
622 int amdgpu_bo_import(amdgpu_device_handle dev,
623 enum amdgpu_bo_handle_type type,
624 uint32_t shared_handle,
625 struct amdgpu_bo_import_result *output);
628 * Request GPU access to user allocated memory e.g. via "malloc"
630 * \param dev - [in] Device handle. See #amdgpu_device_initialize()
631 * \param cpu - [in] CPU address of user allocated memory which we
632 * want to map to GPU address space (make GPU accessible)
633 * (This address must be correctly aligned).
634 * \param size - [in] Size of allocation (must be correctly aligned)
635 * \param buf_handle - [out] Buffer handle for the userptr memory
636 * resource on submission and be used in other operations.
639 * \return 0 on success\n
640 * <0 - Negative POSIX Error code
643 * This call doesn't guarantee that such memory will be persistently
644 * "locked" / make non-pageable. The purpose of this call is to provide
645 * opportunity for GPU get access to this resource during submission.
647 * The maximum amount of memory which could be mapped in this call depends
648 * if overcommit is disabled or not. If overcommit is disabled than the max.
649 * amount of memory to be pinned will be limited by left "free" size in total
650 * amount of memory which could be locked simultaneously ("GART" size).
652 * Supported (theoretical) max. size of mapping is restricted only by
655 * It is responsibility of caller to correctly specify access rights
658 int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev,
659 void *cpu, uint64_t size,
660 amdgpu_bo_handle *buf_handle);
663 * Free previosuly allocated memory
665 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
666 * \param buf_handle - \c [in] Buffer handle to free
668 * \return 0 on success\n
669 * <0 - Negative POSIX Error code
671 * \note In the case of memory shared between different applications all
672 * resources will be “physically” freed only all such applications
674 * \note If is UMD responsibility to ‘free’ buffer only when there is no
677 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_alloc()
680 int amdgpu_bo_free(amdgpu_bo_handle buf_handle);
683 * Request CPU access to GPU accessable memory
685 * \param buf_handle - \c [in] Buffer handle
686 * \param cpu - \c [out] CPU address to be used for access
688 * \return 0 on success\n
689 * <0 - Negative POSIX Error code
691 * \sa amdgpu_bo_cpu_unmap()
694 int amdgpu_bo_cpu_map(amdgpu_bo_handle buf_handle, void **cpu);
697 * Release CPU access to GPU memory
699 * \param buf_handle - \c [in] Buffer handle
701 * \return 0 on success\n
702 * <0 - Negative POSIX Error code
704 * \sa amdgpu_bo_cpu_map()
707 int amdgpu_bo_cpu_unmap(amdgpu_bo_handle buf_handle);
710 * Wait until a buffer is not used by the device.
712 * \param dev - \c [in] Device handle. See #amdgpu_lib_initialize()
713 * \param buf_handle - \c [in] Buffer handle.
714 * \param timeout_ns - Timeout in nanoseconds.
715 * \param buffer_busy - 0 if buffer is idle, all GPU access was completed
716 * and no GPU access is scheduled.
717 * 1 GPU access is in fly or scheduled
719 * \return 0 - on success
720 * <0 - Negative POSIX Error code
722 int amdgpu_bo_wait_for_idle(amdgpu_bo_handle buf_handle,
727 * Creates a BO list handle for command submission.
729 * \param dev - \c [in] Device handle.
730 * See #amdgpu_device_initialize()
731 * \param number_of_resources - \c [in] Number of BOs in the list
732 * \param resources - \c [in] List of BO handles
733 * \param resource_prios - \c [in] Optional priority for each handle
734 * \param result - \c [out] Created BO list handle
736 * \return 0 on success\n
737 * <0 - Negative POSIX Error code
739 * \sa amdgpu_bo_list_destroy()
741 int amdgpu_bo_list_create(amdgpu_device_handle dev,
742 uint32_t number_of_resources,
743 amdgpu_bo_handle *resources,
744 uint8_t *resource_prios,
745 amdgpu_bo_list_handle *result);
748 * Destroys a BO list handle.
750 * \param handle - \c [in] BO list handle.
752 * \return 0 on success\n
753 * <0 - Negative POSIX Error code
755 * \sa amdgpu_bo_list_create()
757 int amdgpu_bo_list_destroy(amdgpu_bo_list_handle handle);
760 * Update resources for existing BO list
762 * \param handle - \c [in] BO list handle
763 * \param number_of_resources - \c [in] Number of BOs in the list
764 * \param resources - \c [in] List of BO handles
765 * \param resource_prios - \c [in] Optional priority for each handle
767 * \return 0 on success\n
768 * <0 - Negative POSIX Error code
770 * \sa amdgpu_bo_list_update()
772 int amdgpu_bo_list_update(amdgpu_bo_list_handle handle,
773 uint32_t number_of_resources,
774 amdgpu_bo_handle *resources,
775 uint8_t *resource_prios);
778 * GPU Execution context
783 * Create GPU execution Context
785 * For the purpose of GPU Scheduler and GPU Robustness extensions it is
786 * necessary to have information/identify rendering/compute contexts.
787 * It also may be needed to associate some specific requirements with such
788 * contexts. Kernel driver will guarantee that submission from the same
789 * context will always be executed in order (first come, first serve).
792 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
793 * \param context - \c [out] GPU Context handle
795 * \return 0 on success\n
796 * <0 - Negative POSIX Error code
798 * \sa amdgpu_cs_ctx_free()
801 int amdgpu_cs_ctx_create(amdgpu_device_handle dev,
802 amdgpu_context_handle *context);
806 * Destroy GPU execution context when not needed any more
808 * \param context - \c [in] GPU Context handle
810 * \return 0 on success\n
811 * <0 - Negative POSIX Error code
813 * \sa amdgpu_cs_ctx_create()
816 int amdgpu_cs_ctx_free(amdgpu_context_handle context);
819 * Query reset state for the specific GPU Context
821 * \param context - \c [in] GPU Context handle
822 * \param state - \c [out] One of AMDGPU_CTX_*_RESET
823 * \param hangs - \c [out] Number of hangs caused by the context.
825 * \return 0 on success\n
826 * <0 - Negative POSIX Error code
828 * \sa amdgpu_cs_ctx_create()
831 int amdgpu_cs_query_reset_state(amdgpu_context_handle context,
832 uint32_t *state, uint32_t *hangs);
835 * Command Buffers Management
840 * Send request to submit command buffers to hardware.
842 * Kernel driver could use GPU Scheduler to make decision when physically
843 * sent this request to the hardware. Accordingly this request could be put
844 * in queue and sent for execution later. The only guarantee is that request
845 * from the same GPU context to the same ip:ip_instance:ring will be executed in
848 * The caller can specify the user fence buffer/location with the fence_info in the
849 * cs_request.The sequence number is returned via the 'seq_no' paramter
850 * in ibs_request structure.
853 * \param dev - \c [in] Device handle.
854 * See #amdgpu_device_initialize()
855 * \param context - \c [in] GPU Context
856 * \param flags - \c [in] Global submission flags
857 * \param ibs_request - \c [in/out] Pointer to submission requests.
858 * We could submit to the several
859 * engines/rings simulteniously as
861 * \param number_of_requests - \c [in] Number of submission requests
863 * \return 0 on success\n
864 * <0 - Negative POSIX Error code
866 * \note It is required to pass correct resource list with buffer handles
867 * which will be accessible by command buffers from submission
868 * This will allow kernel driver to correctly implement "paging".
869 * Failure to do so will have unpredictable results.
871 * \sa amdgpu_command_buffer_alloc(), amdgpu_command_buffer_free(),
872 * amdgpu_cs_query_fence_status()
875 int amdgpu_cs_submit(amdgpu_context_handle context,
877 struct amdgpu_cs_request *ibs_request,
878 uint32_t number_of_requests);
881 * Query status of Command Buffer Submission
883 * \param fence - \c [in] Structure describing fence to query
884 * \param timeout_ns - \c [in] Timeout value to wait
885 * \param flags - \c [in] Flags for the query
886 * \param expired - \c [out] If fence expired or not.\n
887 * 0 – if fence is not expired\n
890 * \return 0 on success\n
891 * <0 - Negative POSIX Error code
893 * \note If UMD wants only to check operation status and returned immediately
894 * then timeout value as 0 must be passed. In this case success will be
895 * returned in the case if submission was completed or timeout error
898 * \sa amdgpu_cs_submit()
900 int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence,
911 * Query allocation size alignments
913 * UMD should query information about GPU VM MC size alignments requirements
914 * to be able correctly choose required allocation size and implement
915 * internal optimization if needed.
917 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
918 * \param info - \c [out] Pointer to structure to get size alignment
921 * \return 0 on success\n
922 * <0 - Negative POSIX Error code
925 int amdgpu_query_buffer_size_alignment(amdgpu_device_handle dev,
926 struct amdgpu_buffer_size_alignments
930 * Query firmware versions
932 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
933 * \param fw_type - \c [in] AMDGPU_INFO_FW_*
934 * \param ip_instance - \c [in] Index of the IP block of the same type.
935 * \param index - \c [in] Index of the engine. (for SDMA and MEC)
936 * \param version - \c [out] Pointer to to the "version" return value
937 * \param feature - \c [out] Pointer to to the "feature" return value
939 * \return 0 on success\n
940 * <0 - Negative POSIX Error code
943 int amdgpu_query_firmware_version(amdgpu_device_handle dev, unsigned fw_type,
944 unsigned ip_instance, unsigned index,
945 uint32_t *version, uint32_t *feature);
948 * Query the number of HW IP instances of a certain type.
950 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
951 * \param type - \c [in] Hardware IP block type = AMDGPU_HW_IP_*
952 * \param count - \c [out] Pointer to structure to get information
954 * \return 0 on success\n
955 * <0 - Negative POSIX Error code
957 int amdgpu_query_hw_ip_count(amdgpu_device_handle dev, unsigned type,
961 * Query engine information
963 * This query allows UMD to query information different engines and their
966 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
967 * \param type - \c [in] Hardware IP block type = AMDGPU_HW_IP_*
968 * \param ip_instance - \c [in] Index of the IP block of the same type.
969 * \param info - \c [out] Pointer to structure to get information
971 * \return 0 on success\n
972 * <0 - Negative POSIX Error code
974 int amdgpu_query_hw_ip_info(amdgpu_device_handle dev, unsigned type,
975 unsigned ip_instance,
976 struct drm_amdgpu_info_hw_ip *info);
979 * Query heap information
981 * This query allows UMD to query potentially available memory resources and
982 * adjust their logic if necessary.
984 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
985 * \param heap - \c [in] Heap type
986 * \param info - \c [in] Pointer to structure to get needed information
988 * \return 0 on success\n
989 * <0 - Negative POSIX Error code
992 int amdgpu_query_heap_info(amdgpu_device_handle dev, uint32_t heap,
993 uint32_t flags, struct amdgpu_heap_info *info);
996 * Get the CRTC ID from the mode object ID
998 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
999 * \param id - \c [in] Mode object ID
1000 * \param result - \c [in] Pointer to the CRTC ID
1002 * \return 0 on success\n
1003 * <0 - Negative POSIX Error code
1006 int amdgpu_query_crtc_from_id(amdgpu_device_handle dev, unsigned id,
1010 * Query GPU H/w Info
1012 * Query hardware specific information
1014 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
1015 * \param heap - \c [in] Heap type
1016 * \param info - \c [in] Pointer to structure to get needed information
1018 * \return 0 on success\n
1019 * <0 - Negative POSIX Error code
1022 int amdgpu_query_gpu_info(amdgpu_device_handle dev,
1023 struct amdgpu_gpu_info *info);
1026 * Query hardware or driver information.
1028 * The return size is query-specific and depends on the "info_id" parameter.
1029 * No more than "size" bytes is returned.
1031 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
1032 * \param info_id - \c [in] AMDGPU_INFO_*
1033 * \param size - \c [in] Size of the returned value.
1034 * \param value - \c [out] Pointer to the return value.
1036 * \return 0 on success\n
1037 * <0 - Negative POSIX error code
1040 int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id,
1041 unsigned size, void *value);
1044 * Query information about GDS
1046 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
1047 * \param gds_info - \c [out] Pointer to structure to get GDS information
1049 * \return 0 on success\n
1050 * <0 - Negative POSIX Error code
1053 int amdgpu_query_gds_info(amdgpu_device_handle dev,
1054 struct amdgpu_gds_resource_info *gds_info);
1057 * Read a set of consecutive memory-mapped registers.
1058 * Not all registers are allowed to be read by userspace.
1060 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize(
1061 * \param dword_offset - \c [in] Register offset in dwords
1062 * \param count - \c [in] The number of registers to read starting
1064 * \param instance - \c [in] GRBM_GFX_INDEX selector. It may have other
1065 * uses. Set it to 0xffffffff if unsure.
1066 * \param flags - \c [in] Flags with additional information.
1067 * \param values - \c [out] The pointer to return values.
1069 * \return 0 on success\n
1070 * <0 - Negative POSIX error code
1073 int amdgpu_read_mm_registers(amdgpu_device_handle dev, unsigned dword_offset,
1074 unsigned count, uint32_t instance, uint32_t flags,
1078 * Allocate virtual address range
1080 * \param dev - [in] Device handle. See #amdgpu_device_initialize()
1081 * \param va_range_type - \c [in] Type of MC va range from which to allocate
1082 * \param size - \c [in] Size of range. Size must be correctly* aligned.
1083 * It is client responsibility to correctly aligned size based on the future
1084 * usage of allocated range.
1085 * \param va_base_alignment - \c [in] Overwrite base address alignment
1086 * requirement for GPU VM MC virtual
1087 * address assignment. Must be multiple of size alignments received as
1088 * 'amdgpu_buffer_size_alignments'.
1089 * If 0 use the default one.
1090 * \param va_base_required - \c [in] Specified required va base address.
1091 * If 0 then library choose available one.
1092 * If !0 value will be passed and those value already "in use" then
1093 * corresponding error status will be returned.
1094 * \param va_base_allocated - \c [out] On return: Allocated VA base to be used
1096 * \param va_range_handle - \c [out] On return: Handle assigned to allocation
1097 * \param flags - \c [in] flags for special VA range
1099 * \return 0 on success\n
1100 * >0 - AMD specific error code\n
1101 * <0 - Negative POSIX Error code
1104 * It is client responsibility to correctly handle VA assignments and usage.
1105 * Neither kernel driver nor libdrm_amdpgu are able to prevent and
1106 * detect wrong va assignemnt.
1108 * It is client responsibility to correctly handle multi-GPU cases and to pass
1109 * the corresponding arrays of all devices handles where corresponding VA will
1113 int amdgpu_va_range_alloc(amdgpu_device_handle dev,
1114 enum amdgpu_gpu_va_range va_range_type,
1116 uint64_t va_base_alignment,
1117 uint64_t va_base_required,
1118 uint64_t *va_base_allocated,
1119 amdgpu_va_handle *va_range_handle,
1123 * Free previously allocated virtual address range
1126 * \param va_range_handle - \c [in] Handle assigned to VA allocation
1128 * \return 0 on success\n
1129 * >0 - AMD specific error code\n
1130 * <0 - Negative POSIX Error code
1133 int amdgpu_va_range_free(amdgpu_va_handle va_range_handle);
1136 * Query virtual address range
1138 * UMD can query GPU VM range supported by each device
1139 * to initialize its own VAM accordingly.
1141 * \param dev - [in] Device handle. See #amdgpu_device_initialize()
1142 * \param type - \c [in] Type of virtual address range
1143 * \param offset - \c [out] Start offset of virtual address range
1144 * \param size - \c [out] Size of virtual address range
1146 * \return 0 on success\n
1147 * <0 - Negative POSIX Error code
1151 int amdgpu_va_range_query(amdgpu_device_handle dev,
1152 enum amdgpu_gpu_va_range type,
1157 * VA mapping/unmapping for the buffer object
1159 * \param bo - \c [in] BO handle
1160 * \param offset - \c [in] Start offset to map
1161 * \param size - \c [in] Size to map
1162 * \param addr - \c [in] Start virtual address.
1163 * \param flags - \c [in] Supported flags for mapping/unmapping
1164 * \param ops - \c [in] AMDGPU_VA_OP_MAP or AMDGPU_VA_OP_UNMAP
1166 * \return 0 on success\n
1167 * <0 - Negative POSIX Error code
1171 int amdgpu_bo_va_op(amdgpu_bo_handle bo,
1178 #endif /* #ifdef _AMDGPU_H_ */