2 * Copyright © 2014 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
32 #include <sys/ioctl.h>
36 #include "libdrm_macros.h"
38 #include "amdgpu_drm.h"
39 #include "amdgpu_internal.h"
40 #include "util_math.h"
42 static void amdgpu_close_kms_handle(amdgpu_device_handle dev,
45 struct drm_gem_close args = {};
48 drmIoctl(dev->fd, DRM_IOCTL_GEM_CLOSE, &args);
51 static int amdgpu_bo_create(amdgpu_device_handle dev,
54 amdgpu_bo_handle *buf_handle)
58 bo = calloc(1, sizeof(struct amdgpu_bo));
62 atomic_set(&bo->refcount, 1);
64 bo->alloc_size = size;
66 pthread_mutex_init(&bo->cpu_access_mutex, NULL);
72 int amdgpu_bo_alloc(amdgpu_device_handle dev,
73 struct amdgpu_bo_alloc_request *alloc_buffer,
74 amdgpu_bo_handle *buf_handle)
76 union drm_amdgpu_gem_create args;
77 unsigned heap = alloc_buffer->preferred_heap;
80 /* It's an error if the heap is not specified */
81 if (!(heap & (AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM)))
84 memset(&args, 0, sizeof(args));
85 args.in.bo_size = alloc_buffer->alloc_size;
86 args.in.alignment = alloc_buffer->phys_alignment;
88 /* Set the placement. */
89 args.in.domains = heap;
90 args.in.domain_flags = alloc_buffer->flags;
92 /* Allocate the buffer with the preferred heap. */
93 r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_CREATE,
98 r = amdgpu_bo_create(dev, alloc_buffer->alloc_size, args.out.handle,
101 amdgpu_close_kms_handle(dev, args.out.handle);
105 pthread_mutex_lock(&dev->bo_table_mutex);
106 r = handle_table_insert(&dev->bo_handles, (*buf_handle)->handle,
108 pthread_mutex_unlock(&dev->bo_table_mutex);
110 amdgpu_bo_free(*buf_handle);
115 int amdgpu_bo_set_metadata(amdgpu_bo_handle bo,
116 struct amdgpu_bo_metadata *info)
118 struct drm_amdgpu_gem_metadata args = {};
120 args.handle = bo->handle;
121 args.op = AMDGPU_GEM_METADATA_OP_SET_METADATA;
122 args.data.flags = info->flags;
123 args.data.tiling_info = info->tiling_info;
125 if (info->size_metadata > sizeof(args.data.data))
128 if (info->size_metadata) {
129 args.data.data_size_bytes = info->size_metadata;
130 memcpy(args.data.data, info->umd_metadata, info->size_metadata);
133 return drmCommandWriteRead(bo->dev->fd,
134 DRM_AMDGPU_GEM_METADATA,
135 &args, sizeof(args));
138 int amdgpu_bo_query_info(amdgpu_bo_handle bo,
139 struct amdgpu_bo_info *info)
141 struct drm_amdgpu_gem_metadata metadata = {};
142 struct drm_amdgpu_gem_create_in bo_info = {};
143 struct drm_amdgpu_gem_op gem_op = {};
146 /* Validate the BO passed in */
150 /* Query metadata. */
151 metadata.handle = bo->handle;
152 metadata.op = AMDGPU_GEM_METADATA_OP_GET_METADATA;
154 r = drmCommandWriteRead(bo->dev->fd, DRM_AMDGPU_GEM_METADATA,
155 &metadata, sizeof(metadata));
159 if (metadata.data.data_size_bytes >
160 sizeof(info->metadata.umd_metadata))
163 /* Query buffer info. */
164 gem_op.handle = bo->handle;
165 gem_op.op = AMDGPU_GEM_OP_GET_GEM_CREATE_INFO;
166 gem_op.value = (uintptr_t)&bo_info;
168 r = drmCommandWriteRead(bo->dev->fd, DRM_AMDGPU_GEM_OP,
169 &gem_op, sizeof(gem_op));
173 memset(info, 0, sizeof(*info));
174 info->alloc_size = bo_info.bo_size;
175 info->phys_alignment = bo_info.alignment;
176 info->preferred_heap = bo_info.domains;
177 info->alloc_flags = bo_info.domain_flags;
178 info->metadata.flags = metadata.data.flags;
179 info->metadata.tiling_info = metadata.data.tiling_info;
181 info->metadata.size_metadata = metadata.data.data_size_bytes;
182 if (metadata.data.data_size_bytes > 0)
183 memcpy(info->metadata.umd_metadata, metadata.data.data,
184 metadata.data.data_size_bytes);
189 static int amdgpu_bo_export_flink(amdgpu_bo_handle bo)
191 struct drm_gem_flink flink;
202 if (bo->dev->flink_fd != bo->dev->fd) {
203 r = drmPrimeHandleToFD(bo->dev->fd, bo->handle, DRM_CLOEXEC,
206 r = drmPrimeFDToHandle(bo->dev->flink_fd, dma_fd, &handle);
211 fd = bo->dev->flink_fd;
213 memset(&flink, 0, sizeof(flink));
214 flink.handle = handle;
216 r = drmIoctl(fd, DRM_IOCTL_GEM_FLINK, &flink);
220 bo->flink_name = flink.name;
222 if (bo->dev->flink_fd != bo->dev->fd) {
223 struct drm_gem_close args = {};
224 args.handle = handle;
225 drmIoctl(bo->dev->flink_fd, DRM_IOCTL_GEM_CLOSE, &args);
228 pthread_mutex_lock(&bo->dev->bo_table_mutex);
229 r = handle_table_insert(&bo->dev->bo_flink_names, bo->flink_name, bo);
230 pthread_mutex_unlock(&bo->dev->bo_table_mutex);
235 int amdgpu_bo_export(amdgpu_bo_handle bo,
236 enum amdgpu_bo_handle_type type,
237 uint32_t *shared_handle)
242 case amdgpu_bo_handle_type_gem_flink_name:
243 r = amdgpu_bo_export_flink(bo);
247 *shared_handle = bo->flink_name;
250 case amdgpu_bo_handle_type_kms:
251 case amdgpu_bo_handle_type_kms_noimport:
252 *shared_handle = bo->handle;
255 case amdgpu_bo_handle_type_dma_buf_fd:
256 return drmPrimeHandleToFD(bo->dev->fd, bo->handle,
257 DRM_CLOEXEC | DRM_RDWR,
258 (int*)shared_handle);
263 int amdgpu_bo_import(amdgpu_device_handle dev,
264 enum amdgpu_bo_handle_type type,
265 uint32_t shared_handle,
266 struct amdgpu_bo_import_result *output)
268 struct drm_gem_open open_arg = {};
269 struct drm_gem_close close_arg = {};
270 struct amdgpu_bo *bo = NULL;
271 uint32_t handle = 0, flink_name = 0;
272 uint64_t alloc_size = 0;
275 uint64_t dma_buf_size = 0;
277 /* We must maintain a list of pairs <handle, bo>, so that we always
278 * return the same amdgpu_bo instance for the same handle. */
279 pthread_mutex_lock(&dev->bo_table_mutex);
281 /* Convert a DMA buf handle to a KMS handle now. */
282 if (type == amdgpu_bo_handle_type_dma_buf_fd) {
285 /* Get a KMS handle. */
286 r = drmPrimeFDToHandle(dev->fd, shared_handle, &handle);
290 /* Query the buffer size. */
291 size = lseek(shared_handle, 0, SEEK_END);
292 if (size == (off_t)-1) {
296 lseek(shared_handle, 0, SEEK_SET);
299 shared_handle = handle;
302 /* If we have already created a buffer with this handle, find it. */
304 case amdgpu_bo_handle_type_gem_flink_name:
305 bo = handle_table_lookup(&dev->bo_flink_names, shared_handle);
308 case amdgpu_bo_handle_type_dma_buf_fd:
309 bo = handle_table_lookup(&dev->bo_handles, shared_handle);
312 case amdgpu_bo_handle_type_kms:
313 case amdgpu_bo_handle_type_kms_noimport:
314 /* Importing a KMS handle in not allowed. */
324 /* The buffer already exists, just bump the refcount. */
325 atomic_inc(&bo->refcount);
326 pthread_mutex_unlock(&dev->bo_table_mutex);
328 output->buf_handle = bo;
329 output->alloc_size = bo->alloc_size;
333 /* Open the handle. */
335 case amdgpu_bo_handle_type_gem_flink_name:
336 open_arg.name = shared_handle;
337 r = drmIoctl(dev->flink_fd, DRM_IOCTL_GEM_OPEN, &open_arg);
341 flink_name = shared_handle;
342 handle = open_arg.handle;
343 alloc_size = open_arg.size;
344 if (dev->flink_fd != dev->fd) {
345 r = drmPrimeHandleToFD(dev->flink_fd, handle,
346 DRM_CLOEXEC, &dma_fd);
349 r = drmPrimeFDToHandle(dev->fd, dma_fd, &handle);
353 close_arg.handle = open_arg.handle;
354 r = drmIoctl(dev->flink_fd, DRM_IOCTL_GEM_CLOSE,
361 case amdgpu_bo_handle_type_dma_buf_fd:
362 handle = shared_handle;
363 alloc_size = dma_buf_size;
366 case amdgpu_bo_handle_type_kms:
367 case amdgpu_bo_handle_type_kms_noimport:
368 assert(0); /* unreachable */
372 r = amdgpu_bo_create(dev, alloc_size, handle, &bo);
376 r = handle_table_insert(&dev->bo_handles, bo->handle, bo);
380 bo->flink_name = flink_name;
381 r = handle_table_insert(&dev->bo_flink_names, flink_name,
388 output->buf_handle = bo;
389 output->alloc_size = bo->alloc_size;
390 pthread_mutex_unlock(&dev->bo_table_mutex);
394 handle_table_remove(&dev->bo_handles, bo->handle);
396 if (flink_name && !close_arg.handle && open_arg.handle) {
397 close_arg.handle = open_arg.handle;
398 drmIoctl(dev->flink_fd, DRM_IOCTL_GEM_CLOSE, &close_arg);
403 amdgpu_close_kms_handle(dev, handle);
405 pthread_mutex_unlock(&dev->bo_table_mutex);
409 int amdgpu_bo_free(amdgpu_bo_handle buf_handle)
411 struct amdgpu_device *dev;
412 struct amdgpu_bo *bo = buf_handle;
416 pthread_mutex_lock(&dev->bo_table_mutex);
418 if (update_references(&bo->refcount, NULL)) {
419 /* Remove the buffer from the hash tables. */
420 handle_table_remove(&dev->bo_handles, bo->handle);
423 handle_table_remove(&dev->bo_flink_names,
426 /* Release CPU access. */
427 if (bo->cpu_map_count > 0) {
428 bo->cpu_map_count = 1;
429 amdgpu_bo_cpu_unmap(bo);
432 amdgpu_close_kms_handle(dev, bo->handle);
433 pthread_mutex_destroy(&bo->cpu_access_mutex);
437 pthread_mutex_unlock(&dev->bo_table_mutex);
441 int amdgpu_bo_inc_ref(amdgpu_bo_handle bo)
443 atomic_inc(&bo->refcount);
447 int amdgpu_bo_cpu_map(amdgpu_bo_handle bo, void **cpu)
449 union drm_amdgpu_gem_mmap args;
453 pthread_mutex_lock(&bo->cpu_access_mutex);
457 assert(bo->cpu_map_count > 0);
460 pthread_mutex_unlock(&bo->cpu_access_mutex);
464 assert(bo->cpu_map_count == 0);
466 memset(&args, 0, sizeof(args));
468 /* Query the buffer address (args.addr_ptr).
469 * The kernel driver ignores the offset and size parameters. */
470 args.in.handle = bo->handle;
472 r = drmCommandWriteRead(bo->dev->fd, DRM_AMDGPU_GEM_MMAP, &args,
475 pthread_mutex_unlock(&bo->cpu_access_mutex);
479 /* Map the buffer. */
480 ptr = drm_mmap(NULL, bo->alloc_size, PROT_READ | PROT_WRITE, MAP_SHARED,
481 bo->dev->fd, args.out.addr_ptr);
482 if (ptr == MAP_FAILED) {
483 pthread_mutex_unlock(&bo->cpu_access_mutex);
488 bo->cpu_map_count = 1;
489 pthread_mutex_unlock(&bo->cpu_access_mutex);
495 int amdgpu_bo_cpu_unmap(amdgpu_bo_handle bo)
499 pthread_mutex_lock(&bo->cpu_access_mutex);
500 assert(bo->cpu_map_count >= 0);
502 if (bo->cpu_map_count == 0) {
504 pthread_mutex_unlock(&bo->cpu_access_mutex);
509 if (bo->cpu_map_count > 0) {
510 /* mapped multiple times */
511 pthread_mutex_unlock(&bo->cpu_access_mutex);
515 r = drm_munmap(bo->cpu_ptr, bo->alloc_size) == 0 ? 0 : -errno;
517 pthread_mutex_unlock(&bo->cpu_access_mutex);
521 int amdgpu_query_buffer_size_alignment(amdgpu_device_handle dev,
522 struct amdgpu_buffer_size_alignments *info)
524 info->size_local = dev->dev_info.pte_fragment_size;
525 info->size_remote = dev->dev_info.gart_page_size;
529 int amdgpu_bo_wait_for_idle(amdgpu_bo_handle bo,
533 union drm_amdgpu_gem_wait_idle args;
536 memset(&args, 0, sizeof(args));
537 args.in.handle = bo->handle;
538 args.in.timeout = amdgpu_cs_calculate_timeout(timeout_ns);
540 r = drmCommandWriteRead(bo->dev->fd, DRM_AMDGPU_GEM_WAIT_IDLE,
541 &args, sizeof(args));
544 *busy = args.out.status;
547 fprintf(stderr, "amdgpu: GEM_WAIT_IDLE failed with %i\n", r);
552 int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev,
555 amdgpu_bo_handle *buf_handle,
556 uint64_t *offset_in_bo)
558 struct amdgpu_bo *bo;
562 if (cpu == NULL || size == 0)
566 * Workaround for a buggy application which tries to import previously
567 * exposed CPU pointers. If we find a real world use case we should
568 * improve that by asking the kernel for the right handle.
570 pthread_mutex_lock(&dev->bo_table_mutex);
571 for (i = 0; i < dev->bo_handles.max_key; i++) {
572 bo = handle_table_lookup(&dev->bo_handles, i);
573 if (!bo || !bo->cpu_ptr || size > bo->alloc_size)
575 if (cpu >= bo->cpu_ptr &&
576 cpu < (void*)((uintptr_t)bo->cpu_ptr + bo->alloc_size))
580 if (i < dev->bo_handles.max_key) {
581 atomic_inc(&bo->refcount);
583 *offset_in_bo = (uintptr_t)cpu - (uintptr_t)bo->cpu_ptr;
589 pthread_mutex_unlock(&dev->bo_table_mutex);
594 int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev,
597 amdgpu_bo_handle *buf_handle)
600 struct drm_amdgpu_gem_userptr args;
602 args.addr = (uintptr_t)cpu;
603 args.flags = AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_REGISTER |
604 AMDGPU_GEM_USERPTR_VALIDATE;
606 r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_USERPTR,
607 &args, sizeof(args));
611 r = amdgpu_bo_create(dev, size, args.handle, buf_handle);
613 amdgpu_close_kms_handle(dev, args.handle);
617 pthread_mutex_lock(&dev->bo_table_mutex);
618 r = handle_table_insert(&dev->bo_handles, (*buf_handle)->handle,
620 pthread_mutex_unlock(&dev->bo_table_mutex);
622 amdgpu_bo_free(*buf_handle);
627 int amdgpu_bo_list_create(amdgpu_device_handle dev,
628 uint32_t number_of_resources,
629 amdgpu_bo_handle *resources,
630 uint8_t *resource_prios,
631 amdgpu_bo_list_handle *result)
633 struct drm_amdgpu_bo_list_entry *list;
634 union drm_amdgpu_bo_list args;
638 if (!number_of_resources)
641 /* overflow check for multiplication */
642 if (number_of_resources > UINT32_MAX / sizeof(struct drm_amdgpu_bo_list_entry))
645 list = malloc(number_of_resources * sizeof(struct drm_amdgpu_bo_list_entry));
649 *result = malloc(sizeof(struct amdgpu_bo_list));
655 memset(&args, 0, sizeof(args));
656 args.in.operation = AMDGPU_BO_LIST_OP_CREATE;
657 args.in.bo_number = number_of_resources;
658 args.in.bo_info_size = sizeof(struct drm_amdgpu_bo_list_entry);
659 args.in.bo_info_ptr = (uint64_t)(uintptr_t)list;
661 for (i = 0; i < number_of_resources; i++) {
662 list[i].bo_handle = resources[i]->handle;
664 list[i].bo_priority = resource_prios[i];
666 list[i].bo_priority = 0;
669 r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_BO_LIST,
670 &args, sizeof(args));
677 (*result)->dev = dev;
678 (*result)->handle = args.out.list_handle;
682 int amdgpu_bo_list_destroy(amdgpu_bo_list_handle list)
684 union drm_amdgpu_bo_list args;
687 memset(&args, 0, sizeof(args));
688 args.in.operation = AMDGPU_BO_LIST_OP_DESTROY;
689 args.in.list_handle = list->handle;
691 r = drmCommandWriteRead(list->dev->fd, DRM_AMDGPU_BO_LIST,
692 &args, sizeof(args));
700 int amdgpu_bo_list_update(amdgpu_bo_list_handle handle,
701 uint32_t number_of_resources,
702 amdgpu_bo_handle *resources,
703 uint8_t *resource_prios)
705 struct drm_amdgpu_bo_list_entry *list;
706 union drm_amdgpu_bo_list args;
710 if (!number_of_resources)
713 /* overflow check for multiplication */
714 if (number_of_resources > UINT32_MAX / sizeof(struct drm_amdgpu_bo_list_entry))
717 list = malloc(number_of_resources * sizeof(struct drm_amdgpu_bo_list_entry));
721 args.in.operation = AMDGPU_BO_LIST_OP_UPDATE;
722 args.in.list_handle = handle->handle;
723 args.in.bo_number = number_of_resources;
724 args.in.bo_info_size = sizeof(struct drm_amdgpu_bo_list_entry);
725 args.in.bo_info_ptr = (uintptr_t)list;
727 for (i = 0; i < number_of_resources; i++) {
728 list[i].bo_handle = resources[i]->handle;
730 list[i].bo_priority = resource_prios[i];
732 list[i].bo_priority = 0;
735 r = drmCommandWriteRead(handle->dev->fd, DRM_AMDGPU_BO_LIST,
736 &args, sizeof(args));
741 int amdgpu_bo_va_op(amdgpu_bo_handle bo,
748 amdgpu_device_handle dev = bo->dev;
750 size = ALIGN(size, getpagesize());
752 return amdgpu_bo_va_op_raw(dev, bo, offset, size, addr,
753 AMDGPU_VM_PAGE_READABLE |
754 AMDGPU_VM_PAGE_WRITEABLE |
755 AMDGPU_VM_PAGE_EXECUTABLE, ops);
758 int amdgpu_bo_va_op_raw(amdgpu_device_handle dev,
766 struct drm_amdgpu_gem_va va;
769 if (ops != AMDGPU_VA_OP_MAP && ops != AMDGPU_VA_OP_UNMAP &&
770 ops != AMDGPU_VA_OP_REPLACE && ops != AMDGPU_VA_OP_CLEAR)
773 memset(&va, 0, sizeof(va));
774 va.handle = bo ? bo->handle : 0;
777 va.va_address = addr;
778 va.offset_in_bo = offset;
781 r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_VA, &va, sizeof(va));