1 /**************************************************************************
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007-2012 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 **************************************************************************/
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
42 #include <xf86atomic.h>
50 #include <sys/ioctl.h>
52 #include <sys/types.h>
57 #define ETIME ETIMEDOUT
59 #include "libdrm_macros.h"
60 #include "libdrm_lists.h"
61 #include "intel_bufmgr.h"
62 #include "intel_bufmgr_priv.h"
63 #include "intel_chipset.h"
77 #define memclear(s) memset(&s, 0, sizeof(s))
79 #define DBG(...) do { \
80 if (bufmgr_gem->bufmgr.debug) \
81 fprintf(stderr, __VA_ARGS__); \
84 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
85 #define MAX2(A, B) ((A) > (B) ? (A) : (B))
88 * upper_32_bits - return bits 32-63 of a number
89 * @n: the number we're accessing
91 * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress
92 * the "right shift count >= width of type" warning when that quantity is
95 #define upper_32_bits(n) ((__u32)(((n) >> 16) >> 16))
98 * lower_32_bits - return bits 0-31 of a number
99 * @n: the number we're accessing
101 #define lower_32_bits(n) ((__u32)(n))
103 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
105 struct drm_intel_gem_bo_bucket {
110 typedef struct _drm_intel_bufmgr_gem {
111 drm_intel_bufmgr bufmgr;
119 pthread_mutex_t lock;
121 struct drm_i915_gem_exec_object *exec_objects;
122 struct drm_i915_gem_exec_object2 *exec2_objects;
123 drm_intel_bo **exec_bos;
127 /** Array of lists of cached gem objects of power-of-two sizes */
128 struct drm_intel_gem_bo_bucket cache_bucket[14 * 4];
132 drmMMListHead managers;
134 drm_intel_bo_gem *name_table;
135 drm_intel_bo_gem *handle_table;
137 drmMMListHead vma_cache;
138 int vma_count, vma_open, vma_max;
141 int available_fences;
144 unsigned int has_bsd : 1;
145 unsigned int has_blt : 1;
146 unsigned int has_relaxed_fencing : 1;
147 unsigned int has_llc : 1;
148 unsigned int has_wait_timeout : 1;
149 unsigned int bo_reuse : 1;
150 unsigned int no_exec : 1;
151 unsigned int has_vebox : 1;
152 unsigned int has_exec_async : 1;
160 } drm_intel_bufmgr_gem;
162 #define DRM_INTEL_RELOC_FENCE (1<<0)
164 typedef struct _drm_intel_reloc_target_info {
167 } drm_intel_reloc_target;
169 struct _drm_intel_bo_gem {
177 * Kenel-assigned global name for this object
179 * List contains both flink named and prime fd'd objects
181 unsigned int global_name;
183 UT_hash_handle handle_hh;
184 UT_hash_handle name_hh;
187 * Index of the buffer within the validation list while preparing a
188 * batchbuffer execution.
193 * Current tiling mode
195 uint32_t tiling_mode;
196 uint32_t swizzle_mode;
197 unsigned long stride;
199 unsigned long kflags;
203 /** Array passed to the DRM containing relocation information. */
204 struct drm_i915_gem_relocation_entry *relocs;
206 * Array of info structs corresponding to relocs[i].target_handle etc
208 drm_intel_reloc_target *reloc_target_info;
209 /** Number of entries in relocs */
211 /** Array of BOs that are referenced by this buffer and will be softpinned */
212 drm_intel_bo **softpin_target;
213 /** Number softpinned BOs that are referenced by this buffer */
214 int softpin_target_count;
215 /** Maximum amount of softpinned BOs that are referenced by this buffer */
216 int softpin_target_size;
218 /** Mapped address for the buffer, saved across map/unmap cycles */
220 /** GTT virtual address for the buffer, saved across map/unmap cycles */
222 /** WC CPU address for the buffer, saved across map/unmap cycles */
225 * Virtual address of the buffer allocated by user, used for userptr
230 drmMMListHead vma_list;
236 * Boolean of whether this BO and its children have been included in
237 * the current drm_intel_bufmgr_check_aperture_space() total.
239 bool included_in_check_aperture;
242 * Boolean of whether this buffer has been used as a relocation
243 * target and had its size accounted for, and thus can't have any
244 * further relocations added to it.
246 bool used_as_reloc_target;
249 * Boolean of whether we have encountered an error whilst building the relocation tree.
254 * Boolean of whether this buffer can be re-used
259 * Boolean of whether the GPU is definitely not accessing the buffer.
261 * This is only valid when reusable, since non-reusable
262 * buffers are those that have been shared with other
263 * processes, so we don't know their state.
268 * Boolean of whether this buffer was allocated with userptr
273 * Size in bytes of this buffer and its relocation descendents.
275 * Used to avoid costly tree walking in
276 * drm_intel_bufmgr_check_aperture in the common case.
281 * Number of potential fence registers required by this buffer and its
284 int reloc_tree_fences;
286 /** Flags that we may need to do the SW_FINISH ioctl on unmap. */
287 bool mapped_cpu_write;
291 drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count);
294 drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count);
297 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
298 uint32_t * swizzle_mode);
301 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
302 uint32_t tiling_mode,
305 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
308 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo);
310 static void drm_intel_gem_bo_free(drm_intel_bo *bo);
312 static inline drm_intel_bo_gem *to_bo_gem(drm_intel_bo *bo)
314 return (drm_intel_bo_gem *)bo;
318 drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
319 uint32_t *tiling_mode)
321 unsigned long min_size, max_size;
324 if (*tiling_mode == I915_TILING_NONE)
327 /* 965+ just need multiples of page size for tiling */
328 if (bufmgr_gem->gen >= 4)
329 return ROUND_UP_TO(size, 4096);
331 /* Older chips need powers of two, of at least 512k or 1M */
332 if (bufmgr_gem->gen == 3) {
333 min_size = 1024*1024;
334 max_size = 128*1024*1024;
337 max_size = 64*1024*1024;
340 if (size > max_size) {
341 *tiling_mode = I915_TILING_NONE;
345 /* Do we need to allocate every page for the fence? */
346 if (bufmgr_gem->has_relaxed_fencing)
347 return ROUND_UP_TO(size, 4096);
349 for (i = min_size; i < size; i <<= 1)
356 * Round a given pitch up to the minimum required for X tiling on a
357 * given chip. We use 512 as the minimum to allow for a later tiling
361 drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
362 unsigned long pitch, uint32_t *tiling_mode)
364 unsigned long tile_width;
367 /* If untiled, then just align it so that we can do rendering
368 * to it with the 3D engine.
370 if (*tiling_mode == I915_TILING_NONE)
371 return ALIGN(pitch, 64);
373 if (*tiling_mode == I915_TILING_X
374 || (IS_915(bufmgr_gem->pci_device)
375 && *tiling_mode == I915_TILING_Y))
380 /* 965 is flexible */
381 if (bufmgr_gem->gen >= 4)
382 return ROUND_UP_TO(pitch, tile_width);
384 /* The older hardware has a maximum pitch of 8192 with tiled
385 * surfaces, so fallback to untiled if it's too large.
388 *tiling_mode = I915_TILING_NONE;
389 return ALIGN(pitch, 64);
392 /* Pre-965 needs power of two tile width */
393 for (i = tile_width; i < pitch; i <<= 1)
399 static struct drm_intel_gem_bo_bucket *
400 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
405 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
406 struct drm_intel_gem_bo_bucket *bucket =
407 &bufmgr_gem->cache_bucket[i];
408 if (bucket->size >= size) {
417 drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
421 for (i = 0; i < bufmgr_gem->exec_count; i++) {
422 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
423 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
425 if (bo_gem->relocs == NULL && bo_gem->softpin_target == NULL) {
426 DBG("%2d: %d %s(%s)\n", i, bo_gem->gem_handle,
427 bo_gem->kflags & EXEC_OBJECT_PINNED ? "*" : "",
432 for (j = 0; j < bo_gem->reloc_count; j++) {
433 drm_intel_bo *target_bo = bo_gem->reloc_target_info[j].bo;
434 drm_intel_bo_gem *target_gem =
435 (drm_intel_bo_gem *) target_bo;
437 DBG("%2d: %d %s(%s)@0x%08x %08x -> "
438 "%d (%s)@0x%08x %08x + 0x%08x\n",
441 bo_gem->kflags & EXEC_OBJECT_PINNED ? "*" : "",
443 upper_32_bits(bo_gem->relocs[j].offset),
444 lower_32_bits(bo_gem->relocs[j].offset),
445 target_gem->gem_handle,
447 upper_32_bits(target_bo->offset64),
448 lower_32_bits(target_bo->offset64),
449 bo_gem->relocs[j].delta);
452 for (j = 0; j < bo_gem->softpin_target_count; j++) {
453 drm_intel_bo *target_bo = bo_gem->softpin_target[j];
454 drm_intel_bo_gem *target_gem =
455 (drm_intel_bo_gem *) target_bo;
456 DBG("%2d: %d %s(%s) -> "
457 "%d *(%s)@0x%08x %08x\n",
460 bo_gem->kflags & EXEC_OBJECT_PINNED ? "*" : "",
462 target_gem->gem_handle,
464 upper_32_bits(target_bo->offset64),
465 lower_32_bits(target_bo->offset64));
471 drm_intel_gem_bo_reference(drm_intel_bo *bo)
473 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
475 atomic_inc(&bo_gem->refcount);
479 * Adds the given buffer to the list of buffers to be validated (moved into the
480 * appropriate memory type) with the next batch submission.
482 * If a buffer is validated multiple times in a batch submission, it ends up
483 * with the intersection of the memory type flags and the union of the
487 drm_intel_add_validate_buffer(drm_intel_bo *bo)
489 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
490 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
493 if (bo_gem->validate_index != -1)
496 /* Extend the array of validation entries as necessary. */
497 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
498 int new_size = bufmgr_gem->exec_size * 2;
503 bufmgr_gem->exec_objects =
504 realloc(bufmgr_gem->exec_objects,
505 sizeof(*bufmgr_gem->exec_objects) * new_size);
506 bufmgr_gem->exec_bos =
507 realloc(bufmgr_gem->exec_bos,
508 sizeof(*bufmgr_gem->exec_bos) * new_size);
509 bufmgr_gem->exec_size = new_size;
512 index = bufmgr_gem->exec_count;
513 bo_gem->validate_index = index;
514 /* Fill in array entry */
515 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
516 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
517 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs;
518 bufmgr_gem->exec_objects[index].alignment = bo->align;
519 bufmgr_gem->exec_objects[index].offset = 0;
520 bufmgr_gem->exec_bos[index] = bo;
521 bufmgr_gem->exec_count++;
525 drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence)
527 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
528 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
534 flags |= EXEC_OBJECT_NEEDS_FENCE;
536 if (bo_gem->validate_index != -1) {
537 bufmgr_gem->exec2_objects[bo_gem->validate_index].flags |= flags;
541 /* Extend the array of validation entries as necessary. */
542 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
543 int new_size = bufmgr_gem->exec_size * 2;
548 bufmgr_gem->exec2_objects =
549 realloc(bufmgr_gem->exec2_objects,
550 sizeof(*bufmgr_gem->exec2_objects) * new_size);
551 bufmgr_gem->exec_bos =
552 realloc(bufmgr_gem->exec_bos,
553 sizeof(*bufmgr_gem->exec_bos) * new_size);
554 bufmgr_gem->exec_size = new_size;
557 index = bufmgr_gem->exec_count;
558 bo_gem->validate_index = index;
559 /* Fill in array entry */
560 bufmgr_gem->exec2_objects[index].handle = bo_gem->gem_handle;
561 bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count;
562 bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
563 bufmgr_gem->exec2_objects[index].alignment = bo->align;
564 bufmgr_gem->exec2_objects[index].offset = bo->offset64;
565 bufmgr_gem->exec2_objects[index].flags = bo_gem->kflags | flags;
566 bufmgr_gem->exec2_objects[index].rsvd1 = 0;
567 bufmgr_gem->exec2_objects[index].rsvd2 = 0;
568 bufmgr_gem->exec_bos[index] = bo;
569 bufmgr_gem->exec_count++;
572 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
576 drm_intel_bo_gem_set_in_aperture_size(drm_intel_bufmgr_gem *bufmgr_gem,
577 drm_intel_bo_gem *bo_gem,
578 unsigned int alignment)
582 assert(!bo_gem->used_as_reloc_target);
584 /* The older chipsets are far-less flexible in terms of tiling,
585 * and require tiled buffer to be size aligned in the aperture.
586 * This means that in the worst possible case we will need a hole
587 * twice as large as the object in order for it to fit into the
588 * aperture. Optimal packing is for wimps.
590 size = bo_gem->bo.size;
591 if (bufmgr_gem->gen < 4 && bo_gem->tiling_mode != I915_TILING_NONE) {
592 unsigned int min_size;
594 if (bufmgr_gem->has_relaxed_fencing) {
595 if (bufmgr_gem->gen == 3)
596 min_size = 1024*1024;
600 while (min_size < size)
605 /* Account for worst-case alignment. */
606 alignment = MAX2(alignment, min_size);
609 bo_gem->reloc_tree_size = size + alignment;
613 drm_intel_setup_reloc_list(drm_intel_bo *bo)
615 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
616 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
617 unsigned int max_relocs = bufmgr_gem->max_relocs;
619 if (bo->size / 4 < max_relocs)
620 max_relocs = bo->size / 4;
622 bo_gem->relocs = malloc(max_relocs *
623 sizeof(struct drm_i915_gem_relocation_entry));
624 bo_gem->reloc_target_info = malloc(max_relocs *
625 sizeof(drm_intel_reloc_target));
626 if (bo_gem->relocs == NULL || bo_gem->reloc_target_info == NULL) {
627 bo_gem->has_error = true;
629 free (bo_gem->relocs);
630 bo_gem->relocs = NULL;
632 free (bo_gem->reloc_target_info);
633 bo_gem->reloc_target_info = NULL;
642 drm_intel_gem_bo_busy(drm_intel_bo *bo)
644 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
645 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
646 struct drm_i915_gem_busy busy;
649 if (bo_gem->reusable && bo_gem->idle)
653 busy.handle = bo_gem->gem_handle;
655 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
657 bo_gem->idle = !busy.busy;
665 drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem,
666 drm_intel_bo_gem *bo_gem, int state)
668 struct drm_i915_gem_madvise madv;
671 madv.handle = bo_gem->gem_handle;
674 drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
676 return madv.retained;
680 drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
682 return drm_intel_gem_bo_madvise_internal
683 ((drm_intel_bufmgr_gem *) bo->bufmgr,
684 (drm_intel_bo_gem *) bo,
688 /* drop the oldest entries that have been purged by the kernel */
690 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
691 struct drm_intel_gem_bo_bucket *bucket)
693 while (!DRMLISTEMPTY(&bucket->head)) {
694 drm_intel_bo_gem *bo_gem;
696 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
697 bucket->head.next, head);
698 if (drm_intel_gem_bo_madvise_internal
699 (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
702 DRMLISTDEL(&bo_gem->head);
703 drm_intel_gem_bo_free(&bo_gem->bo);
707 static drm_intel_bo *
708 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr,
712 uint32_t tiling_mode,
713 unsigned long stride,
714 unsigned int alignment)
716 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
717 drm_intel_bo_gem *bo_gem;
718 unsigned int page_size = getpagesize();
720 struct drm_intel_gem_bo_bucket *bucket;
721 bool alloc_from_cache;
722 unsigned long bo_size;
723 bool for_render = false;
725 if (flags & BO_ALLOC_FOR_RENDER)
728 /* Round the allocated size up to a power of two number of pages. */
729 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
731 /* If we don't have caching at this size, don't actually round the
734 if (bucket == NULL) {
736 if (bo_size < page_size)
739 bo_size = bucket->size;
742 pthread_mutex_lock(&bufmgr_gem->lock);
743 /* Get a buffer out of the cache if available */
745 alloc_from_cache = false;
746 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) {
748 /* Allocate new render-target BOs from the tail (MRU)
749 * of the list, as it will likely be hot in the GPU
750 * cache and in the aperture for us.
752 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
753 bucket->head.prev, head);
754 DRMLISTDEL(&bo_gem->head);
755 alloc_from_cache = true;
756 bo_gem->bo.align = alignment;
758 assert(alignment == 0);
759 /* For non-render-target BOs (where we're probably
760 * going to map it first thing in order to fill it
761 * with data), check if the last BO in the cache is
762 * unbusy, and only reuse in that case. Otherwise,
763 * allocating a new buffer is probably faster than
764 * waiting for the GPU to finish.
766 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
767 bucket->head.next, head);
768 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
769 alloc_from_cache = true;
770 DRMLISTDEL(&bo_gem->head);
774 if (alloc_from_cache) {
775 if (!drm_intel_gem_bo_madvise_internal
776 (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) {
777 drm_intel_gem_bo_free(&bo_gem->bo);
778 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem,
783 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
786 drm_intel_gem_bo_free(&bo_gem->bo);
792 if (!alloc_from_cache) {
793 struct drm_i915_gem_create create;
795 bo_gem = calloc(1, sizeof(*bo_gem));
799 /* drm_intel_gem_bo_free calls DRMLISTDEL() for an uninitialized
800 list (vma_list), so better set the list head here */
801 DRMINITLISTHEAD(&bo_gem->vma_list);
803 bo_gem->bo.size = bo_size;
806 create.size = bo_size;
808 ret = drmIoctl(bufmgr_gem->fd,
809 DRM_IOCTL_I915_GEM_CREATE,
816 bo_gem->gem_handle = create.handle;
817 HASH_ADD(handle_hh, bufmgr_gem->handle_table,
818 gem_handle, sizeof(bo_gem->gem_handle),
821 bo_gem->bo.handle = bo_gem->gem_handle;
822 bo_gem->bo.bufmgr = bufmgr;
823 bo_gem->bo.align = alignment;
825 bo_gem->tiling_mode = I915_TILING_NONE;
826 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
829 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
836 atomic_set(&bo_gem->refcount, 1);
837 bo_gem->validate_index = -1;
838 bo_gem->reloc_tree_fences = 0;
839 bo_gem->used_as_reloc_target = false;
840 bo_gem->has_error = false;
841 bo_gem->reusable = true;
843 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem, alignment);
844 pthread_mutex_unlock(&bufmgr_gem->lock);
846 DBG("bo_create: buf %d (%s) %ldb\n",
847 bo_gem->gem_handle, bo_gem->name, size);
852 drm_intel_gem_bo_free(&bo_gem->bo);
854 pthread_mutex_unlock(&bufmgr_gem->lock);
858 static drm_intel_bo *
859 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
862 unsigned int alignment)
864 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
870 static drm_intel_bo *
871 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr,
874 unsigned int alignment)
876 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0,
877 I915_TILING_NONE, 0, 0);
880 static drm_intel_bo *
881 drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
882 int x, int y, int cpp, uint32_t *tiling_mode,
883 unsigned long *pitch, unsigned long flags)
885 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
886 unsigned long size, stride;
890 unsigned long aligned_y, height_alignment;
892 tiling = *tiling_mode;
894 /* If we're tiled, our allocations are in 8 or 32-row blocks,
895 * so failure to align our height means that we won't allocate
898 * If we're untiled, we still have to align to 2 rows high
899 * because the data port accesses 2x2 blocks even if the
900 * bottom row isn't to be rendered, so failure to align means
901 * we could walk off the end of the GTT and fault. This is
902 * documented on 965, and may be the case on older chipsets
903 * too so we try to be careful.
906 height_alignment = 2;
908 if ((bufmgr_gem->gen == 2) && tiling != I915_TILING_NONE)
909 height_alignment = 16;
910 else if (tiling == I915_TILING_X
911 || (IS_915(bufmgr_gem->pci_device)
912 && tiling == I915_TILING_Y))
913 height_alignment = 8;
914 else if (tiling == I915_TILING_Y)
915 height_alignment = 32;
916 aligned_y = ALIGN(y, height_alignment);
919 stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, tiling_mode);
920 size = stride * aligned_y;
921 size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
922 } while (*tiling_mode != tiling);
925 if (tiling == I915_TILING_NONE)
928 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags,
932 static drm_intel_bo *
933 drm_intel_gem_bo_alloc_userptr(drm_intel_bufmgr *bufmgr,
936 uint32_t tiling_mode,
941 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
942 drm_intel_bo_gem *bo_gem;
944 struct drm_i915_gem_userptr userptr;
946 /* Tiling with userptr surfaces is not supported
947 * on all hardware so refuse it for time being.
949 if (tiling_mode != I915_TILING_NONE)
952 bo_gem = calloc(1, sizeof(*bo_gem));
956 atomic_set(&bo_gem->refcount, 1);
957 DRMINITLISTHEAD(&bo_gem->vma_list);
959 bo_gem->bo.size = size;
962 userptr.user_ptr = (__u64)((unsigned long)addr);
963 userptr.user_size = size;
964 userptr.flags = flags;
966 ret = drmIoctl(bufmgr_gem->fd,
967 DRM_IOCTL_I915_GEM_USERPTR,
970 DBG("bo_create_userptr: "
971 "ioctl failed with user ptr %p size 0x%lx, "
972 "user flags 0x%lx\n", addr, size, flags);
977 pthread_mutex_lock(&bufmgr_gem->lock);
979 bo_gem->gem_handle = userptr.handle;
980 bo_gem->bo.handle = bo_gem->gem_handle;
981 bo_gem->bo.bufmgr = bufmgr;
982 bo_gem->is_userptr = true;
983 bo_gem->bo.virtual = addr;
984 /* Save the address provided by user */
985 bo_gem->user_virtual = addr;
986 bo_gem->tiling_mode = I915_TILING_NONE;
987 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
990 HASH_ADD(handle_hh, bufmgr_gem->handle_table,
991 gem_handle, sizeof(bo_gem->gem_handle),
995 bo_gem->validate_index = -1;
996 bo_gem->reloc_tree_fences = 0;
997 bo_gem->used_as_reloc_target = false;
998 bo_gem->has_error = false;
999 bo_gem->reusable = false;
1001 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem, 0);
1002 pthread_mutex_unlock(&bufmgr_gem->lock);
1004 DBG("bo_create_userptr: "
1005 "ptr %p buf %d (%s) size %ldb, stride 0x%x, tile mode %d\n",
1006 addr, bo_gem->gem_handle, bo_gem->name,
1007 size, stride, tiling_mode);
1013 has_userptr(drm_intel_bufmgr_gem *bufmgr_gem)
1018 struct drm_i915_gem_userptr userptr;
1020 pgsz = sysconf(_SC_PAGESIZE);
1023 ret = posix_memalign(&ptr, pgsz, pgsz);
1025 DBG("Failed to get a page (%ld) for userptr detection!\n",
1031 userptr.user_ptr = (__u64)(unsigned long)ptr;
1032 userptr.user_size = pgsz;
1035 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_USERPTR, &userptr);
1037 if (errno == ENODEV && userptr.flags == 0) {
1038 userptr.flags = I915_USERPTR_UNSYNCHRONIZED;
1045 /* We don't release the userptr bo here as we want to keep the
1046 * kernel mm tracking alive for our lifetime. The first time we
1047 * create a userptr object the kernel has to install a mmu_notifer
1048 * which is a heavyweight operation (e.g. it requires taking all
1049 * mm_locks and stop_machine()).
1052 bufmgr_gem->userptr_active.ptr = ptr;
1053 bufmgr_gem->userptr_active.handle = userptr.handle;
1058 static drm_intel_bo *
1059 check_bo_alloc_userptr(drm_intel_bufmgr *bufmgr,
1062 uint32_t tiling_mode,
1065 unsigned long flags)
1067 if (has_userptr((drm_intel_bufmgr_gem *)bufmgr))
1068 bufmgr->bo_alloc_userptr = drm_intel_gem_bo_alloc_userptr;
1070 bufmgr->bo_alloc_userptr = NULL;
1072 return drm_intel_bo_alloc_userptr(bufmgr, name, addr,
1073 tiling_mode, stride, size, flags);
1077 * Returns a drm_intel_bo wrapping the given buffer object handle.
1079 * This can be used when one application needs to pass a buffer object
1083 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
1085 unsigned int handle)
1087 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1088 drm_intel_bo_gem *bo_gem;
1090 struct drm_gem_open open_arg;
1091 struct drm_i915_gem_get_tiling get_tiling;
1093 /* At the moment most applications only have a few named bo.
1094 * For instance, in a DRI client only the render buffers passed
1095 * between X and the client are named. And since X returns the
1096 * alternating names for the front/back buffer a linear search
1097 * provides a sufficiently fast match.
1099 pthread_mutex_lock(&bufmgr_gem->lock);
1100 HASH_FIND(name_hh, bufmgr_gem->name_table,
1101 &handle, sizeof(handle), bo_gem);
1103 drm_intel_gem_bo_reference(&bo_gem->bo);
1108 open_arg.name = handle;
1109 ret = drmIoctl(bufmgr_gem->fd,
1113 DBG("Couldn't reference %s handle 0x%08x: %s\n",
1114 name, handle, strerror(errno));
1118 /* Now see if someone has used a prime handle to get this
1119 * object from the kernel before by looking through the list
1120 * again for a matching gem_handle
1122 HASH_FIND(handle_hh, bufmgr_gem->handle_table,
1123 &open_arg.handle, sizeof(open_arg.handle), bo_gem);
1125 drm_intel_gem_bo_reference(&bo_gem->bo);
1129 bo_gem = calloc(1, sizeof(*bo_gem));
1133 atomic_set(&bo_gem->refcount, 1);
1134 DRMINITLISTHEAD(&bo_gem->vma_list);
1136 bo_gem->bo.size = open_arg.size;
1137 bo_gem->bo.offset = 0;
1138 bo_gem->bo.offset64 = 0;
1139 bo_gem->bo.virtual = NULL;
1140 bo_gem->bo.bufmgr = bufmgr;
1141 bo_gem->name = name;
1142 bo_gem->validate_index = -1;
1143 bo_gem->gem_handle = open_arg.handle;
1144 bo_gem->bo.handle = open_arg.handle;
1145 bo_gem->global_name = handle;
1146 bo_gem->reusable = false;
1148 HASH_ADD(handle_hh, bufmgr_gem->handle_table,
1149 gem_handle, sizeof(bo_gem->gem_handle), bo_gem);
1150 HASH_ADD(name_hh, bufmgr_gem->name_table,
1151 global_name, sizeof(bo_gem->global_name), bo_gem);
1153 memclear(get_tiling);
1154 get_tiling.handle = bo_gem->gem_handle;
1155 ret = drmIoctl(bufmgr_gem->fd,
1156 DRM_IOCTL_I915_GEM_GET_TILING,
1161 bo_gem->tiling_mode = get_tiling.tiling_mode;
1162 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
1163 /* XXX stride is unknown */
1164 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem, 0);
1165 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
1168 pthread_mutex_unlock(&bufmgr_gem->lock);
1172 drm_intel_gem_bo_free(&bo_gem->bo);
1173 pthread_mutex_unlock(&bufmgr_gem->lock);
1178 drm_intel_gem_bo_free(drm_intel_bo *bo)
1180 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1181 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1182 struct drm_gem_close close;
1185 DRMLISTDEL(&bo_gem->vma_list);
1186 if (bo_gem->mem_virtual) {
1187 VG(VALGRIND_FREELIKE_BLOCK(bo_gem->mem_virtual, 0));
1188 drm_munmap(bo_gem->mem_virtual, bo_gem->bo.size);
1189 bufmgr_gem->vma_count--;
1191 if (bo_gem->wc_virtual) {
1192 VG(VALGRIND_FREELIKE_BLOCK(bo_gem->wc_virtual, 0));
1193 drm_munmap(bo_gem->wc_virtual, bo_gem->bo.size);
1194 bufmgr_gem->vma_count--;
1196 if (bo_gem->gtt_virtual) {
1197 drm_munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
1198 bufmgr_gem->vma_count--;
1201 if (bo_gem->global_name)
1202 HASH_DELETE(name_hh, bufmgr_gem->name_table, bo_gem);
1203 HASH_DELETE(handle_hh, bufmgr_gem->handle_table, bo_gem);
1205 /* Close this object */
1207 close.handle = bo_gem->gem_handle;
1208 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
1210 DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
1211 bo_gem->gem_handle, bo_gem->name, strerror(errno));
1217 drm_intel_gem_bo_mark_mmaps_incoherent(drm_intel_bo *bo)
1220 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1222 if (bo_gem->mem_virtual)
1223 VALGRIND_MAKE_MEM_NOACCESS(bo_gem->mem_virtual, bo->size);
1225 if (bo_gem->wc_virtual)
1226 VALGRIND_MAKE_MEM_NOACCESS(bo_gem->wc_virtual, bo->size);
1228 if (bo_gem->gtt_virtual)
1229 VALGRIND_MAKE_MEM_NOACCESS(bo_gem->gtt_virtual, bo->size);
1233 /** Frees all cached buffers significantly older than @time. */
1235 drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time)
1239 if (bufmgr_gem->time == time)
1242 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
1243 struct drm_intel_gem_bo_bucket *bucket =
1244 &bufmgr_gem->cache_bucket[i];
1246 while (!DRMLISTEMPTY(&bucket->head)) {
1247 drm_intel_bo_gem *bo_gem;
1249 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1250 bucket->head.next, head);
1251 if (time - bo_gem->free_time <= 1)
1254 DRMLISTDEL(&bo_gem->head);
1256 drm_intel_gem_bo_free(&bo_gem->bo);
1260 bufmgr_gem->time = time;
1263 static void drm_intel_gem_bo_purge_vma_cache(drm_intel_bufmgr_gem *bufmgr_gem)
1267 DBG("%s: cached=%d, open=%d, limit=%d\n", __FUNCTION__,
1268 bufmgr_gem->vma_count, bufmgr_gem->vma_open, bufmgr_gem->vma_max);
1270 if (bufmgr_gem->vma_max < 0)
1273 /* We may need to evict a few entries in order to create new mmaps */
1274 limit = bufmgr_gem->vma_max - 2*bufmgr_gem->vma_open;
1278 while (bufmgr_gem->vma_count > limit) {
1279 drm_intel_bo_gem *bo_gem;
1281 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1282 bufmgr_gem->vma_cache.next,
1284 assert(bo_gem->map_count == 0);
1285 DRMLISTDELINIT(&bo_gem->vma_list);
1287 if (bo_gem->mem_virtual) {
1288 drm_munmap(bo_gem->mem_virtual, bo_gem->bo.size);
1289 bo_gem->mem_virtual = NULL;
1290 bufmgr_gem->vma_count--;
1292 if (bo_gem->wc_virtual) {
1293 drm_munmap(bo_gem->wc_virtual, bo_gem->bo.size);
1294 bo_gem->wc_virtual = NULL;
1295 bufmgr_gem->vma_count--;
1297 if (bo_gem->gtt_virtual) {
1298 drm_munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
1299 bo_gem->gtt_virtual = NULL;
1300 bufmgr_gem->vma_count--;
1305 static void drm_intel_gem_bo_close_vma(drm_intel_bufmgr_gem *bufmgr_gem,
1306 drm_intel_bo_gem *bo_gem)
1308 bufmgr_gem->vma_open--;
1309 DRMLISTADDTAIL(&bo_gem->vma_list, &bufmgr_gem->vma_cache);
1310 if (bo_gem->mem_virtual)
1311 bufmgr_gem->vma_count++;
1312 if (bo_gem->wc_virtual)
1313 bufmgr_gem->vma_count++;
1314 if (bo_gem->gtt_virtual)
1315 bufmgr_gem->vma_count++;
1316 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
1319 static void drm_intel_gem_bo_open_vma(drm_intel_bufmgr_gem *bufmgr_gem,
1320 drm_intel_bo_gem *bo_gem)
1322 bufmgr_gem->vma_open++;
1323 DRMLISTDEL(&bo_gem->vma_list);
1324 if (bo_gem->mem_virtual)
1325 bufmgr_gem->vma_count--;
1326 if (bo_gem->wc_virtual)
1327 bufmgr_gem->vma_count--;
1328 if (bo_gem->gtt_virtual)
1329 bufmgr_gem->vma_count--;
1330 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
1334 drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
1336 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1337 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1338 struct drm_intel_gem_bo_bucket *bucket;
1341 /* Unreference all the target buffers */
1342 for (i = 0; i < bo_gem->reloc_count; i++) {
1343 if (bo_gem->reloc_target_info[i].bo != bo) {
1344 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
1345 reloc_target_info[i].bo,
1349 for (i = 0; i < bo_gem->softpin_target_count; i++)
1350 drm_intel_gem_bo_unreference_locked_timed(bo_gem->softpin_target[i],
1353 bo_gem->reloc_count = 0;
1354 bo_gem->used_as_reloc_target = false;
1355 bo_gem->softpin_target_count = 0;
1357 DBG("bo_unreference final: %d (%s)\n",
1358 bo_gem->gem_handle, bo_gem->name);
1360 /* release memory associated with this object */
1361 if (bo_gem->reloc_target_info) {
1362 free(bo_gem->reloc_target_info);
1363 bo_gem->reloc_target_info = NULL;
1365 if (bo_gem->relocs) {
1366 free(bo_gem->relocs);
1367 bo_gem->relocs = NULL;
1369 if (bo_gem->softpin_target) {
1370 free(bo_gem->softpin_target);
1371 bo_gem->softpin_target = NULL;
1372 bo_gem->softpin_target_size = 0;
1375 /* Clear any left-over mappings */
1376 if (bo_gem->map_count) {
1377 DBG("bo freed with non-zero map-count %d\n", bo_gem->map_count);
1378 bo_gem->map_count = 0;
1379 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1380 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1383 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
1384 /* Put the buffer into our internal cache for reuse if we can. */
1385 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
1386 drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem,
1387 I915_MADV_DONTNEED)) {
1388 bo_gem->free_time = time;
1390 bo_gem->name = NULL;
1391 bo_gem->validate_index = -1;
1393 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
1395 drm_intel_gem_bo_free(bo);
1399 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
1402 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1404 assert(atomic_read(&bo_gem->refcount) > 0);
1405 if (atomic_dec_and_test(&bo_gem->refcount))
1406 drm_intel_gem_bo_unreference_final(bo, time);
1409 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
1411 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1413 assert(atomic_read(&bo_gem->refcount) > 0);
1415 if (atomic_add_unless(&bo_gem->refcount, -1, 1)) {
1416 drm_intel_bufmgr_gem *bufmgr_gem =
1417 (drm_intel_bufmgr_gem *) bo->bufmgr;
1418 struct timespec time;
1420 clock_gettime(CLOCK_MONOTONIC, &time);
1422 pthread_mutex_lock(&bufmgr_gem->lock);
1424 if (atomic_dec_and_test(&bo_gem->refcount)) {
1425 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
1426 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time.tv_sec);
1429 pthread_mutex_unlock(&bufmgr_gem->lock);
1433 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
1435 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1436 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1437 struct drm_i915_gem_set_domain set_domain;
1440 if (bo_gem->is_userptr) {
1441 /* Return the same user ptr */
1442 bo->virtual = bo_gem->user_virtual;
1446 pthread_mutex_lock(&bufmgr_gem->lock);
1448 if (bo_gem->map_count++ == 0)
1449 drm_intel_gem_bo_open_vma(bufmgr_gem, bo_gem);
1451 if (!bo_gem->mem_virtual) {
1452 struct drm_i915_gem_mmap mmap_arg;
1454 DBG("bo_map: %d (%s), map_count=%d\n",
1455 bo_gem->gem_handle, bo_gem->name, bo_gem->map_count);
1458 mmap_arg.handle = bo_gem->gem_handle;
1459 mmap_arg.size = bo->size;
1460 ret = drmIoctl(bufmgr_gem->fd,
1461 DRM_IOCTL_I915_GEM_MMAP,
1465 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1466 __FILE__, __LINE__, bo_gem->gem_handle,
1467 bo_gem->name, strerror(errno));
1468 if (--bo_gem->map_count == 0)
1469 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1470 pthread_mutex_unlock(&bufmgr_gem->lock);
1473 VG(VALGRIND_MALLOCLIKE_BLOCK(mmap_arg.addr_ptr, mmap_arg.size, 0, 1));
1474 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
1476 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1477 bo_gem->mem_virtual);
1478 bo->virtual = bo_gem->mem_virtual;
1480 memclear(set_domain);
1481 set_domain.handle = bo_gem->gem_handle;
1482 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
1484 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
1486 set_domain.write_domain = 0;
1487 ret = drmIoctl(bufmgr_gem->fd,
1488 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1491 DBG("%s:%d: Error setting to CPU domain %d: %s\n",
1492 __FILE__, __LINE__, bo_gem->gem_handle,
1497 bo_gem->mapped_cpu_write = true;
1499 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1500 VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->mem_virtual, bo->size));
1501 pthread_mutex_unlock(&bufmgr_gem->lock);
1507 map_gtt(drm_intel_bo *bo)
1509 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1510 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1513 if (bo_gem->is_userptr)
1516 if (bo_gem->map_count++ == 0)
1517 drm_intel_gem_bo_open_vma(bufmgr_gem, bo_gem);
1519 /* Get a mapping of the buffer if we haven't before. */
1520 if (bo_gem->gtt_virtual == NULL) {
1521 struct drm_i915_gem_mmap_gtt mmap_arg;
1523 DBG("bo_map_gtt: mmap %d (%s), map_count=%d\n",
1524 bo_gem->gem_handle, bo_gem->name, bo_gem->map_count);
1527 mmap_arg.handle = bo_gem->gem_handle;
1529 /* Get the fake offset back... */
1530 ret = drmIoctl(bufmgr_gem->fd,
1531 DRM_IOCTL_I915_GEM_MMAP_GTT,
1535 DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n",
1537 bo_gem->gem_handle, bo_gem->name,
1539 if (--bo_gem->map_count == 0)
1540 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1545 bo_gem->gtt_virtual = drm_mmap(0, bo->size, PROT_READ | PROT_WRITE,
1546 MAP_SHARED, bufmgr_gem->fd,
1548 if (bo_gem->gtt_virtual == MAP_FAILED) {
1549 bo_gem->gtt_virtual = NULL;
1551 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1553 bo_gem->gem_handle, bo_gem->name,
1555 if (--bo_gem->map_count == 0)
1556 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1561 bo->virtual = bo_gem->gtt_virtual;
1563 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1564 bo_gem->gtt_virtual);
1570 drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
1572 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1573 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1574 struct drm_i915_gem_set_domain set_domain;
1577 pthread_mutex_lock(&bufmgr_gem->lock);
1581 pthread_mutex_unlock(&bufmgr_gem->lock);
1585 /* Now move it to the GTT domain so that the GPU and CPU
1586 * caches are flushed and the GPU isn't actively using the
1589 * The pagefault handler does this domain change for us when
1590 * it has unbound the BO from the GTT, but it's up to us to
1591 * tell it when we're about to use things if we had done
1592 * rendering and it still happens to be bound to the GTT.
1594 memclear(set_domain);
1595 set_domain.handle = bo_gem->gem_handle;
1596 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1597 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
1598 ret = drmIoctl(bufmgr_gem->fd,
1599 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1602 DBG("%s:%d: Error setting domain %d: %s\n",
1603 __FILE__, __LINE__, bo_gem->gem_handle,
1607 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1608 VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->gtt_virtual, bo->size));
1609 pthread_mutex_unlock(&bufmgr_gem->lock);
1615 * Performs a mapping of the buffer object like the normal GTT
1616 * mapping, but avoids waiting for the GPU to be done reading from or
1617 * rendering to the buffer.
1619 * This is used in the implementation of GL_ARB_map_buffer_range: The
1620 * user asks to create a buffer, then does a mapping, fills some
1621 * space, runs a drawing command, then asks to map it again without
1622 * synchronizing because it guarantees that it won't write over the
1623 * data that the GPU is busy using (or, more specifically, that if it
1624 * does write over the data, it acknowledges that rendering is
1629 drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo)
1631 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1632 #ifdef HAVE_VALGRIND
1633 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1637 /* If the CPU cache isn't coherent with the GTT, then use a
1638 * regular synchronized mapping. The problem is that we don't
1639 * track where the buffer was last used on the CPU side in
1640 * terms of drm_intel_bo_map vs drm_intel_gem_bo_map_gtt, so
1641 * we would potentially corrupt the buffer even when the user
1642 * does reasonable things.
1644 if (!bufmgr_gem->has_llc)
1645 return drm_intel_gem_bo_map_gtt(bo);
1647 pthread_mutex_lock(&bufmgr_gem->lock);
1651 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1652 VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->gtt_virtual, bo->size));
1655 pthread_mutex_unlock(&bufmgr_gem->lock);
1660 static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
1662 drm_intel_bufmgr_gem *bufmgr_gem;
1663 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1669 if (bo_gem->is_userptr)
1672 bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1674 pthread_mutex_lock(&bufmgr_gem->lock);
1676 if (bo_gem->map_count <= 0) {
1677 DBG("attempted to unmap an unmapped bo\n");
1678 pthread_mutex_unlock(&bufmgr_gem->lock);
1679 /* Preserve the old behaviour of just treating this as a
1680 * no-op rather than reporting the error.
1685 if (bo_gem->mapped_cpu_write) {
1686 struct drm_i915_gem_sw_finish sw_finish;
1688 /* Cause a flush to happen if the buffer's pinned for
1689 * scanout, so the results show up in a timely manner.
1690 * Unlike GTT set domains, this only does work if the
1691 * buffer should be scanout-related.
1693 memclear(sw_finish);
1694 sw_finish.handle = bo_gem->gem_handle;
1695 ret = drmIoctl(bufmgr_gem->fd,
1696 DRM_IOCTL_I915_GEM_SW_FINISH,
1698 ret = ret == -1 ? -errno : 0;
1700 bo_gem->mapped_cpu_write = false;
1703 /* We need to unmap after every innovation as we cannot track
1704 * an open vma for every bo as that will exhaust the system
1705 * limits and cause later failures.
1707 if (--bo_gem->map_count == 0) {
1708 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1709 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1712 pthread_mutex_unlock(&bufmgr_gem->lock);
1718 drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
1720 return drm_intel_gem_bo_unmap(bo);
1724 drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset,
1725 unsigned long size, const void *data)
1727 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1728 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1729 struct drm_i915_gem_pwrite pwrite;
1732 if (bo_gem->is_userptr)
1736 pwrite.handle = bo_gem->gem_handle;
1737 pwrite.offset = offset;
1739 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
1740 ret = drmIoctl(bufmgr_gem->fd,
1741 DRM_IOCTL_I915_GEM_PWRITE,
1745 DBG("%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
1746 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1747 (int)size, strerror(errno));
1754 drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
1756 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1757 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
1760 memclear(get_pipe_from_crtc_id);
1761 get_pipe_from_crtc_id.crtc_id = crtc_id;
1762 ret = drmIoctl(bufmgr_gem->fd,
1763 DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
1764 &get_pipe_from_crtc_id);
1766 /* We return -1 here to signal that we don't
1767 * know which pipe is associated with this crtc.
1768 * This lets the caller know that this information
1769 * isn't available; using the wrong pipe for
1770 * vblank waiting can cause the chipset to lock up
1775 return get_pipe_from_crtc_id.pipe;
1779 drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
1780 unsigned long size, void *data)
1782 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1783 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1784 struct drm_i915_gem_pread pread;
1787 if (bo_gem->is_userptr)
1791 pread.handle = bo_gem->gem_handle;
1792 pread.offset = offset;
1794 pread.data_ptr = (uint64_t) (uintptr_t) data;
1795 ret = drmIoctl(bufmgr_gem->fd,
1796 DRM_IOCTL_I915_GEM_PREAD,
1800 DBG("%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
1801 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1802 (int)size, strerror(errno));
1808 /** Waits for all GPU rendering with the object to have completed. */
1810 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
1812 drm_intel_gem_bo_start_gtt_access(bo, 1);
1816 * Waits on a BO for the given amount of time.
1818 * @bo: buffer object to wait for
1819 * @timeout_ns: amount of time to wait in nanoseconds.
1820 * If value is less than 0, an infinite wait will occur.
1822 * Returns 0 if the wait was successful ie. the last batch referencing the
1823 * object has completed within the allotted time. Otherwise some negative return
1824 * value describes the error. Of particular interest is -ETIME when the wait has
1825 * failed to yield the desired result.
1827 * Similar to drm_intel_gem_bo_wait_rendering except a timeout parameter allows
1828 * the operation to give up after a certain amount of time. Another subtle
1829 * difference is the internal locking semantics are different (this variant does
1830 * not hold the lock for the duration of the wait). This makes the wait subject
1831 * to a larger userspace race window.
1833 * The implementation shall wait until the object is no longer actively
1834 * referenced within a batch buffer at the time of the call. The wait will
1835 * not guarantee that the buffer is re-issued via another thread, or an flinked
1836 * handle. Userspace must make sure this race does not occur if such precision
1839 * Note that some kernels have broken the inifite wait for negative values
1840 * promise, upgrade to latest stable kernels if this is the case.
1843 drm_intel_gem_bo_wait(drm_intel_bo *bo, int64_t timeout_ns)
1845 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1846 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1847 struct drm_i915_gem_wait wait;
1850 if (!bufmgr_gem->has_wait_timeout) {
1851 DBG("%s:%d: Timed wait is not supported. Falling back to "
1852 "infinite wait\n", __FILE__, __LINE__);
1854 drm_intel_gem_bo_wait_rendering(bo);
1857 return drm_intel_gem_bo_busy(bo) ? -ETIME : 0;
1862 wait.bo_handle = bo_gem->gem_handle;
1863 wait.timeout_ns = timeout_ns;
1864 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_WAIT, &wait);
1872 * Sets the object to the GTT read and possibly write domain, used by the X
1873 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
1875 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
1876 * can do tiled pixmaps this way.
1879 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
1881 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1882 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1883 struct drm_i915_gem_set_domain set_domain;
1886 memclear(set_domain);
1887 set_domain.handle = bo_gem->gem_handle;
1888 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1889 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
1890 ret = drmIoctl(bufmgr_gem->fd,
1891 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1894 DBG("%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
1895 __FILE__, __LINE__, bo_gem->gem_handle,
1896 set_domain.read_domains, set_domain.write_domain,
1902 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
1904 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1905 struct drm_gem_close close_bo;
1908 free(bufmgr_gem->exec2_objects);
1909 free(bufmgr_gem->exec_objects);
1910 free(bufmgr_gem->exec_bos);
1912 pthread_mutex_destroy(&bufmgr_gem->lock);
1914 /* Free any cached buffer objects we were going to reuse */
1915 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
1916 struct drm_intel_gem_bo_bucket *bucket =
1917 &bufmgr_gem->cache_bucket[i];
1918 drm_intel_bo_gem *bo_gem;
1920 while (!DRMLISTEMPTY(&bucket->head)) {
1921 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1922 bucket->head.next, head);
1923 DRMLISTDEL(&bo_gem->head);
1925 drm_intel_gem_bo_free(&bo_gem->bo);
1929 /* Release userptr bo kept hanging around for optimisation. */
1930 if (bufmgr_gem->userptr_active.ptr) {
1932 close_bo.handle = bufmgr_gem->userptr_active.handle;
1933 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close_bo);
1934 free(bufmgr_gem->userptr_active.ptr);
1937 "Failed to release test userptr object! (%d) "
1938 "i915 kernel driver may not be sane!\n", errno);
1945 * Adds the target buffer to the validation list and adds the relocation
1946 * to the reloc_buffer's relocation list.
1948 * The relocation entry at the given offset must already contain the
1949 * precomputed relocation value, because the kernel will optimize out
1950 * the relocation entry write when the buffer hasn't moved from the
1951 * last known offset in target_bo.
1954 do_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1955 drm_intel_bo *target_bo, uint32_t target_offset,
1956 uint32_t read_domains, uint32_t write_domain,
1959 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1960 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1961 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1962 bool fenced_command;
1964 if (bo_gem->has_error)
1967 if (target_bo_gem->has_error) {
1968 bo_gem->has_error = true;
1972 /* We never use HW fences for rendering on 965+ */
1973 if (bufmgr_gem->gen >= 4)
1976 fenced_command = need_fence;
1977 if (target_bo_gem->tiling_mode == I915_TILING_NONE)
1980 /* Create a new relocation list if needed */
1981 if (bo_gem->relocs == NULL && drm_intel_setup_reloc_list(bo))
1984 /* Check overflow */
1985 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
1988 assert(offset <= bo->size - 4);
1989 assert((write_domain & (write_domain - 1)) == 0);
1991 /* An object needing a fence is a tiled buffer, so it won't have
1992 * relocs to other buffers.
1995 assert(target_bo_gem->reloc_count == 0);
1996 target_bo_gem->reloc_tree_fences = 1;
1999 /* Make sure that we're not adding a reloc to something whose size has
2000 * already been accounted for.
2002 assert(!bo_gem->used_as_reloc_target);
2003 if (target_bo_gem != bo_gem) {
2004 target_bo_gem->used_as_reloc_target = true;
2005 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
2006 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
2009 bo_gem->reloc_target_info[bo_gem->reloc_count].bo = target_bo;
2010 if (target_bo != bo)
2011 drm_intel_gem_bo_reference(target_bo);
2013 bo_gem->reloc_target_info[bo_gem->reloc_count].flags =
2014 DRM_INTEL_RELOC_FENCE;
2016 bo_gem->reloc_target_info[bo_gem->reloc_count].flags = 0;
2018 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
2019 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
2020 bo_gem->relocs[bo_gem->reloc_count].target_handle =
2021 target_bo_gem->gem_handle;
2022 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
2023 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
2024 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset64;
2025 bo_gem->reloc_count++;
2031 drm_intel_gem_bo_use_48b_address_range(drm_intel_bo *bo, uint32_t enable)
2033 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2036 bo_gem->kflags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
2038 bo_gem->kflags &= ~EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
2042 drm_intel_gem_bo_add_softpin_target(drm_intel_bo *bo, drm_intel_bo *target_bo)
2044 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2045 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2046 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
2047 if (bo_gem->has_error)
2050 if (target_bo_gem->has_error) {
2051 bo_gem->has_error = true;
2055 if (!(target_bo_gem->kflags & EXEC_OBJECT_PINNED))
2057 if (target_bo_gem == bo_gem)
2060 if (bo_gem->softpin_target_count == bo_gem->softpin_target_size) {
2061 int new_size = bo_gem->softpin_target_size * 2;
2063 new_size = bufmgr_gem->max_relocs;
2065 bo_gem->softpin_target = realloc(bo_gem->softpin_target, new_size *
2066 sizeof(drm_intel_bo *));
2067 if (!bo_gem->softpin_target)
2070 bo_gem->softpin_target_size = new_size;
2072 bo_gem->softpin_target[bo_gem->softpin_target_count] = target_bo;
2073 drm_intel_gem_bo_reference(target_bo);
2074 bo_gem->softpin_target_count++;
2080 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
2081 drm_intel_bo *target_bo, uint32_t target_offset,
2082 uint32_t read_domains, uint32_t write_domain)
2084 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
2085 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *)target_bo;
2087 if (target_bo_gem->kflags & EXEC_OBJECT_PINNED)
2088 return drm_intel_gem_bo_add_softpin_target(bo, target_bo);
2090 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
2091 read_domains, write_domain,
2092 !bufmgr_gem->fenced_relocs);
2096 drm_intel_gem_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
2097 drm_intel_bo *target_bo,
2098 uint32_t target_offset,
2099 uint32_t read_domains, uint32_t write_domain)
2101 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
2102 read_domains, write_domain, true);
2106 drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo)
2108 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2110 return bo_gem->reloc_count;
2114 * Removes existing relocation entries in the BO after "start".
2116 * This allows a user to avoid a two-step process for state setup with
2117 * counting up all the buffer objects and doing a
2118 * drm_intel_bufmgr_check_aperture_space() before emitting any of the
2119 * relocations for the state setup. Instead, save the state of the
2120 * batchbuffer including drm_intel_gem_get_reloc_count(), emit all the
2121 * state, and then check if it still fits in the aperture.
2123 * Any further drm_intel_bufmgr_check_aperture_space() queries
2124 * involving this buffer in the tree are undefined after this call.
2126 * This also removes all softpinned targets being referenced by the BO.
2129 drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start)
2131 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2132 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2134 struct timespec time;
2136 clock_gettime(CLOCK_MONOTONIC, &time);
2138 assert(bo_gem->reloc_count >= start);
2140 /* Unreference the cleared target buffers */
2141 pthread_mutex_lock(&bufmgr_gem->lock);
2143 for (i = start; i < bo_gem->reloc_count; i++) {
2144 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) bo_gem->reloc_target_info[i].bo;
2145 if (&target_bo_gem->bo != bo) {
2146 bo_gem->reloc_tree_fences -= target_bo_gem->reloc_tree_fences;
2147 drm_intel_gem_bo_unreference_locked_timed(&target_bo_gem->bo,
2151 bo_gem->reloc_count = start;
2153 for (i = 0; i < bo_gem->softpin_target_count; i++) {
2154 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) bo_gem->softpin_target[i];
2155 drm_intel_gem_bo_unreference_locked_timed(&target_bo_gem->bo, time.tv_sec);
2157 bo_gem->softpin_target_count = 0;
2159 pthread_mutex_unlock(&bufmgr_gem->lock);
2164 * Walk the tree of relocations rooted at BO and accumulate the list of
2165 * validations to be performed and update the relocation buffers with
2166 * index values into the validation list.
2169 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
2171 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2174 if (bo_gem->relocs == NULL)
2177 for (i = 0; i < bo_gem->reloc_count; i++) {
2178 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
2180 if (target_bo == bo)
2183 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
2185 /* Continue walking the tree depth-first. */
2186 drm_intel_gem_bo_process_reloc(target_bo);
2188 /* Add the target to the validate list */
2189 drm_intel_add_validate_buffer(target_bo);
2194 drm_intel_gem_bo_process_reloc2(drm_intel_bo *bo)
2196 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
2199 if (bo_gem->relocs == NULL && bo_gem->softpin_target == NULL)
2202 for (i = 0; i < bo_gem->reloc_count; i++) {
2203 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
2206 if (target_bo == bo)
2209 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
2211 /* Continue walking the tree depth-first. */
2212 drm_intel_gem_bo_process_reloc2(target_bo);
2214 need_fence = (bo_gem->reloc_target_info[i].flags &
2215 DRM_INTEL_RELOC_FENCE);
2217 /* Add the target to the validate list */
2218 drm_intel_add_validate_buffer2(target_bo, need_fence);
2221 for (i = 0; i < bo_gem->softpin_target_count; i++) {
2222 drm_intel_bo *target_bo = bo_gem->softpin_target[i];
2224 if (target_bo == bo)
2227 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
2228 drm_intel_gem_bo_process_reloc2(target_bo);
2229 drm_intel_add_validate_buffer2(target_bo, false);
2235 drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem)
2239 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2240 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
2241 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2243 /* Update the buffer offset */
2244 if (bufmgr_gem->exec_objects[i].offset != bo->offset64) {
2245 DBG("BO %d (%s) migrated: 0x%08x %08x -> 0x%08x %08x\n",
2246 bo_gem->gem_handle, bo_gem->name,
2247 upper_32_bits(bo->offset64),
2248 lower_32_bits(bo->offset64),
2249 upper_32_bits(bufmgr_gem->exec_objects[i].offset),
2250 lower_32_bits(bufmgr_gem->exec_objects[i].offset));
2251 bo->offset64 = bufmgr_gem->exec_objects[i].offset;
2252 bo->offset = bufmgr_gem->exec_objects[i].offset;
2258 drm_intel_update_buffer_offsets2 (drm_intel_bufmgr_gem *bufmgr_gem)
2262 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2263 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
2264 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
2266 /* Update the buffer offset */
2267 if (bufmgr_gem->exec2_objects[i].offset != bo->offset64) {
2268 /* If we're seeing softpinned object here it means that the kernel
2269 * has relocated our object... Indicating a programming error
2271 assert(!(bo_gem->kflags & EXEC_OBJECT_PINNED));
2272 DBG("BO %d (%s) migrated: 0x%08x %08x -> 0x%08x %08x\n",
2273 bo_gem->gem_handle, bo_gem->name,
2274 upper_32_bits(bo->offset64),
2275 lower_32_bits(bo->offset64),
2276 upper_32_bits(bufmgr_gem->exec2_objects[i].offset),
2277 lower_32_bits(bufmgr_gem->exec2_objects[i].offset));
2278 bo->offset64 = bufmgr_gem->exec2_objects[i].offset;
2279 bo->offset = bufmgr_gem->exec2_objects[i].offset;
2285 drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo,
2286 int x1, int y1, int width, int height,
2287 enum aub_dump_bmp_format format,
2288 int pitch, int offset)
2293 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
2294 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
2296 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2297 struct drm_i915_gem_execbuffer execbuf;
2300 if (to_bo_gem(bo)->has_error)
2303 pthread_mutex_lock(&bufmgr_gem->lock);
2304 /* Update indices and set up the validate list. */
2305 drm_intel_gem_bo_process_reloc(bo);
2307 /* Add the batch buffer to the validation list. There are no
2308 * relocations pointing to it.
2310 drm_intel_add_validate_buffer(bo);
2313 execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects;
2314 execbuf.buffer_count = bufmgr_gem->exec_count;
2315 execbuf.batch_start_offset = 0;
2316 execbuf.batch_len = used;
2317 execbuf.cliprects_ptr = (uintptr_t) cliprects;
2318 execbuf.num_cliprects = num_cliprects;
2322 ret = drmIoctl(bufmgr_gem->fd,
2323 DRM_IOCTL_I915_GEM_EXECBUFFER,
2327 if (errno == ENOSPC) {
2328 DBG("Execbuffer fails to pin. "
2329 "Estimate: %u. Actual: %u. Available: %u\n",
2330 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
2333 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
2336 (unsigned int)bufmgr_gem->gtt_size);
2339 drm_intel_update_buffer_offsets(bufmgr_gem);
2341 if (bufmgr_gem->bufmgr.debug)
2342 drm_intel_gem_dump_validation_list(bufmgr_gem);
2344 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2345 drm_intel_bo_gem *bo_gem = to_bo_gem(bufmgr_gem->exec_bos[i]);
2347 bo_gem->idle = false;
2349 /* Disconnect the buffer from the validate list */
2350 bo_gem->validate_index = -1;
2351 bufmgr_gem->exec_bos[i] = NULL;
2353 bufmgr_gem->exec_count = 0;
2354 pthread_mutex_unlock(&bufmgr_gem->lock);
2360 do_exec2(drm_intel_bo *bo, int used, drm_intel_context *ctx,
2361 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
2362 int in_fence, int *out_fence,
2365 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
2366 struct drm_i915_gem_execbuffer2 execbuf;
2370 if (to_bo_gem(bo)->has_error)
2373 switch (flags & 0x7) {
2377 if (!bufmgr_gem->has_blt)
2381 if (!bufmgr_gem->has_bsd)
2384 case I915_EXEC_VEBOX:
2385 if (!bufmgr_gem->has_vebox)
2388 case I915_EXEC_RENDER:
2389 case I915_EXEC_DEFAULT:
2393 pthread_mutex_lock(&bufmgr_gem->lock);
2394 /* Update indices and set up the validate list. */
2395 drm_intel_gem_bo_process_reloc2(bo);
2397 /* Add the batch buffer to the validation list. There are no relocations
2400 drm_intel_add_validate_buffer2(bo, 0);
2403 execbuf.buffers_ptr = (uintptr_t)bufmgr_gem->exec2_objects;
2404 execbuf.buffer_count = bufmgr_gem->exec_count;
2405 execbuf.batch_start_offset = 0;
2406 execbuf.batch_len = used;
2407 execbuf.cliprects_ptr = (uintptr_t)cliprects;
2408 execbuf.num_cliprects = num_cliprects;
2411 execbuf.flags = flags;
2413 i915_execbuffer2_set_context_id(execbuf, 0);
2415 i915_execbuffer2_set_context_id(execbuf, ctx->ctx_id);
2417 if (in_fence != -1) {
2418 execbuf.rsvd2 = in_fence;
2419 execbuf.flags |= I915_EXEC_FENCE_IN;
2421 if (out_fence != NULL) {
2423 execbuf.flags |= I915_EXEC_FENCE_OUT;
2426 if (bufmgr_gem->no_exec)
2427 goto skip_execution;
2429 ret = drmIoctl(bufmgr_gem->fd,
2430 DRM_IOCTL_I915_GEM_EXECBUFFER2_WR,
2434 if (ret == -ENOSPC) {
2435 DBG("Execbuffer fails to pin. "
2436 "Estimate: %u. Actual: %u. Available: %u\n",
2437 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
2438 bufmgr_gem->exec_count),
2439 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
2440 bufmgr_gem->exec_count),
2441 (unsigned int) bufmgr_gem->gtt_size);
2444 drm_intel_update_buffer_offsets2(bufmgr_gem);
2446 if (ret == 0 && out_fence != NULL)
2447 *out_fence = execbuf.rsvd2 >> 32;
2450 if (bufmgr_gem->bufmgr.debug)
2451 drm_intel_gem_dump_validation_list(bufmgr_gem);
2453 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2454 drm_intel_bo_gem *bo_gem = to_bo_gem(bufmgr_gem->exec_bos[i]);
2456 bo_gem->idle = false;
2458 /* Disconnect the buffer from the validate list */
2459 bo_gem->validate_index = -1;
2460 bufmgr_gem->exec_bos[i] = NULL;
2462 bufmgr_gem->exec_count = 0;
2463 pthread_mutex_unlock(&bufmgr_gem->lock);
2469 drm_intel_gem_bo_exec2(drm_intel_bo *bo, int used,
2470 drm_clip_rect_t *cliprects, int num_cliprects,
2473 return do_exec2(bo, used, NULL, cliprects, num_cliprects, DR4,
2474 -1, NULL, I915_EXEC_RENDER);
2478 drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used,
2479 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
2482 return do_exec2(bo, used, NULL, cliprects, num_cliprects, DR4,
2487 drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx,
2488 int used, unsigned int flags)
2490 return do_exec2(bo, used, ctx, NULL, 0, 0, -1, NULL, flags);
2494 drm_intel_gem_bo_fence_exec(drm_intel_bo *bo,
2495 drm_intel_context *ctx,
2501 return do_exec2(bo, used, ctx, NULL, 0, 0, in_fence, out_fence, flags);
2505 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
2507 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2508 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2509 struct drm_i915_gem_pin pin;
2513 pin.handle = bo_gem->gem_handle;
2514 pin.alignment = alignment;
2516 ret = drmIoctl(bufmgr_gem->fd,
2517 DRM_IOCTL_I915_GEM_PIN,
2522 bo->offset64 = pin.offset;
2523 bo->offset = pin.offset;
2528 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
2530 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2531 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2532 struct drm_i915_gem_unpin unpin;
2536 unpin.handle = bo_gem->gem_handle;
2538 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
2546 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
2547 uint32_t tiling_mode,
2550 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2551 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2552 struct drm_i915_gem_set_tiling set_tiling;
2555 if (bo_gem->global_name == 0 &&
2556 tiling_mode == bo_gem->tiling_mode &&
2557 stride == bo_gem->stride)
2560 memset(&set_tiling, 0, sizeof(set_tiling));
2562 /* set_tiling is slightly broken and overwrites the
2563 * input on the error path, so we have to open code
2566 set_tiling.handle = bo_gem->gem_handle;
2567 set_tiling.tiling_mode = tiling_mode;
2568 set_tiling.stride = stride;
2570 ret = ioctl(bufmgr_gem->fd,
2571 DRM_IOCTL_I915_GEM_SET_TILING,
2573 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
2577 bo_gem->tiling_mode = set_tiling.tiling_mode;
2578 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
2579 bo_gem->stride = set_tiling.stride;
2584 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
2587 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2588 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2591 /* Tiling with userptr surfaces is not supported
2592 * on all hardware so refuse it for time being.
2594 if (bo_gem->is_userptr)
2597 /* Linear buffers have no stride. By ensuring that we only ever use
2598 * stride 0 with linear buffers, we simplify our code.
2600 if (*tiling_mode == I915_TILING_NONE)
2603 ret = drm_intel_gem_bo_set_tiling_internal(bo, *tiling_mode, stride);
2605 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem, 0);
2607 *tiling_mode = bo_gem->tiling_mode;
2612 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
2613 uint32_t * swizzle_mode)
2615 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2617 *tiling_mode = bo_gem->tiling_mode;
2618 *swizzle_mode = bo_gem->swizzle_mode;
2623 drm_intel_gem_bo_set_softpin_offset(drm_intel_bo *bo, uint64_t offset)
2625 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2627 bo->offset64 = offset;
2628 bo->offset = offset;
2629 bo_gem->kflags |= EXEC_OBJECT_PINNED;
2635 drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr, int prime_fd, int size)
2637 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
2640 drm_intel_bo_gem *bo_gem;
2641 struct drm_i915_gem_get_tiling get_tiling;
2643 pthread_mutex_lock(&bufmgr_gem->lock);
2644 ret = drmPrimeFDToHandle(bufmgr_gem->fd, prime_fd, &handle);
2646 DBG("create_from_prime: failed to obtain handle from fd: %s\n", strerror(errno));
2647 pthread_mutex_unlock(&bufmgr_gem->lock);
2652 * See if the kernel has already returned this buffer to us. Just as
2653 * for named buffers, we must not create two bo's pointing at the same
2656 HASH_FIND(handle_hh, bufmgr_gem->handle_table,
2657 &handle, sizeof(handle), bo_gem);
2659 drm_intel_gem_bo_reference(&bo_gem->bo);
2663 bo_gem = calloc(1, sizeof(*bo_gem));
2667 atomic_set(&bo_gem->refcount, 1);
2668 DRMINITLISTHEAD(&bo_gem->vma_list);
2670 /* Determine size of bo. The fd-to-handle ioctl really should
2671 * return the size, but it doesn't. If we have kernel 3.12 or
2672 * later, we can lseek on the prime fd to get the size. Older
2673 * kernels will just fail, in which case we fall back to the
2674 * provided (estimated or guess size). */
2675 ret = lseek(prime_fd, 0, SEEK_END);
2677 bo_gem->bo.size = ret;
2679 bo_gem->bo.size = size;
2681 bo_gem->bo.handle = handle;
2682 bo_gem->bo.bufmgr = bufmgr;
2684 bo_gem->gem_handle = handle;
2685 HASH_ADD(handle_hh, bufmgr_gem->handle_table,
2686 gem_handle, sizeof(bo_gem->gem_handle), bo_gem);
2688 bo_gem->name = "prime";
2689 bo_gem->validate_index = -1;
2690 bo_gem->reloc_tree_fences = 0;
2691 bo_gem->used_as_reloc_target = false;
2692 bo_gem->has_error = false;
2693 bo_gem->reusable = false;
2695 memclear(get_tiling);
2696 get_tiling.handle = bo_gem->gem_handle;
2697 if (drmIoctl(bufmgr_gem->fd,
2698 DRM_IOCTL_I915_GEM_GET_TILING,
2702 bo_gem->tiling_mode = get_tiling.tiling_mode;
2703 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
2704 /* XXX stride is unknown */
2705 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem, 0);
2708 pthread_mutex_unlock(&bufmgr_gem->lock);
2712 drm_intel_gem_bo_free(&bo_gem->bo);
2713 pthread_mutex_unlock(&bufmgr_gem->lock);
2718 drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int *prime_fd)
2720 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2721 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2723 if (drmPrimeHandleToFD(bufmgr_gem->fd, bo_gem->gem_handle,
2724 DRM_CLOEXEC, prime_fd) != 0)
2727 bo_gem->reusable = false;
2733 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name)
2735 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2736 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2738 if (!bo_gem->global_name) {
2739 struct drm_gem_flink flink;
2742 flink.handle = bo_gem->gem_handle;
2743 if (drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink))
2746 pthread_mutex_lock(&bufmgr_gem->lock);
2747 if (!bo_gem->global_name) {
2748 bo_gem->global_name = flink.name;
2749 bo_gem->reusable = false;
2751 HASH_ADD(name_hh, bufmgr_gem->name_table,
2752 global_name, sizeof(bo_gem->global_name),
2755 pthread_mutex_unlock(&bufmgr_gem->lock);
2758 *name = bo_gem->global_name;
2763 * Enables unlimited caching of buffer objects for reuse.
2765 * This is potentially very memory expensive, as the cache at each bucket
2766 * size is only bounded by how many buffers of that size we've managed to have
2767 * in flight at once.
2770 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
2772 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
2774 bufmgr_gem->bo_reuse = true;
2778 * Disables implicit synchronisation before executing the bo
2780 * This will cause rendering corruption unless you correctly manage explicit
2781 * fences for all rendering involving this buffer - including use by others.
2782 * Disabling the implicit serialisation is only required if that serialisation
2783 * is too coarse (for example, you have split the buffer into many
2784 * non-overlapping regions and are sharing the whole buffer between concurrent
2785 * independent command streams).
2787 * Note the kernel must advertise support via I915_PARAM_HAS_EXEC_ASYNC,
2788 * which can be checked using drm_intel_bufmgr_can_disable_implicit_sync,
2789 * or subsequent execbufs involving the bo will generate EINVAL.
2792 drm_intel_gem_bo_disable_implicit_sync(drm_intel_bo *bo)
2794 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2796 bo_gem->kflags |= EXEC_OBJECT_ASYNC;
2800 * Enables implicit synchronisation before executing the bo
2802 * This is the default behaviour of the kernel, to wait upon prior writes
2803 * completing on the object before rendering with it, or to wait for prior
2804 * reads to complete before writing into the object.
2805 * drm_intel_gem_bo_disable_implicit_sync() can stop this behaviour, telling
2806 * the kernel never to insert a stall before using the object. Then this
2807 * function can be used to restore the implicit sync before subsequent
2811 drm_intel_gem_bo_enable_implicit_sync(drm_intel_bo *bo)
2813 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2815 bo_gem->kflags &= ~EXEC_OBJECT_ASYNC;
2819 * Query whether the kernel supports disabling of its implicit synchronisation
2820 * before execbuf. See drm_intel_gem_bo_disable_implicit_sync()
2823 drm_intel_bufmgr_gem_can_disable_implicit_sync(drm_intel_bufmgr *bufmgr)
2825 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
2827 return bufmgr_gem->has_exec_async;
2831 * Enable use of fenced reloc type.
2833 * New code should enable this to avoid unnecessary fence register
2834 * allocation. If this option is not enabled, all relocs will have fence
2835 * register allocated.
2838 drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr)
2840 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2842 if (bufmgr_gem->bufmgr.bo_exec == drm_intel_gem_bo_exec2)
2843 bufmgr_gem->fenced_relocs = true;
2847 * Return the additional aperture space required by the tree of buffer objects
2851 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
2853 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2857 if (bo == NULL || bo_gem->included_in_check_aperture)
2861 bo_gem->included_in_check_aperture = true;
2863 for (i = 0; i < bo_gem->reloc_count; i++)
2865 drm_intel_gem_bo_get_aperture_space(bo_gem->
2866 reloc_target_info[i].bo);
2872 * Count the number of buffers in this list that need a fence reg
2874 * If the count is greater than the number of available regs, we'll have
2875 * to ask the caller to resubmit a batch with fewer tiled buffers.
2877 * This function over-counts if the same buffer is used multiple times.
2880 drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count)
2883 unsigned int total = 0;
2885 for (i = 0; i < count; i++) {
2886 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
2891 total += bo_gem->reloc_tree_fences;
2897 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
2898 * for the next drm_intel_bufmgr_check_aperture_space() call.
2901 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
2903 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2906 if (bo == NULL || !bo_gem->included_in_check_aperture)
2909 bo_gem->included_in_check_aperture = false;
2911 for (i = 0; i < bo_gem->reloc_count; i++)
2912 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->
2913 reloc_target_info[i].bo);
2917 * Return a conservative estimate for the amount of aperture required
2918 * for a collection of buffers. This may double-count some buffers.
2921 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
2924 unsigned int total = 0;
2926 for (i = 0; i < count; i++) {
2927 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
2929 total += bo_gem->reloc_tree_size;
2935 * Return the amount of aperture needed for a collection of buffers.
2936 * This avoids double counting any buffers, at the cost of looking
2937 * at every buffer in the set.
2940 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
2943 unsigned int total = 0;
2945 for (i = 0; i < count; i++) {
2946 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
2947 /* For the first buffer object in the array, we get an
2948 * accurate count back for its reloc_tree size (since nothing
2949 * had been flagged as being counted yet). We can save that
2950 * value out as a more conservative reloc_tree_size that
2951 * avoids double-counting target buffers. Since the first
2952 * buffer happens to usually be the batch buffer in our
2953 * callers, this can pull us back from doing the tree
2954 * walk on every new batch emit.
2957 drm_intel_bo_gem *bo_gem =
2958 (drm_intel_bo_gem *) bo_array[i];
2959 bo_gem->reloc_tree_size = total;
2963 for (i = 0; i < count; i++)
2964 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
2969 * Return -1 if the batchbuffer should be flushed before attempting to
2970 * emit rendering referencing the buffers pointed to by bo_array.
2972 * This is required because if we try to emit a batchbuffer with relocations
2973 * to a tree of buffers that won't simultaneously fit in the aperture,
2974 * the rendering will return an error at a point where the software is not
2975 * prepared to recover from it.
2977 * However, we also want to emit the batchbuffer significantly before we reach
2978 * the limit, as a series of batchbuffers each of which references buffers
2979 * covering almost all of the aperture means that at each emit we end up
2980 * waiting to evict a buffer from the last rendering, and we get synchronous
2981 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
2982 * get better parallelism.
2985 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
2987 drm_intel_bufmgr_gem *bufmgr_gem =
2988 (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr;
2989 unsigned int total = 0;
2990 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
2993 /* Check for fence reg constraints if necessary */
2994 if (bufmgr_gem->available_fences) {
2995 total_fences = drm_intel_gem_total_fences(bo_array, count);
2996 if (total_fences > bufmgr_gem->available_fences)
3000 total = drm_intel_gem_estimate_batch_space(bo_array, count);
3002 if (total > threshold)
3003 total = drm_intel_gem_compute_batch_space(bo_array, count);
3005 if (total > threshold) {
3006 DBG("check_space: overflowed available aperture, "
3008 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
3011 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024,
3012 (int)bufmgr_gem->gtt_size / 1024);
3018 * Disable buffer reuse for objects which are shared with the kernel
3019 * as scanout buffers
3022 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
3024 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
3026 bo_gem->reusable = false;
3031 drm_intel_gem_bo_is_reusable(drm_intel_bo *bo)
3033 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
3035 return bo_gem->reusable;
3039 _drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
3041 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
3044 for (i = 0; i < bo_gem->reloc_count; i++) {
3045 if (bo_gem->reloc_target_info[i].bo == target_bo)
3047 if (bo == bo_gem->reloc_target_info[i].bo)
3049 if (_drm_intel_gem_bo_references(bo_gem->reloc_target_info[i].bo,
3054 for (i = 0; i< bo_gem->softpin_target_count; i++) {
3055 if (bo_gem->softpin_target[i] == target_bo)
3057 if (_drm_intel_gem_bo_references(bo_gem->softpin_target[i], target_bo))
3064 /** Return true if target_bo is referenced by bo's relocation tree. */
3066 drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
3068 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
3070 if (bo == NULL || target_bo == NULL)
3072 if (target_bo_gem->used_as_reloc_target)
3073 return _drm_intel_gem_bo_references(bo, target_bo);
3078 add_bucket(drm_intel_bufmgr_gem *bufmgr_gem, int size)
3080 unsigned int i = bufmgr_gem->num_buckets;
3082 assert(i < ARRAY_SIZE(bufmgr_gem->cache_bucket));
3084 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
3085 bufmgr_gem->cache_bucket[i].size = size;
3086 bufmgr_gem->num_buckets++;
3090 init_cache_buckets(drm_intel_bufmgr_gem *bufmgr_gem)
3092 unsigned long size, cache_max_size = 64 * 1024 * 1024;
3094 /* OK, so power of two buckets was too wasteful of memory.
3095 * Give 3 other sizes between each power of two, to hopefully
3096 * cover things accurately enough. (The alternative is
3097 * probably to just go for exact matching of sizes, and assume
3098 * that for things like composited window resize the tiled
3099 * width/height alignment and rounding of sizes to pages will
3100 * get us useful cache hit rates anyway)
3102 add_bucket(bufmgr_gem, 4096);
3103 add_bucket(bufmgr_gem, 4096 * 2);
3104 add_bucket(bufmgr_gem, 4096 * 3);
3106 /* Initialize the linked lists for BO reuse cache. */
3107 for (size = 4 * 4096; size <= cache_max_size; size *= 2) {
3108 add_bucket(bufmgr_gem, size);
3110 add_bucket(bufmgr_gem, size + size * 1 / 4);
3111 add_bucket(bufmgr_gem, size + size * 2 / 4);
3112 add_bucket(bufmgr_gem, size + size * 3 / 4);
3117 drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr, int limit)
3119 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3121 bufmgr_gem->vma_max = limit;
3123 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
3127 parse_devid_override(const char *devid_override)
3129 static const struct {
3133 { "brw", PCI_CHIP_I965_GM },
3134 { "g4x", PCI_CHIP_GM45_GM },
3135 { "ilk", PCI_CHIP_ILD_G },
3136 { "snb", PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS },
3137 { "ivb", PCI_CHIP_IVYBRIDGE_S_GT2 },
3138 { "hsw", PCI_CHIP_HASWELL_CRW_E_GT3 },
3139 { "byt", PCI_CHIP_VALLEYVIEW_3 },
3140 { "bdw", 0x1620 | BDW_ULX },
3141 { "skl", PCI_CHIP_SKYLAKE_DT_GT2 },
3142 { "kbl", PCI_CHIP_KABYLAKE_DT_GT2 },
3146 for (i = 0; i < ARRAY_SIZE(name_map); i++) {
3147 if (!strcmp(name_map[i].name, devid_override))
3148 return name_map[i].pci_id;
3151 return strtod(devid_override, NULL);
3155 * Get the PCI ID for the device. This can be overridden by setting the
3156 * INTEL_DEVID_OVERRIDE environment variable to the desired ID.
3159 get_pci_device_id(drm_intel_bufmgr_gem *bufmgr_gem)
3161 char *devid_override;
3164 drm_i915_getparam_t gp;
3166 if (geteuid() == getuid()) {
3167 devid_override = getenv("INTEL_DEVID_OVERRIDE");
3168 if (devid_override) {
3169 bufmgr_gem->no_exec = true;
3170 return parse_devid_override(devid_override);
3175 gp.param = I915_PARAM_CHIPSET_ID;
3177 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3179 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
3180 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
3186 drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr)
3188 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3190 return bufmgr_gem->pci_device;
3194 * Sets the AUB filename.
3196 * This function has to be called before drm_intel_bufmgr_gem_set_aub_dump()
3197 * for it to have any effect.
3200 drm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr,
3201 const char *filename)
3206 * Sets up AUB dumping.
3208 * This is a trace file format that can be used with the simulator.
3209 * Packets are emitted in a format somewhat like GPU command packets.
3210 * You can set up a GTT and upload your objects into the referenced
3211 * space, then send off batchbuffers and get BMPs out the other end.
3214 drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable)
3216 fprintf(stderr, "libdrm aub dumping is deprecated.\n\n"
3217 "Use intel_aubdump from intel-gpu-tools instead. Install intel-gpu-tools,\n"
3218 "then run (for example)\n\n"
3219 "\t$ intel_aubdump --output=trace.aub glxgears -geometry 500x500\n\n"
3220 "See the intel_aubdump man page for more details.\n");
3224 drm_intel_gem_context_create(drm_intel_bufmgr *bufmgr)
3226 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3227 struct drm_i915_gem_context_create create;
3228 drm_intel_context *context = NULL;
3231 context = calloc(1, sizeof(*context));
3236 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE, &create);
3238 DBG("DRM_IOCTL_I915_GEM_CONTEXT_CREATE failed: %s\n",
3244 context->ctx_id = create.ctx_id;
3245 context->bufmgr = bufmgr;
3251 drm_intel_gem_context_get_id(drm_intel_context *ctx, uint32_t *ctx_id)
3256 *ctx_id = ctx->ctx_id;
3262 drm_intel_gem_context_destroy(drm_intel_context *ctx)
3264 drm_intel_bufmgr_gem *bufmgr_gem;
3265 struct drm_i915_gem_context_destroy destroy;
3273 bufmgr_gem = (drm_intel_bufmgr_gem *)ctx->bufmgr;
3274 destroy.ctx_id = ctx->ctx_id;
3275 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_CONTEXT_DESTROY,
3278 fprintf(stderr, "DRM_IOCTL_I915_GEM_CONTEXT_DESTROY failed: %s\n",
3285 drm_intel_get_reset_stats(drm_intel_context *ctx,
3286 uint32_t *reset_count,
3290 drm_intel_bufmgr_gem *bufmgr_gem;
3291 struct drm_i915_reset_stats stats;
3299 bufmgr_gem = (drm_intel_bufmgr_gem *)ctx->bufmgr;
3300 stats.ctx_id = ctx->ctx_id;
3301 ret = drmIoctl(bufmgr_gem->fd,
3302 DRM_IOCTL_I915_GET_RESET_STATS,
3305 if (reset_count != NULL)
3306 *reset_count = stats.reset_count;
3309 *active = stats.batch_active;
3311 if (pending != NULL)
3312 *pending = stats.batch_pending;
3319 drm_intel_reg_read(drm_intel_bufmgr *bufmgr,
3323 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3324 struct drm_i915_reg_read reg_read;
3328 reg_read.offset = offset;
3330 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_REG_READ, ®_read);
3332 *result = reg_read.val;
3337 drm_intel_get_subslice_total(int fd, unsigned int *subslice_total)
3339 drm_i915_getparam_t gp;
3343 gp.value = (int*)subslice_total;
3344 gp.param = I915_PARAM_SUBSLICE_TOTAL;
3345 ret = drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
3353 drm_intel_get_eu_total(int fd, unsigned int *eu_total)
3355 drm_i915_getparam_t gp;
3359 gp.value = (int*)eu_total;
3360 gp.param = I915_PARAM_EU_TOTAL;
3361 ret = drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
3369 drm_intel_get_pooled_eu(int fd)
3371 drm_i915_getparam_t gp;
3375 gp.param = I915_PARAM_HAS_POOLED_EU;
3377 if (drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, &gp))
3384 drm_intel_get_min_eu_in_pool(int fd)
3386 drm_i915_getparam_t gp;
3390 gp.param = I915_PARAM_MIN_EU_IN_POOL;
3392 if (drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, &gp))
3399 * Annotate the given bo for use in aub dumping.
3401 * \param annotations is an array of drm_intel_aub_annotation objects
3402 * describing the type of data in various sections of the bo. Each
3403 * element of the array specifies the type and subtype of a section of
3404 * the bo, and the past-the-end offset of that section. The elements
3405 * of \c annotations must be sorted so that ending_offset is
3408 * \param count is the number of elements in the \c annotations array.
3409 * If \c count is zero, then \c annotations will not be dereferenced.
3411 * Annotations are copied into a private data structure, so caller may
3412 * re-use the memory pointed to by \c annotations after the call
3415 * Annotations are stored for the lifetime of the bo; to reset to the
3416 * default state (no annotations), call this function with a \c count
3420 drm_intel_bufmgr_gem_set_aub_annotations(drm_intel_bo *bo,
3421 drm_intel_aub_annotation *annotations,
3426 static pthread_mutex_t bufmgr_list_mutex = PTHREAD_MUTEX_INITIALIZER;
3427 static drmMMListHead bufmgr_list = { &bufmgr_list, &bufmgr_list };
3429 static drm_intel_bufmgr_gem *
3430 drm_intel_bufmgr_gem_find(int fd)
3432 drm_intel_bufmgr_gem *bufmgr_gem;
3434 DRMLISTFOREACHENTRY(bufmgr_gem, &bufmgr_list, managers) {
3435 if (bufmgr_gem->fd == fd) {
3436 atomic_inc(&bufmgr_gem->refcount);
3445 drm_intel_bufmgr_gem_unref(drm_intel_bufmgr *bufmgr)
3447 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3449 if (atomic_add_unless(&bufmgr_gem->refcount, -1, 1)) {
3450 pthread_mutex_lock(&bufmgr_list_mutex);
3452 if (atomic_dec_and_test(&bufmgr_gem->refcount)) {
3453 DRMLISTDEL(&bufmgr_gem->managers);
3454 drm_intel_bufmgr_gem_destroy(bufmgr);
3457 pthread_mutex_unlock(&bufmgr_list_mutex);
3461 void *drm_intel_gem_bo_map__gtt(drm_intel_bo *bo)
3463 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
3464 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
3466 if (bo_gem->gtt_virtual)
3467 return bo_gem->gtt_virtual;
3469 if (bo_gem->is_userptr)
3472 pthread_mutex_lock(&bufmgr_gem->lock);
3473 if (bo_gem->gtt_virtual == NULL) {
3474 struct drm_i915_gem_mmap_gtt mmap_arg;
3477 DBG("bo_map_gtt: mmap %d (%s), map_count=%d\n",
3478 bo_gem->gem_handle, bo_gem->name, bo_gem->map_count);
3480 if (bo_gem->map_count++ == 0)
3481 drm_intel_gem_bo_open_vma(bufmgr_gem, bo_gem);
3484 mmap_arg.handle = bo_gem->gem_handle;
3486 /* Get the fake offset back... */
3488 if (drmIoctl(bufmgr_gem->fd,
3489 DRM_IOCTL_I915_GEM_MMAP_GTT,
3492 ptr = drm_mmap(0, bo->size, PROT_READ | PROT_WRITE,
3493 MAP_SHARED, bufmgr_gem->fd,
3496 if (ptr == MAP_FAILED) {
3497 if (--bo_gem->map_count == 0)
3498 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
3502 bo_gem->gtt_virtual = ptr;
3504 pthread_mutex_unlock(&bufmgr_gem->lock);
3506 return bo_gem->gtt_virtual;
3509 void *drm_intel_gem_bo_map__cpu(drm_intel_bo *bo)
3511 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
3512 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
3514 if (bo_gem->mem_virtual)
3515 return bo_gem->mem_virtual;
3517 if (bo_gem->is_userptr) {
3518 /* Return the same user ptr */
3519 return bo_gem->user_virtual;
3522 pthread_mutex_lock(&bufmgr_gem->lock);
3523 if (!bo_gem->mem_virtual) {
3524 struct drm_i915_gem_mmap mmap_arg;
3526 if (bo_gem->map_count++ == 0)
3527 drm_intel_gem_bo_open_vma(bufmgr_gem, bo_gem);
3529 DBG("bo_map: %d (%s), map_count=%d\n",
3530 bo_gem->gem_handle, bo_gem->name, bo_gem->map_count);
3533 mmap_arg.handle = bo_gem->gem_handle;
3534 mmap_arg.size = bo->size;
3535 if (drmIoctl(bufmgr_gem->fd,
3536 DRM_IOCTL_I915_GEM_MMAP,
3538 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
3539 __FILE__, __LINE__, bo_gem->gem_handle,
3540 bo_gem->name, strerror(errno));
3541 if (--bo_gem->map_count == 0)
3542 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
3544 VG(VALGRIND_MALLOCLIKE_BLOCK(mmap_arg.addr_ptr, mmap_arg.size, 0, 1));
3545 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
3548 pthread_mutex_unlock(&bufmgr_gem->lock);
3550 return bo_gem->mem_virtual;
3553 void *drm_intel_gem_bo_map__wc(drm_intel_bo *bo)
3555 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
3556 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
3558 if (bo_gem->wc_virtual)
3559 return bo_gem->wc_virtual;
3561 if (bo_gem->is_userptr)
3564 pthread_mutex_lock(&bufmgr_gem->lock);
3565 if (!bo_gem->wc_virtual) {
3566 struct drm_i915_gem_mmap mmap_arg;
3568 if (bo_gem->map_count++ == 0)
3569 drm_intel_gem_bo_open_vma(bufmgr_gem, bo_gem);
3571 DBG("bo_map: %d (%s), map_count=%d\n",
3572 bo_gem->gem_handle, bo_gem->name, bo_gem->map_count);
3575 mmap_arg.handle = bo_gem->gem_handle;
3576 mmap_arg.size = bo->size;
3577 mmap_arg.flags = I915_MMAP_WC;
3578 if (drmIoctl(bufmgr_gem->fd,
3579 DRM_IOCTL_I915_GEM_MMAP,
3581 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
3582 __FILE__, __LINE__, bo_gem->gem_handle,
3583 bo_gem->name, strerror(errno));
3584 if (--bo_gem->map_count == 0)
3585 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
3587 VG(VALGRIND_MALLOCLIKE_BLOCK(mmap_arg.addr_ptr, mmap_arg.size, 0, 1));
3588 bo_gem->wc_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
3591 pthread_mutex_unlock(&bufmgr_gem->lock);
3593 return bo_gem->wc_virtual;
3597 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
3598 * and manage map buffer objections.
3600 * \param fd File descriptor of the opened DRM device.
3603 drm_intel_bufmgr_gem_init(int fd, int batch_size)
3605 drm_intel_bufmgr_gem *bufmgr_gem;
3606 struct drm_i915_gem_get_aperture aperture;
3607 drm_i915_getparam_t gp;
3611 pthread_mutex_lock(&bufmgr_list_mutex);
3613 bufmgr_gem = drm_intel_bufmgr_gem_find(fd);
3617 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
3618 if (bufmgr_gem == NULL)
3621 bufmgr_gem->fd = fd;
3622 atomic_set(&bufmgr_gem->refcount, 1);
3624 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
3631 ret = drmIoctl(bufmgr_gem->fd,
3632 DRM_IOCTL_I915_GEM_GET_APERTURE,
3636 bufmgr_gem->gtt_size = aperture.aper_available_size;
3638 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
3640 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
3641 fprintf(stderr, "Assuming %dkB available aperture size.\n"
3642 "May lead to reduced performance or incorrect "
3644 (int)bufmgr_gem->gtt_size / 1024);
3647 bufmgr_gem->pci_device = get_pci_device_id(bufmgr_gem);
3649 if (IS_GEN2(bufmgr_gem->pci_device))
3650 bufmgr_gem->gen = 2;
3651 else if (IS_GEN3(bufmgr_gem->pci_device))
3652 bufmgr_gem->gen = 3;
3653 else if (IS_GEN4(bufmgr_gem->pci_device))
3654 bufmgr_gem->gen = 4;
3655 else if (IS_GEN5(bufmgr_gem->pci_device))
3656 bufmgr_gem->gen = 5;
3657 else if (IS_GEN6(bufmgr_gem->pci_device))
3658 bufmgr_gem->gen = 6;
3659 else if (IS_GEN7(bufmgr_gem->pci_device))
3660 bufmgr_gem->gen = 7;
3661 else if (IS_GEN8(bufmgr_gem->pci_device))
3662 bufmgr_gem->gen = 8;
3663 else if (IS_GEN9(bufmgr_gem->pci_device))
3664 bufmgr_gem->gen = 9;
3665 else if (IS_GEN10(bufmgr_gem->pci_device))
3666 bufmgr_gem->gen = 10;
3673 if (IS_GEN3(bufmgr_gem->pci_device) &&
3674 bufmgr_gem->gtt_size > 256*1024*1024) {
3675 /* The unmappable part of gtt on gen 3 (i.e. above 256MB) can't
3676 * be used for tiled blits. To simplify the accounting, just
3677 * subtract the unmappable part (fixed to 256MB on all known
3678 * gen3 devices) if the kernel advertises it. */
3679 bufmgr_gem->gtt_size -= 256*1024*1024;
3685 gp.param = I915_PARAM_HAS_EXECBUF2;
3686 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3690 gp.param = I915_PARAM_HAS_BSD;
3691 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3692 bufmgr_gem->has_bsd = ret == 0;
3694 gp.param = I915_PARAM_HAS_BLT;
3695 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3696 bufmgr_gem->has_blt = ret == 0;
3698 gp.param = I915_PARAM_HAS_RELAXED_FENCING;
3699 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3700 bufmgr_gem->has_relaxed_fencing = ret == 0;
3702 gp.param = I915_PARAM_HAS_EXEC_ASYNC;
3703 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3704 bufmgr_gem->has_exec_async = ret == 0;
3706 bufmgr_gem->bufmgr.bo_alloc_userptr = check_bo_alloc_userptr;
3708 gp.param = I915_PARAM_HAS_WAIT_TIMEOUT;
3709 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3710 bufmgr_gem->has_wait_timeout = ret == 0;
3712 gp.param = I915_PARAM_HAS_LLC;
3713 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3715 /* Kernel does not supports HAS_LLC query, fallback to GPU
3716 * generation detection and assume that we have LLC on GEN6/7
3718 bufmgr_gem->has_llc = (IS_GEN6(bufmgr_gem->pci_device) |
3719 IS_GEN7(bufmgr_gem->pci_device));
3721 bufmgr_gem->has_llc = *gp.value;
3723 gp.param = I915_PARAM_HAS_VEBOX;
3724 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3725 bufmgr_gem->has_vebox = (ret == 0) & (*gp.value > 0);
3727 gp.param = I915_PARAM_HAS_EXEC_SOFTPIN;
3728 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3729 if (ret == 0 && *gp.value > 0)
3730 bufmgr_gem->bufmgr.bo_set_softpin_offset = drm_intel_gem_bo_set_softpin_offset;
3732 if (bufmgr_gem->gen < 4) {
3733 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
3734 gp.value = &bufmgr_gem->available_fences;
3735 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3737 fprintf(stderr, "get fences failed: %d [%d]\n", ret,
3739 fprintf(stderr, "param: %d, val: %d\n", gp.param,
3741 bufmgr_gem->available_fences = 0;
3743 /* XXX The kernel reports the total number of fences,
3744 * including any that may be pinned.
3746 * We presume that there will be at least one pinned
3747 * fence for the scanout buffer, but there may be more
3748 * than one scanout and the user may be manually
3749 * pinning buffers. Let's move to execbuffer2 and
3750 * thereby forget the insanity of using fences...
3752 bufmgr_gem->available_fences -= 2;
3753 if (bufmgr_gem->available_fences < 0)
3754 bufmgr_gem->available_fences = 0;
3758 if (bufmgr_gem->gen >= 8) {
3759 gp.param = I915_PARAM_HAS_ALIASING_PPGTT;
3760 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3761 if (ret == 0 && *gp.value == 3)
3762 bufmgr_gem->bufmgr.bo_use_48b_address_range = drm_intel_gem_bo_use_48b_address_range;
3765 /* Let's go with one relocation per every 2 dwords (but round down a bit
3766 * since a power of two will mean an extra page allocation for the reloc
3769 * Every 4 was too few for the blender benchmark.
3771 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
3773 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
3774 bufmgr_gem->bufmgr.bo_alloc_for_render =
3775 drm_intel_gem_bo_alloc_for_render;
3776 bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled;
3777 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
3778 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
3779 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
3780 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
3781 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
3782 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
3783 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
3784 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
3785 bufmgr_gem->bufmgr.bo_emit_reloc_fence = drm_intel_gem_bo_emit_reloc_fence;
3786 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
3787 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
3788 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
3789 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
3790 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
3791 /* Use the new one if available */
3793 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec2;
3794 bufmgr_gem->bufmgr.bo_mrb_exec = drm_intel_gem_bo_mrb_exec2;
3796 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
3797 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
3798 bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise;
3799 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_unref;
3800 bufmgr_gem->bufmgr.debug = 0;
3801 bufmgr_gem->bufmgr.check_aperture_space =
3802 drm_intel_gem_check_aperture_space;
3803 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
3804 bufmgr_gem->bufmgr.bo_is_reusable = drm_intel_gem_bo_is_reusable;
3805 bufmgr_gem->bufmgr.get_pipe_from_crtc_id =
3806 drm_intel_gem_get_pipe_from_crtc_id;
3807 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
3809 init_cache_buckets(bufmgr_gem);
3811 DRMINITLISTHEAD(&bufmgr_gem->vma_cache);
3812 bufmgr_gem->vma_max = -1; /* unlimited by default */
3814 DRMLISTADD(&bufmgr_gem->managers, &bufmgr_list);
3817 pthread_mutex_unlock(&bufmgr_list_mutex);
3819 return bufmgr_gem != NULL ? &bufmgr_gem->bufmgr : NULL;