1 /**************************************************************************
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 **************************************************************************/
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
42 #include <xf86atomic.h>
50 #include <sys/ioctl.h>
53 #include <sys/types.h>
57 #include "libdrm_lists.h"
58 #include "intel_bufmgr.h"
59 #include "intel_bufmgr_priv.h"
60 #include "intel_chipset.h"
65 #define DBG(...) do { \
66 if (bufmgr_gem->bufmgr.debug) \
67 fprintf(stderr, __VA_ARGS__); \
70 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
72 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
74 struct drm_intel_gem_bo_bucket {
79 typedef struct _drm_intel_bufmgr_gem {
80 drm_intel_bufmgr bufmgr;
88 struct drm_i915_gem_exec_object *exec_objects;
89 struct drm_i915_gem_exec_object2 *exec2_objects;
90 drm_intel_bo **exec_bos;
94 /** Array of lists of cached gem objects of power-of-two sizes */
95 struct drm_intel_gem_bo_bucket cache_bucket[14 * 4];
102 int available_fences;
105 unsigned int has_bsd : 1;
106 unsigned int has_blt : 1;
107 unsigned int has_relaxed_fencing : 1;
108 unsigned int bo_reuse : 1;
110 } drm_intel_bufmgr_gem;
112 #define DRM_INTEL_RELOC_FENCE (1<<0)
114 typedef struct _drm_intel_reloc_target_info {
117 } drm_intel_reloc_target;
119 struct _drm_intel_bo_gem {
127 * Kenel-assigned global name for this object
129 unsigned int global_name;
130 drmMMListHead name_list;
133 * Index of the buffer within the validation list while preparing a
134 * batchbuffer execution.
139 * Current tiling mode
141 uint32_t tiling_mode;
142 uint32_t swizzle_mode;
143 unsigned long stride;
147 /** Array passed to the DRM containing relocation information. */
148 struct drm_i915_gem_relocation_entry *relocs;
150 * Array of info structs corresponding to relocs[i].target_handle etc
152 drm_intel_reloc_target *reloc_target_info;
153 /** Number of entries in relocs */
155 /** Mapped address for the buffer, saved across map/unmap cycles */
157 /** GTT virtual address for the buffer, saved across map/unmap cycles */
165 * Boolean of whether this BO and its children have been included in
166 * the current drm_intel_bufmgr_check_aperture_space() total.
168 bool included_in_check_aperture;
171 * Boolean of whether this buffer has been used as a relocation
172 * target and had its size accounted for, and thus can't have any
173 * further relocations added to it.
175 bool used_as_reloc_target;
178 * Boolean of whether we have encountered an error whilst building the relocation tree.
183 * Boolean of whether this buffer can be re-used
188 * Size in bytes of this buffer and its relocation descendents.
190 * Used to avoid costly tree walking in
191 * drm_intel_bufmgr_check_aperture in the common case.
196 * Number of potential fence registers required by this buffer and its
199 int reloc_tree_fences;
201 /** Flags that we may need to do the SW_FINSIH ioctl on unmap. */
202 bool mapped_cpu_write;
206 drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count);
209 drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count);
212 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
213 uint32_t * swizzle_mode);
216 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
217 uint32_t tiling_mode,
220 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
223 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo);
225 static void drm_intel_gem_bo_free(drm_intel_bo *bo);
228 drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
229 uint32_t *tiling_mode)
231 unsigned long min_size, max_size;
234 if (*tiling_mode == I915_TILING_NONE)
237 /* 965+ just need multiples of page size for tiling */
238 if (bufmgr_gem->gen >= 4)
239 return ROUND_UP_TO(size, 4096);
241 /* Older chips need powers of two, of at least 512k or 1M */
242 if (bufmgr_gem->gen == 3) {
243 min_size = 1024*1024;
244 max_size = 128*1024*1024;
247 max_size = 64*1024*1024;
250 if (size > max_size) {
251 *tiling_mode = I915_TILING_NONE;
255 /* Do we need to allocate every page for the fence? */
256 if (bufmgr_gem->has_relaxed_fencing)
257 return ROUND_UP_TO(size, 4096);
259 for (i = min_size; i < size; i <<= 1)
266 * Round a given pitch up to the minimum required for X tiling on a
267 * given chip. We use 512 as the minimum to allow for a later tiling
271 drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
272 unsigned long pitch, uint32_t *tiling_mode)
274 unsigned long tile_width;
277 /* If untiled, then just align it so that we can do rendering
278 * to it with the 3D engine.
280 if (*tiling_mode == I915_TILING_NONE)
281 return ALIGN(pitch, 64);
283 if (*tiling_mode == I915_TILING_X
284 || (IS_915(bufmgr_gem) && *tiling_mode == I915_TILING_Y))
289 /* 965 is flexible */
290 if (bufmgr_gem->gen >= 4)
291 return ROUND_UP_TO(pitch, tile_width);
293 /* The older hardware has a maximum pitch of 8192 with tiled
294 * surfaces, so fallback to untiled if it's too large.
297 *tiling_mode = I915_TILING_NONE;
298 return ALIGN(pitch, 64);
301 /* Pre-965 needs power of two tile width */
302 for (i = tile_width; i < pitch; i <<= 1)
308 static struct drm_intel_gem_bo_bucket *
309 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
314 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
315 struct drm_intel_gem_bo_bucket *bucket =
316 &bufmgr_gem->cache_bucket[i];
317 if (bucket->size >= size) {
326 drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
330 for (i = 0; i < bufmgr_gem->exec_count; i++) {
331 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
332 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
334 if (bo_gem->relocs == NULL) {
335 DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle,
340 for (j = 0; j < bo_gem->reloc_count; j++) {
341 drm_intel_bo *target_bo = bo_gem->reloc_target_info[j].bo;
342 drm_intel_bo_gem *target_gem =
343 (drm_intel_bo_gem *) target_bo;
345 DBG("%2d: %d (%s)@0x%08llx -> "
346 "%d (%s)@0x%08lx + 0x%08x\n",
348 bo_gem->gem_handle, bo_gem->name,
349 (unsigned long long)bo_gem->relocs[j].offset,
350 target_gem->gem_handle,
353 bo_gem->relocs[j].delta);
359 drm_intel_gem_bo_reference(drm_intel_bo *bo)
361 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
363 atomic_inc(&bo_gem->refcount);
367 * Adds the given buffer to the list of buffers to be validated (moved into the
368 * appropriate memory type) with the next batch submission.
370 * If a buffer is validated multiple times in a batch submission, it ends up
371 * with the intersection of the memory type flags and the union of the
375 drm_intel_add_validate_buffer(drm_intel_bo *bo)
377 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
378 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
381 if (bo_gem->validate_index != -1)
384 /* Extend the array of validation entries as necessary. */
385 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
386 int new_size = bufmgr_gem->exec_size * 2;
391 bufmgr_gem->exec_objects =
392 realloc(bufmgr_gem->exec_objects,
393 sizeof(*bufmgr_gem->exec_objects) * new_size);
394 bufmgr_gem->exec_bos =
395 realloc(bufmgr_gem->exec_bos,
396 sizeof(*bufmgr_gem->exec_bos) * new_size);
397 bufmgr_gem->exec_size = new_size;
400 index = bufmgr_gem->exec_count;
401 bo_gem->validate_index = index;
402 /* Fill in array entry */
403 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
404 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
405 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs;
406 bufmgr_gem->exec_objects[index].alignment = 0;
407 bufmgr_gem->exec_objects[index].offset = 0;
408 bufmgr_gem->exec_bos[index] = bo;
409 bufmgr_gem->exec_count++;
413 drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence)
415 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
416 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
419 if (bo_gem->validate_index != -1) {
421 bufmgr_gem->exec2_objects[bo_gem->validate_index].flags |=
422 EXEC_OBJECT_NEEDS_FENCE;
426 /* Extend the array of validation entries as necessary. */
427 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
428 int new_size = bufmgr_gem->exec_size * 2;
433 bufmgr_gem->exec2_objects =
434 realloc(bufmgr_gem->exec2_objects,
435 sizeof(*bufmgr_gem->exec2_objects) * new_size);
436 bufmgr_gem->exec_bos =
437 realloc(bufmgr_gem->exec_bos,
438 sizeof(*bufmgr_gem->exec_bos) * new_size);
439 bufmgr_gem->exec_size = new_size;
442 index = bufmgr_gem->exec_count;
443 bo_gem->validate_index = index;
444 /* Fill in array entry */
445 bufmgr_gem->exec2_objects[index].handle = bo_gem->gem_handle;
446 bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count;
447 bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
448 bufmgr_gem->exec2_objects[index].alignment = 0;
449 bufmgr_gem->exec2_objects[index].offset = 0;
450 bufmgr_gem->exec_bos[index] = bo;
451 bufmgr_gem->exec2_objects[index].flags = 0;
452 bufmgr_gem->exec2_objects[index].rsvd1 = 0;
453 bufmgr_gem->exec2_objects[index].rsvd2 = 0;
455 bufmgr_gem->exec2_objects[index].flags |=
456 EXEC_OBJECT_NEEDS_FENCE;
458 bufmgr_gem->exec_count++;
461 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
465 drm_intel_bo_gem_set_in_aperture_size(drm_intel_bufmgr_gem *bufmgr_gem,
466 drm_intel_bo_gem *bo_gem)
470 assert(!bo_gem->used_as_reloc_target);
472 /* The older chipsets are far-less flexible in terms of tiling,
473 * and require tiled buffer to be size aligned in the aperture.
474 * This means that in the worst possible case we will need a hole
475 * twice as large as the object in order for it to fit into the
476 * aperture. Optimal packing is for wimps.
478 size = bo_gem->bo.size;
479 if (bufmgr_gem->gen < 4 && bo_gem->tiling_mode != I915_TILING_NONE) {
482 if (bufmgr_gem->has_relaxed_fencing) {
483 if (bufmgr_gem->gen == 3)
484 min_size = 1024*1024;
488 while (min_size < size)
493 /* Account for worst-case alignment. */
497 bo_gem->reloc_tree_size = size;
501 drm_intel_setup_reloc_list(drm_intel_bo *bo)
503 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
504 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
505 unsigned int max_relocs = bufmgr_gem->max_relocs;
507 if (bo->size / 4 < max_relocs)
508 max_relocs = bo->size / 4;
510 bo_gem->relocs = malloc(max_relocs *
511 sizeof(struct drm_i915_gem_relocation_entry));
512 bo_gem->reloc_target_info = malloc(max_relocs *
513 sizeof(drm_intel_reloc_target));
514 if (bo_gem->relocs == NULL || bo_gem->reloc_target_info == NULL) {
515 bo_gem->has_error = true;
517 free (bo_gem->relocs);
518 bo_gem->relocs = NULL;
520 free (bo_gem->reloc_target_info);
521 bo_gem->reloc_target_info = NULL;
530 drm_intel_gem_bo_busy(drm_intel_bo *bo)
532 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
533 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
534 struct drm_i915_gem_busy busy;
537 memset(&busy, 0, sizeof(busy));
538 busy.handle = bo_gem->gem_handle;
540 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
542 return (ret == 0 && busy.busy);
546 drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem,
547 drm_intel_bo_gem *bo_gem, int state)
549 struct drm_i915_gem_madvise madv;
551 madv.handle = bo_gem->gem_handle;
554 drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
556 return madv.retained;
560 drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
562 return drm_intel_gem_bo_madvise_internal
563 ((drm_intel_bufmgr_gem *) bo->bufmgr,
564 (drm_intel_bo_gem *) bo,
568 /* drop the oldest entries that have been purged by the kernel */
570 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
571 struct drm_intel_gem_bo_bucket *bucket)
573 while (!DRMLISTEMPTY(&bucket->head)) {
574 drm_intel_bo_gem *bo_gem;
576 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
577 bucket->head.next, head);
578 if (drm_intel_gem_bo_madvise_internal
579 (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
582 DRMLISTDEL(&bo_gem->head);
583 drm_intel_gem_bo_free(&bo_gem->bo);
587 static drm_intel_bo *
588 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr,
592 uint32_t tiling_mode,
593 unsigned long stride)
595 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
596 drm_intel_bo_gem *bo_gem;
597 unsigned int page_size = getpagesize();
599 struct drm_intel_gem_bo_bucket *bucket;
600 bool alloc_from_cache;
601 unsigned long bo_size;
602 bool for_render = false;
604 if (flags & BO_ALLOC_FOR_RENDER)
607 /* Round the allocated size up to a power of two number of pages. */
608 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
610 /* If we don't have caching at this size, don't actually round the
613 if (bucket == NULL) {
615 if (bo_size < page_size)
618 bo_size = bucket->size;
621 pthread_mutex_lock(&bufmgr_gem->lock);
622 /* Get a buffer out of the cache if available */
624 alloc_from_cache = false;
625 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) {
627 /* Allocate new render-target BOs from the tail (MRU)
628 * of the list, as it will likely be hot in the GPU
629 * cache and in the aperture for us.
631 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
632 bucket->head.prev, head);
633 DRMLISTDEL(&bo_gem->head);
634 alloc_from_cache = true;
636 /* For non-render-target BOs (where we're probably
637 * going to map it first thing in order to fill it
638 * with data), check if the last BO in the cache is
639 * unbusy, and only reuse in that case. Otherwise,
640 * allocating a new buffer is probably faster than
641 * waiting for the GPU to finish.
643 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
644 bucket->head.next, head);
645 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
646 alloc_from_cache = true;
647 DRMLISTDEL(&bo_gem->head);
651 if (alloc_from_cache) {
652 if (!drm_intel_gem_bo_madvise_internal
653 (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) {
654 drm_intel_gem_bo_free(&bo_gem->bo);
655 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem,
660 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
663 drm_intel_gem_bo_free(&bo_gem->bo);
668 pthread_mutex_unlock(&bufmgr_gem->lock);
670 if (!alloc_from_cache) {
671 struct drm_i915_gem_create create;
673 bo_gem = calloc(1, sizeof(*bo_gem));
677 bo_gem->bo.size = bo_size;
678 memset(&create, 0, sizeof(create));
679 create.size = bo_size;
681 ret = drmIoctl(bufmgr_gem->fd,
682 DRM_IOCTL_I915_GEM_CREATE,
684 bo_gem->gem_handle = create.handle;
685 bo_gem->bo.handle = bo_gem->gem_handle;
690 bo_gem->bo.bufmgr = bufmgr;
692 bo_gem->tiling_mode = I915_TILING_NONE;
693 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
696 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
699 drm_intel_gem_bo_free(&bo_gem->bo);
703 DRMINITLISTHEAD(&bo_gem->name_list);
707 atomic_set(&bo_gem->refcount, 1);
708 bo_gem->validate_index = -1;
709 bo_gem->reloc_tree_fences = 0;
710 bo_gem->used_as_reloc_target = false;
711 bo_gem->has_error = false;
712 bo_gem->reusable = true;
714 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
716 DBG("bo_create: buf %d (%s) %ldb\n",
717 bo_gem->gem_handle, bo_gem->name, size);
722 static drm_intel_bo *
723 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
726 unsigned int alignment)
728 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
730 I915_TILING_NONE, 0);
733 static drm_intel_bo *
734 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr,
737 unsigned int alignment)
739 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0,
740 I915_TILING_NONE, 0);
743 static drm_intel_bo *
744 drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
745 int x, int y, int cpp, uint32_t *tiling_mode,
746 unsigned long *pitch, unsigned long flags)
748 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
749 unsigned long size, stride;
753 unsigned long aligned_y, height_alignment;
755 tiling = *tiling_mode;
757 /* If we're tiled, our allocations are in 8 or 32-row blocks,
758 * so failure to align our height means that we won't allocate
761 * If we're untiled, we still have to align to 2 rows high
762 * because the data port accesses 2x2 blocks even if the
763 * bottom row isn't to be rendered, so failure to align means
764 * we could walk off the end of the GTT and fault. This is
765 * documented on 965, and may be the case on older chipsets
766 * too so we try to be careful.
769 height_alignment = 2;
771 if (IS_GEN2(bufmgr_gem) && tiling != I915_TILING_NONE)
772 height_alignment = 16;
773 else if (tiling == I915_TILING_X
774 || (IS_915(bufmgr_gem) && tiling == I915_TILING_Y))
775 height_alignment = 8;
776 else if (tiling == I915_TILING_Y)
777 height_alignment = 32;
778 aligned_y = ALIGN(y, height_alignment);
781 stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, tiling_mode);
782 size = stride * aligned_y;
783 size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
784 } while (*tiling_mode != tiling);
787 if (tiling == I915_TILING_NONE)
790 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags,
795 * Returns a drm_intel_bo wrapping the given buffer object handle.
797 * This can be used when one application needs to pass a buffer object
801 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
805 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
806 drm_intel_bo_gem *bo_gem;
808 struct drm_gem_open open_arg;
809 struct drm_i915_gem_get_tiling get_tiling;
812 /* At the moment most applications only have a few named bo.
813 * For instance, in a DRI client only the render buffers passed
814 * between X and the client are named. And since X returns the
815 * alternating names for the front/back buffer a linear search
816 * provides a sufficiently fast match.
818 for (list = bufmgr_gem->named.next;
819 list != &bufmgr_gem->named;
821 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, list, name_list);
822 if (bo_gem->global_name == handle) {
823 drm_intel_gem_bo_reference(&bo_gem->bo);
828 bo_gem = calloc(1, sizeof(*bo_gem));
832 memset(&open_arg, 0, sizeof(open_arg));
833 open_arg.name = handle;
834 ret = drmIoctl(bufmgr_gem->fd,
838 DBG("Couldn't reference %s handle 0x%08x: %s\n",
839 name, handle, strerror(errno));
843 bo_gem->bo.size = open_arg.size;
844 bo_gem->bo.offset = 0;
845 bo_gem->bo.virtual = NULL;
846 bo_gem->bo.bufmgr = bufmgr;
848 atomic_set(&bo_gem->refcount, 1);
849 bo_gem->validate_index = -1;
850 bo_gem->gem_handle = open_arg.handle;
851 bo_gem->bo.handle = open_arg.handle;
852 bo_gem->global_name = handle;
853 bo_gem->reusable = false;
855 memset(&get_tiling, 0, sizeof(get_tiling));
856 get_tiling.handle = bo_gem->gem_handle;
857 ret = drmIoctl(bufmgr_gem->fd,
858 DRM_IOCTL_I915_GEM_GET_TILING,
861 drm_intel_gem_bo_unreference(&bo_gem->bo);
864 bo_gem->tiling_mode = get_tiling.tiling_mode;
865 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
866 /* XXX stride is unknown */
867 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
869 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
870 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
876 drm_intel_gem_bo_free(drm_intel_bo *bo)
878 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
879 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
880 struct drm_gem_close close;
883 /* Close this object */
884 memset(&close, 0, sizeof(close));
885 close.handle = bo_gem->gem_handle;
886 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
888 DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
889 bo_gem->gem_handle, bo_gem->name, strerror(errno));
894 /** Frees all cached buffers significantly older than @time. */
896 drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time)
900 if (bufmgr_gem->time == time)
903 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
904 struct drm_intel_gem_bo_bucket *bucket =
905 &bufmgr_gem->cache_bucket[i];
907 while (!DRMLISTEMPTY(&bucket->head)) {
908 drm_intel_bo_gem *bo_gem;
910 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
911 bucket->head.next, head);
912 if (time - bo_gem->free_time <= 1)
915 DRMLISTDEL(&bo_gem->head);
917 drm_intel_gem_bo_free(&bo_gem->bo);
921 bufmgr_gem->time = time;
925 drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
927 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
928 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
929 struct drm_intel_gem_bo_bucket *bucket;
932 /* Unreference all the target buffers */
933 for (i = 0; i < bo_gem->reloc_count; i++) {
934 if (bo_gem->reloc_target_info[i].bo != bo) {
935 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
936 reloc_target_info[i].bo,
940 bo_gem->reloc_count = 0;
941 bo_gem->used_as_reloc_target = false;
943 DBG("bo_unreference final: %d (%s)\n",
944 bo_gem->gem_handle, bo_gem->name);
946 /* release memory associated with this object */
947 if (bo_gem->reloc_target_info) {
948 free(bo_gem->reloc_target_info);
949 bo_gem->reloc_target_info = NULL;
951 if (bo_gem->relocs) {
952 free(bo_gem->relocs);
953 bo_gem->relocs = NULL;
956 DRMLISTDEL(&bo_gem->name_list);
958 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
959 /* Put the buffer into our internal cache for reuse if we can. */
960 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
961 drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem,
962 I915_MADV_DONTNEED)) {
963 bo_gem->free_time = time;
966 bo_gem->validate_index = -1;
968 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
970 drm_intel_gem_bo_free(bo);
974 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
977 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
979 assert(atomic_read(&bo_gem->refcount) > 0);
980 if (atomic_dec_and_test(&bo_gem->refcount))
981 drm_intel_gem_bo_unreference_final(bo, time);
984 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
986 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
988 assert(atomic_read(&bo_gem->refcount) > 0);
989 if (atomic_dec_and_test(&bo_gem->refcount)) {
990 drm_intel_bufmgr_gem *bufmgr_gem =
991 (drm_intel_bufmgr_gem *) bo->bufmgr;
992 struct timespec time;
994 clock_gettime(CLOCK_MONOTONIC, &time);
996 pthread_mutex_lock(&bufmgr_gem->lock);
997 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
998 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time.tv_sec);
999 pthread_mutex_unlock(&bufmgr_gem->lock);
1003 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
1005 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1006 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1007 struct drm_i915_gem_set_domain set_domain;
1010 pthread_mutex_lock(&bufmgr_gem->lock);
1012 if (!bo_gem->mem_virtual) {
1013 struct drm_i915_gem_mmap mmap_arg;
1015 DBG("bo_map: %d (%s)\n", bo_gem->gem_handle, bo_gem->name);
1016 assert(bo_gem->map_count == 0);
1018 memset(&mmap_arg, 0, sizeof(mmap_arg));
1019 mmap_arg.handle = bo_gem->gem_handle;
1020 mmap_arg.offset = 0;
1021 mmap_arg.size = bo->size;
1022 ret = drmIoctl(bufmgr_gem->fd,
1023 DRM_IOCTL_I915_GEM_MMAP,
1027 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1028 __FILE__, __LINE__, bo_gem->gem_handle,
1029 bo_gem->name, strerror(errno));
1030 pthread_mutex_unlock(&bufmgr_gem->lock);
1033 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
1035 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1036 bo_gem->mem_virtual);
1037 bo->virtual = bo_gem->mem_virtual;
1038 bo_gem->map_count++;
1040 set_domain.handle = bo_gem->gem_handle;
1041 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
1043 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
1045 set_domain.write_domain = 0;
1046 ret = drmIoctl(bufmgr_gem->fd,
1047 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1050 DBG("%s:%d: Error setting to CPU domain %d: %s\n",
1051 __FILE__, __LINE__, bo_gem->gem_handle,
1056 bo_gem->mapped_cpu_write = true;
1058 pthread_mutex_unlock(&bufmgr_gem->lock);
1063 int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
1065 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1066 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1067 struct drm_i915_gem_set_domain set_domain;
1070 pthread_mutex_lock(&bufmgr_gem->lock);
1072 /* Get a mapping of the buffer if we haven't before. */
1073 if (bo_gem->gtt_virtual == NULL) {
1074 struct drm_i915_gem_mmap_gtt mmap_arg;
1076 DBG("bo_map_gtt: mmap %d (%s)\n", bo_gem->gem_handle,
1078 assert(bo_gem->map_count == 0);
1080 memset(&mmap_arg, 0, sizeof(mmap_arg));
1081 mmap_arg.handle = bo_gem->gem_handle;
1083 /* Get the fake offset back... */
1084 ret = drmIoctl(bufmgr_gem->fd,
1085 DRM_IOCTL_I915_GEM_MMAP_GTT,
1089 DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n",
1091 bo_gem->gem_handle, bo_gem->name,
1093 pthread_mutex_unlock(&bufmgr_gem->lock);
1098 bo_gem->gtt_virtual = mmap(0, bo->size, PROT_READ | PROT_WRITE,
1099 MAP_SHARED, bufmgr_gem->fd,
1101 if (bo_gem->gtt_virtual == MAP_FAILED) {
1102 bo_gem->gtt_virtual = NULL;
1104 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1106 bo_gem->gem_handle, bo_gem->name,
1108 pthread_mutex_unlock(&bufmgr_gem->lock);
1113 bo->virtual = bo_gem->gtt_virtual;
1114 bo_gem->map_count++;
1116 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1117 bo_gem->gtt_virtual);
1119 /* Now move it to the GTT domain so that the CPU caches are flushed */
1120 set_domain.handle = bo_gem->gem_handle;
1121 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1122 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
1123 ret = drmIoctl(bufmgr_gem->fd,
1124 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1127 DBG("%s:%d: Error setting domain %d: %s\n",
1128 __FILE__, __LINE__, bo_gem->gem_handle,
1132 pthread_mutex_unlock(&bufmgr_gem->lock);
1137 static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
1139 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1140 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1141 struct drm_i915_gem_sw_finish sw_finish;
1147 pthread_mutex_lock(&bufmgr_gem->lock);
1149 if (bo_gem->mapped_cpu_write) {
1150 /* Cause a flush to happen if the buffer's pinned for
1151 * scanout, so the results show up in a timely manner.
1152 * Unlike GTT set domains, this only does work if the
1153 * buffer should be scanout-related.
1155 sw_finish.handle = bo_gem->gem_handle;
1156 ret = drmIoctl(bufmgr_gem->fd,
1157 DRM_IOCTL_I915_GEM_SW_FINISH,
1159 ret = ret == -1 ? -errno : 0;
1161 bo_gem->mapped_cpu_write = false;
1164 /* We need to unmap after every innovation as we cannot track
1165 * an open vma for every bo as that will exhaasut the system
1166 * limits and cause later failures.
1168 if (--bo_gem->map_count == 0) {
1169 if (bo_gem->mem_virtual) {
1170 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
1171 bo_gem->mem_virtual = NULL;
1173 if (bo_gem->gtt_virtual) {
1174 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
1175 bo_gem->gtt_virtual = NULL;
1180 pthread_mutex_unlock(&bufmgr_gem->lock);
1185 int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
1187 return drm_intel_gem_bo_unmap(bo);
1191 drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset,
1192 unsigned long size, const void *data)
1194 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1195 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1196 struct drm_i915_gem_pwrite pwrite;
1199 memset(&pwrite, 0, sizeof(pwrite));
1200 pwrite.handle = bo_gem->gem_handle;
1201 pwrite.offset = offset;
1203 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
1204 ret = drmIoctl(bufmgr_gem->fd,
1205 DRM_IOCTL_I915_GEM_PWRITE,
1209 DBG("%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
1210 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1211 (int)size, strerror(errno));
1218 drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
1220 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1221 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
1224 get_pipe_from_crtc_id.crtc_id = crtc_id;
1225 ret = drmIoctl(bufmgr_gem->fd,
1226 DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
1227 &get_pipe_from_crtc_id);
1229 /* We return -1 here to signal that we don't
1230 * know which pipe is associated with this crtc.
1231 * This lets the caller know that this information
1232 * isn't available; using the wrong pipe for
1233 * vblank waiting can cause the chipset to lock up
1238 return get_pipe_from_crtc_id.pipe;
1242 drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
1243 unsigned long size, void *data)
1245 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1246 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1247 struct drm_i915_gem_pread pread;
1250 memset(&pread, 0, sizeof(pread));
1251 pread.handle = bo_gem->gem_handle;
1252 pread.offset = offset;
1254 pread.data_ptr = (uint64_t) (uintptr_t) data;
1255 ret = drmIoctl(bufmgr_gem->fd,
1256 DRM_IOCTL_I915_GEM_PREAD,
1260 DBG("%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
1261 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1262 (int)size, strerror(errno));
1268 /** Waits for all GPU rendering with the object to have completed. */
1270 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
1272 drm_intel_gem_bo_start_gtt_access(bo, 1);
1276 * Sets the object to the GTT read and possibly write domain, used by the X
1277 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
1279 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
1280 * can do tiled pixmaps this way.
1283 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
1285 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1286 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1287 struct drm_i915_gem_set_domain set_domain;
1290 set_domain.handle = bo_gem->gem_handle;
1291 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1292 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
1293 ret = drmIoctl(bufmgr_gem->fd,
1294 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1297 DBG("%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
1298 __FILE__, __LINE__, bo_gem->gem_handle,
1299 set_domain.read_domains, set_domain.write_domain,
1305 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
1307 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1310 free(bufmgr_gem->exec2_objects);
1311 free(bufmgr_gem->exec_objects);
1312 free(bufmgr_gem->exec_bos);
1314 pthread_mutex_destroy(&bufmgr_gem->lock);
1316 /* Free any cached buffer objects we were going to reuse */
1317 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
1318 struct drm_intel_gem_bo_bucket *bucket =
1319 &bufmgr_gem->cache_bucket[i];
1320 drm_intel_bo_gem *bo_gem;
1322 while (!DRMLISTEMPTY(&bucket->head)) {
1323 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1324 bucket->head.next, head);
1325 DRMLISTDEL(&bo_gem->head);
1327 drm_intel_gem_bo_free(&bo_gem->bo);
1335 * Adds the target buffer to the validation list and adds the relocation
1336 * to the reloc_buffer's relocation list.
1338 * The relocation entry at the given offset must already contain the
1339 * precomputed relocation value, because the kernel will optimize out
1340 * the relocation entry write when the buffer hasn't moved from the
1341 * last known offset in target_bo.
1344 do_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1345 drm_intel_bo *target_bo, uint32_t target_offset,
1346 uint32_t read_domains, uint32_t write_domain,
1349 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1350 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1351 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1352 bool fenced_command;
1354 if (bo_gem->has_error)
1357 if (target_bo_gem->has_error) {
1358 bo_gem->has_error = true;
1362 /* We never use HW fences for rendering on 965+ */
1363 if (bufmgr_gem->gen >= 4)
1366 fenced_command = need_fence;
1367 if (target_bo_gem->tiling_mode == I915_TILING_NONE)
1370 /* Create a new relocation list if needed */
1371 if (bo_gem->relocs == NULL && drm_intel_setup_reloc_list(bo))
1374 /* Check overflow */
1375 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
1378 assert(offset <= bo->size - 4);
1379 assert((write_domain & (write_domain - 1)) == 0);
1381 /* Make sure that we're not adding a reloc to something whose size has
1382 * already been accounted for.
1384 assert(!bo_gem->used_as_reloc_target);
1385 if (target_bo_gem != bo_gem) {
1386 target_bo_gem->used_as_reloc_target = true;
1387 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
1389 /* An object needing a fence is a tiled buffer, so it won't have
1390 * relocs to other buffers.
1393 target_bo_gem->reloc_tree_fences = 1;
1394 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
1396 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
1397 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
1398 bo_gem->relocs[bo_gem->reloc_count].target_handle =
1399 target_bo_gem->gem_handle;
1400 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
1401 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
1402 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset;
1404 bo_gem->reloc_target_info[bo_gem->reloc_count].bo = target_bo;
1405 if (target_bo != bo)
1406 drm_intel_gem_bo_reference(target_bo);
1408 bo_gem->reloc_target_info[bo_gem->reloc_count].flags =
1409 DRM_INTEL_RELOC_FENCE;
1411 bo_gem->reloc_target_info[bo_gem->reloc_count].flags = 0;
1413 bo_gem->reloc_count++;
1419 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1420 drm_intel_bo *target_bo, uint32_t target_offset,
1421 uint32_t read_domains, uint32_t write_domain)
1423 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1425 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1426 read_domains, write_domain,
1427 !bufmgr_gem->fenced_relocs);
1431 drm_intel_gem_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
1432 drm_intel_bo *target_bo,
1433 uint32_t target_offset,
1434 uint32_t read_domains, uint32_t write_domain)
1436 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1437 read_domains, write_domain, true);
1441 drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo)
1443 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1445 return bo_gem->reloc_count;
1449 * Removes existing relocation entries in the BO after "start".
1451 * This allows a user to avoid a two-step process for state setup with
1452 * counting up all the buffer objects and doing a
1453 * drm_intel_bufmgr_check_aperture_space() before emitting any of the
1454 * relocations for the state setup. Instead, save the state of the
1455 * batchbuffer including drm_intel_gem_get_reloc_count(), emit all the
1456 * state, and then check if it still fits in the aperture.
1458 * Any further drm_intel_bufmgr_check_aperture_space() queries
1459 * involving this buffer in the tree are undefined after this call.
1462 drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start)
1464 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1466 struct timespec time;
1468 clock_gettime(CLOCK_MONOTONIC, &time);
1470 assert(bo_gem->reloc_count >= start);
1471 /* Unreference the cleared target buffers */
1472 for (i = start; i < bo_gem->reloc_count; i++) {
1473 if (bo_gem->reloc_target_info[i].bo != bo) {
1474 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
1475 reloc_target_info[i].bo,
1479 bo_gem->reloc_count = start;
1483 * Walk the tree of relocations rooted at BO and accumulate the list of
1484 * validations to be performed and update the relocation buffers with
1485 * index values into the validation list.
1488 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
1490 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1493 if (bo_gem->relocs == NULL)
1496 for (i = 0; i < bo_gem->reloc_count; i++) {
1497 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1499 if (target_bo == bo)
1502 /* Continue walking the tree depth-first. */
1503 drm_intel_gem_bo_process_reloc(target_bo);
1505 /* Add the target to the validate list */
1506 drm_intel_add_validate_buffer(target_bo);
1511 drm_intel_gem_bo_process_reloc2(drm_intel_bo *bo)
1513 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1516 if (bo_gem->relocs == NULL)
1519 for (i = 0; i < bo_gem->reloc_count; i++) {
1520 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1523 if (target_bo == bo)
1526 /* Continue walking the tree depth-first. */
1527 drm_intel_gem_bo_process_reloc2(target_bo);
1529 need_fence = (bo_gem->reloc_target_info[i].flags &
1530 DRM_INTEL_RELOC_FENCE);
1532 /* Add the target to the validate list */
1533 drm_intel_add_validate_buffer2(target_bo, need_fence);
1539 drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem)
1543 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1544 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1545 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1547 /* Update the buffer offset */
1548 if (bufmgr_gem->exec_objects[i].offset != bo->offset) {
1549 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1550 bo_gem->gem_handle, bo_gem->name, bo->offset,
1551 (unsigned long long)bufmgr_gem->exec_objects[i].
1553 bo->offset = bufmgr_gem->exec_objects[i].offset;
1559 drm_intel_update_buffer_offsets2 (drm_intel_bufmgr_gem *bufmgr_gem)
1563 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1564 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1565 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1567 /* Update the buffer offset */
1568 if (bufmgr_gem->exec2_objects[i].offset != bo->offset) {
1569 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1570 bo_gem->gem_handle, bo_gem->name, bo->offset,
1571 (unsigned long long)bufmgr_gem->exec2_objects[i].offset);
1572 bo->offset = bufmgr_gem->exec2_objects[i].offset;
1578 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
1579 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
1581 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1582 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1583 struct drm_i915_gem_execbuffer execbuf;
1586 if (bo_gem->has_error)
1589 pthread_mutex_lock(&bufmgr_gem->lock);
1590 /* Update indices and set up the validate list. */
1591 drm_intel_gem_bo_process_reloc(bo);
1593 /* Add the batch buffer to the validation list. There are no
1594 * relocations pointing to it.
1596 drm_intel_add_validate_buffer(bo);
1598 execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects;
1599 execbuf.buffer_count = bufmgr_gem->exec_count;
1600 execbuf.batch_start_offset = 0;
1601 execbuf.batch_len = used;
1602 execbuf.cliprects_ptr = (uintptr_t) cliprects;
1603 execbuf.num_cliprects = num_cliprects;
1607 ret = drmIoctl(bufmgr_gem->fd,
1608 DRM_IOCTL_I915_GEM_EXECBUFFER,
1612 if (errno == ENOSPC) {
1613 DBG("Execbuffer fails to pin. "
1614 "Estimate: %u. Actual: %u. Available: %u\n",
1615 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1618 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1621 (unsigned int)bufmgr_gem->gtt_size);
1624 drm_intel_update_buffer_offsets(bufmgr_gem);
1626 if (bufmgr_gem->bufmgr.debug)
1627 drm_intel_gem_dump_validation_list(bufmgr_gem);
1629 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1630 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1631 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1633 /* Disconnect the buffer from the validate list */
1634 bo_gem->validate_index = -1;
1635 bufmgr_gem->exec_bos[i] = NULL;
1637 bufmgr_gem->exec_count = 0;
1638 pthread_mutex_unlock(&bufmgr_gem->lock);
1644 drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used,
1645 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
1648 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1649 struct drm_i915_gem_execbuffer2 execbuf;
1652 switch (flags & 0x7) {
1656 if (!bufmgr_gem->has_blt)
1660 if (!bufmgr_gem->has_bsd)
1663 case I915_EXEC_RENDER:
1664 case I915_EXEC_DEFAULT:
1668 pthread_mutex_lock(&bufmgr_gem->lock);
1669 /* Update indices and set up the validate list. */
1670 drm_intel_gem_bo_process_reloc2(bo);
1672 /* Add the batch buffer to the validation list. There are no relocations
1675 drm_intel_add_validate_buffer2(bo, 0);
1677 execbuf.buffers_ptr = (uintptr_t)bufmgr_gem->exec2_objects;
1678 execbuf.buffer_count = bufmgr_gem->exec_count;
1679 execbuf.batch_start_offset = 0;
1680 execbuf.batch_len = used;
1681 execbuf.cliprects_ptr = (uintptr_t)cliprects;
1682 execbuf.num_cliprects = num_cliprects;
1685 execbuf.flags = flags;
1689 ret = drmIoctl(bufmgr_gem->fd,
1690 DRM_IOCTL_I915_GEM_EXECBUFFER2,
1694 if (ret == -ENOSPC) {
1695 DBG("Execbuffer fails to pin. "
1696 "Estimate: %u. Actual: %u. Available: %u\n",
1697 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1698 bufmgr_gem->exec_count),
1699 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1700 bufmgr_gem->exec_count),
1701 (unsigned int) bufmgr_gem->gtt_size);
1704 drm_intel_update_buffer_offsets2(bufmgr_gem);
1706 if (bufmgr_gem->bufmgr.debug)
1707 drm_intel_gem_dump_validation_list(bufmgr_gem);
1709 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1710 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1711 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1713 /* Disconnect the buffer from the validate list */
1714 bo_gem->validate_index = -1;
1715 bufmgr_gem->exec_bos[i] = NULL;
1717 bufmgr_gem->exec_count = 0;
1718 pthread_mutex_unlock(&bufmgr_gem->lock);
1724 drm_intel_gem_bo_exec2(drm_intel_bo *bo, int used,
1725 drm_clip_rect_t *cliprects, int num_cliprects,
1728 return drm_intel_gem_bo_mrb_exec2(bo, used,
1729 cliprects, num_cliprects, DR4,
1734 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
1736 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1737 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1738 struct drm_i915_gem_pin pin;
1741 memset(&pin, 0, sizeof(pin));
1742 pin.handle = bo_gem->gem_handle;
1743 pin.alignment = alignment;
1745 ret = drmIoctl(bufmgr_gem->fd,
1746 DRM_IOCTL_I915_GEM_PIN,
1751 bo->offset = pin.offset;
1756 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
1758 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1759 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1760 struct drm_i915_gem_unpin unpin;
1763 memset(&unpin, 0, sizeof(unpin));
1764 unpin.handle = bo_gem->gem_handle;
1766 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
1774 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
1775 uint32_t tiling_mode,
1778 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1779 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1780 struct drm_i915_gem_set_tiling set_tiling;
1783 if (bo_gem->global_name == 0 &&
1784 tiling_mode == bo_gem->tiling_mode &&
1785 stride == bo_gem->stride)
1788 memset(&set_tiling, 0, sizeof(set_tiling));
1790 /* set_tiling is slightly broken and overwrites the
1791 * input on the error path, so we have to open code
1794 set_tiling.handle = bo_gem->gem_handle;
1795 set_tiling.tiling_mode = tiling_mode;
1796 set_tiling.stride = stride;
1798 ret = ioctl(bufmgr_gem->fd,
1799 DRM_IOCTL_I915_GEM_SET_TILING,
1801 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
1805 bo_gem->tiling_mode = set_tiling.tiling_mode;
1806 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
1807 bo_gem->stride = set_tiling.stride;
1812 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1815 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1816 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1819 /* Linear buffers have no stride. By ensuring that we only ever use
1820 * stride 0 with linear buffers, we simplify our code.
1822 if (*tiling_mode == I915_TILING_NONE)
1825 ret = drm_intel_gem_bo_set_tiling_internal(bo, *tiling_mode, stride);
1827 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
1829 *tiling_mode = bo_gem->tiling_mode;
1834 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1835 uint32_t * swizzle_mode)
1837 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1839 *tiling_mode = bo_gem->tiling_mode;
1840 *swizzle_mode = bo_gem->swizzle_mode;
1845 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name)
1847 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1848 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1849 struct drm_gem_flink flink;
1852 if (!bo_gem->global_name) {
1853 memset(&flink, 0, sizeof(flink));
1854 flink.handle = bo_gem->gem_handle;
1856 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink);
1859 bo_gem->global_name = flink.name;
1860 bo_gem->reusable = false;
1862 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
1865 *name = bo_gem->global_name;
1870 * Enables unlimited caching of buffer objects for reuse.
1872 * This is potentially very memory expensive, as the cache at each bucket
1873 * size is only bounded by how many buffers of that size we've managed to have
1874 * in flight at once.
1877 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
1879 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1881 bufmgr_gem->bo_reuse = true;
1885 * Enable use of fenced reloc type.
1887 * New code should enable this to avoid unnecessary fence register
1888 * allocation. If this option is not enabled, all relocs will have fence
1889 * register allocated.
1892 drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr)
1894 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
1896 if (bufmgr_gem->bufmgr.bo_exec == drm_intel_gem_bo_exec2)
1897 bufmgr_gem->fenced_relocs = true;
1901 * Return the additional aperture space required by the tree of buffer objects
1905 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
1907 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1911 if (bo == NULL || bo_gem->included_in_check_aperture)
1915 bo_gem->included_in_check_aperture = true;
1917 for (i = 0; i < bo_gem->reloc_count; i++)
1919 drm_intel_gem_bo_get_aperture_space(bo_gem->
1920 reloc_target_info[i].bo);
1926 * Count the number of buffers in this list that need a fence reg
1928 * If the count is greater than the number of available regs, we'll have
1929 * to ask the caller to resubmit a batch with fewer tiled buffers.
1931 * This function over-counts if the same buffer is used multiple times.
1934 drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count)
1937 unsigned int total = 0;
1939 for (i = 0; i < count; i++) {
1940 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1945 total += bo_gem->reloc_tree_fences;
1951 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
1952 * for the next drm_intel_bufmgr_check_aperture_space() call.
1955 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
1957 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1960 if (bo == NULL || !bo_gem->included_in_check_aperture)
1963 bo_gem->included_in_check_aperture = false;
1965 for (i = 0; i < bo_gem->reloc_count; i++)
1966 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->
1967 reloc_target_info[i].bo);
1971 * Return a conservative estimate for the amount of aperture required
1972 * for a collection of buffers. This may double-count some buffers.
1975 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
1978 unsigned int total = 0;
1980 for (i = 0; i < count; i++) {
1981 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1983 total += bo_gem->reloc_tree_size;
1989 * Return the amount of aperture needed for a collection of buffers.
1990 * This avoids double counting any buffers, at the cost of looking
1991 * at every buffer in the set.
1994 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
1997 unsigned int total = 0;
1999 for (i = 0; i < count; i++) {
2000 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
2001 /* For the first buffer object in the array, we get an
2002 * accurate count back for its reloc_tree size (since nothing
2003 * had been flagged as being counted yet). We can save that
2004 * value out as a more conservative reloc_tree_size that
2005 * avoids double-counting target buffers. Since the first
2006 * buffer happens to usually be the batch buffer in our
2007 * callers, this can pull us back from doing the tree
2008 * walk on every new batch emit.
2011 drm_intel_bo_gem *bo_gem =
2012 (drm_intel_bo_gem *) bo_array[i];
2013 bo_gem->reloc_tree_size = total;
2017 for (i = 0; i < count; i++)
2018 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
2023 * Return -1 if the batchbuffer should be flushed before attempting to
2024 * emit rendering referencing the buffers pointed to by bo_array.
2026 * This is required because if we try to emit a batchbuffer with relocations
2027 * to a tree of buffers that won't simultaneously fit in the aperture,
2028 * the rendering will return an error at a point where the software is not
2029 * prepared to recover from it.
2031 * However, we also want to emit the batchbuffer significantly before we reach
2032 * the limit, as a series of batchbuffers each of which references buffers
2033 * covering almost all of the aperture means that at each emit we end up
2034 * waiting to evict a buffer from the last rendering, and we get synchronous
2035 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
2036 * get better parallelism.
2039 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
2041 drm_intel_bufmgr_gem *bufmgr_gem =
2042 (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr;
2043 unsigned int total = 0;
2044 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
2047 /* Check for fence reg constraints if necessary */
2048 if (bufmgr_gem->available_fences) {
2049 total_fences = drm_intel_gem_total_fences(bo_array, count);
2050 if (total_fences > bufmgr_gem->available_fences)
2054 total = drm_intel_gem_estimate_batch_space(bo_array, count);
2056 if (total > threshold)
2057 total = drm_intel_gem_compute_batch_space(bo_array, count);
2059 if (total > threshold) {
2060 DBG("check_space: overflowed available aperture, "
2062 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
2065 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024,
2066 (int)bufmgr_gem->gtt_size / 1024);
2072 * Disable buffer reuse for objects which are shared with the kernel
2073 * as scanout buffers
2076 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
2078 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2080 bo_gem->reusable = false;
2085 drm_intel_gem_bo_is_reusable(drm_intel_bo *bo)
2087 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2089 return bo_gem->reusable;
2093 _drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2095 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2098 for (i = 0; i < bo_gem->reloc_count; i++) {
2099 if (bo_gem->reloc_target_info[i].bo == target_bo)
2101 if (bo == bo_gem->reloc_target_info[i].bo)
2103 if (_drm_intel_gem_bo_references(bo_gem->reloc_target_info[i].bo,
2111 /** Return true if target_bo is referenced by bo's relocation tree. */
2113 drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2115 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
2117 if (bo == NULL || target_bo == NULL)
2119 if (target_bo_gem->used_as_reloc_target)
2120 return _drm_intel_gem_bo_references(bo, target_bo);
2125 add_bucket(drm_intel_bufmgr_gem *bufmgr_gem, int size)
2127 unsigned int i = bufmgr_gem->num_buckets;
2129 assert(i < ARRAY_SIZE(bufmgr_gem->cache_bucket));
2131 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
2132 bufmgr_gem->cache_bucket[i].size = size;
2133 bufmgr_gem->num_buckets++;
2137 init_cache_buckets(drm_intel_bufmgr_gem *bufmgr_gem)
2139 unsigned long size, cache_max_size = 64 * 1024 * 1024;
2141 /* OK, so power of two buckets was too wasteful of memory.
2142 * Give 3 other sizes between each power of two, to hopefully
2143 * cover things accurately enough. (The alternative is
2144 * probably to just go for exact matching of sizes, and assume
2145 * that for things like composited window resize the tiled
2146 * width/height alignment and rounding of sizes to pages will
2147 * get us useful cache hit rates anyway)
2149 add_bucket(bufmgr_gem, 4096);
2150 add_bucket(bufmgr_gem, 4096 * 2);
2151 add_bucket(bufmgr_gem, 4096 * 3);
2153 /* Initialize the linked lists for BO reuse cache. */
2154 for (size = 4 * 4096; size <= cache_max_size; size *= 2) {
2155 add_bucket(bufmgr_gem, size);
2157 add_bucket(bufmgr_gem, size + size * 1 / 4);
2158 add_bucket(bufmgr_gem, size + size * 2 / 4);
2159 add_bucket(bufmgr_gem, size + size * 3 / 4);
2164 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
2165 * and manage map buffer objections.
2167 * \param fd File descriptor of the opened DRM device.
2170 drm_intel_bufmgr_gem_init(int fd, int batch_size)
2172 drm_intel_bufmgr_gem *bufmgr_gem;
2173 struct drm_i915_gem_get_aperture aperture;
2174 drm_i915_getparam_t gp;
2178 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
2179 if (bufmgr_gem == NULL)
2182 bufmgr_gem->fd = fd;
2184 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
2189 ret = drmIoctl(bufmgr_gem->fd,
2190 DRM_IOCTL_I915_GEM_GET_APERTURE,
2194 bufmgr_gem->gtt_size = aperture.aper_available_size;
2196 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
2198 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
2199 fprintf(stderr, "Assuming %dkB available aperture size.\n"
2200 "May lead to reduced performance or incorrect "
2202 (int)bufmgr_gem->gtt_size / 1024);
2205 gp.param = I915_PARAM_CHIPSET_ID;
2206 gp.value = &bufmgr_gem->pci_device;
2207 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2209 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
2210 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
2213 if (IS_GEN2(bufmgr_gem))
2214 bufmgr_gem->gen = 2;
2215 else if (IS_GEN3(bufmgr_gem))
2216 bufmgr_gem->gen = 3;
2217 else if (IS_GEN4(bufmgr_gem))
2218 bufmgr_gem->gen = 4;
2220 bufmgr_gem->gen = 6;
2222 if (IS_GEN3(bufmgr_gem) && bufmgr_gem->gtt_size > 256*1024*1024) {
2223 /* The unmappable part of gtt on gen 3 (i.e. above 256MB) can't
2224 * be used for tiled blits. To simplify the accounting, just
2225 * substract the unmappable part (fixed to 256MB on all known
2226 * gen3 devices) if the kernel advertises it. */
2227 bufmgr_gem->gtt_size -= 256*1024*1024;
2232 gp.param = I915_PARAM_HAS_EXECBUF2;
2233 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2237 gp.param = I915_PARAM_HAS_BSD;
2238 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2239 bufmgr_gem->has_bsd = ret == 0;
2241 gp.param = I915_PARAM_HAS_BLT;
2242 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2243 bufmgr_gem->has_blt = ret == 0;
2245 gp.param = I915_PARAM_HAS_RELAXED_FENCING;
2246 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2247 bufmgr_gem->has_relaxed_fencing = ret == 0;
2249 if (bufmgr_gem->gen < 4) {
2250 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
2251 gp.value = &bufmgr_gem->available_fences;
2252 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2254 fprintf(stderr, "get fences failed: %d [%d]\n", ret,
2256 fprintf(stderr, "param: %d, val: %d\n", gp.param,
2258 bufmgr_gem->available_fences = 0;
2260 /* XXX The kernel reports the total number of fences,
2261 * including any that may be pinned.
2263 * We presume that there will be at least one pinned
2264 * fence for the scanout buffer, but there may be more
2265 * than one scanout and the user may be manually
2266 * pinning buffers. Let's move to execbuffer2 and
2267 * thereby forget the insanity of using fences...
2269 bufmgr_gem->available_fences -= 2;
2270 if (bufmgr_gem->available_fences < 0)
2271 bufmgr_gem->available_fences = 0;
2275 /* Let's go with one relocation per every 2 dwords (but round down a bit
2276 * since a power of two will mean an extra page allocation for the reloc
2279 * Every 4 was too few for the blender benchmark.
2281 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
2283 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
2284 bufmgr_gem->bufmgr.bo_alloc_for_render =
2285 drm_intel_gem_bo_alloc_for_render;
2286 bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled;
2287 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
2288 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
2289 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
2290 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
2291 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
2292 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
2293 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
2294 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
2295 bufmgr_gem->bufmgr.bo_emit_reloc_fence = drm_intel_gem_bo_emit_reloc_fence;
2296 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
2297 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
2298 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
2299 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
2300 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
2301 /* Use the new one if available */
2303 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec2;
2304 bufmgr_gem->bufmgr.bo_mrb_exec = drm_intel_gem_bo_mrb_exec2;
2306 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
2307 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
2308 bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise;
2309 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_destroy;
2310 bufmgr_gem->bufmgr.debug = 0;
2311 bufmgr_gem->bufmgr.check_aperture_space =
2312 drm_intel_gem_check_aperture_space;
2313 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
2314 bufmgr_gem->bufmgr.bo_is_reusable = drm_intel_gem_bo_is_reusable;
2315 bufmgr_gem->bufmgr.get_pipe_from_crtc_id =
2316 drm_intel_gem_get_pipe_from_crtc_id;
2317 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
2319 DRMINITLISTHEAD(&bufmgr_gem->named);
2320 init_cache_buckets(bufmgr_gem);
2322 return &bufmgr_gem->bufmgr;