1 /**************************************************************************
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 **************************************************************************/
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
42 #include <xf86atomic.h>
50 #include <sys/ioctl.h>
53 #include <sys/types.h>
57 #include "libdrm_lists.h"
58 #include "intel_bufmgr.h"
59 #include "intel_bufmgr_priv.h"
60 #include "intel_chipset.h"
65 #define DBG(...) do { \
66 if (bufmgr_gem->bufmgr.debug) \
67 fprintf(stderr, __VA_ARGS__); \
70 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
72 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
74 struct drm_intel_gem_bo_bucket {
79 typedef struct _drm_intel_bufmgr_gem {
80 drm_intel_bufmgr bufmgr;
88 struct drm_i915_gem_exec_object *exec_objects;
89 struct drm_i915_gem_exec_object2 *exec2_objects;
90 drm_intel_bo **exec_bos;
94 /** Array of lists of cached gem objects of power-of-two sizes */
95 struct drm_intel_gem_bo_bucket cache_bucket[14 * 4];
102 int available_fences;
105 unsigned int has_bsd : 1;
106 unsigned int has_blt : 1;
107 unsigned int has_relaxed_fencing : 1;
108 unsigned int bo_reuse : 1;
110 } drm_intel_bufmgr_gem;
112 #define DRM_INTEL_RELOC_FENCE (1<<0)
114 typedef struct _drm_intel_reloc_target_info {
117 } drm_intel_reloc_target;
119 struct _drm_intel_bo_gem {
127 * Kenel-assigned global name for this object
129 unsigned int global_name;
130 drmMMListHead name_list;
133 * Index of the buffer within the validation list while preparing a
134 * batchbuffer execution.
139 * Current tiling mode
141 uint32_t tiling_mode;
142 uint32_t swizzle_mode;
143 unsigned long stride;
147 /** Array passed to the DRM containing relocation information. */
148 struct drm_i915_gem_relocation_entry *relocs;
150 * Array of info structs corresponding to relocs[i].target_handle etc
152 drm_intel_reloc_target *reloc_target_info;
153 /** Number of entries in relocs */
155 /** Mapped address for the buffer, saved across map/unmap cycles */
157 /** GTT virtual address for the buffer, saved across map/unmap cycles */
164 * Boolean of whether this BO and its children have been included in
165 * the current drm_intel_bufmgr_check_aperture_space() total.
167 bool included_in_check_aperture;
170 * Boolean of whether this buffer has been used as a relocation
171 * target and had its size accounted for, and thus can't have any
172 * further relocations added to it.
174 bool used_as_reloc_target;
177 * Boolean of whether we have encountered an error whilst building the relocation tree.
182 * Boolean of whether this buffer can be re-used
187 * Size in bytes of this buffer and its relocation descendents.
189 * Used to avoid costly tree walking in
190 * drm_intel_bufmgr_check_aperture in the common case.
195 * Number of potential fence registers required by this buffer and its
198 int reloc_tree_fences;
200 /** Flags that we may need to do the SW_FINSIH ioctl on unmap. */
201 bool mapped_cpu_write;
205 drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count);
208 drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count);
211 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
212 uint32_t * swizzle_mode);
215 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
216 uint32_t tiling_mode,
219 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
222 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo);
224 static void drm_intel_gem_bo_free(drm_intel_bo *bo);
227 drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
228 uint32_t *tiling_mode)
230 unsigned long min_size, max_size;
233 if (*tiling_mode == I915_TILING_NONE)
236 /* 965+ just need multiples of page size for tiling */
237 if (bufmgr_gem->gen >= 4)
238 return ROUND_UP_TO(size, 4096);
240 /* Older chips need powers of two, of at least 512k or 1M */
241 if (bufmgr_gem->gen == 3) {
242 min_size = 1024*1024;
243 max_size = 128*1024*1024;
246 max_size = 64*1024*1024;
249 if (size > max_size) {
250 *tiling_mode = I915_TILING_NONE;
254 /* Do we need to allocate every page for the fence? */
255 if (bufmgr_gem->has_relaxed_fencing)
256 return ROUND_UP_TO(size, 4096);
258 for (i = min_size; i < size; i <<= 1)
265 * Round a given pitch up to the minimum required for X tiling on a
266 * given chip. We use 512 as the minimum to allow for a later tiling
270 drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
271 unsigned long pitch, uint32_t *tiling_mode)
273 unsigned long tile_width;
276 /* If untiled, then just align it so that we can do rendering
277 * to it with the 3D engine.
279 if (*tiling_mode == I915_TILING_NONE)
280 return ALIGN(pitch, 64);
282 if (*tiling_mode == I915_TILING_X
283 || (IS_915(bufmgr_gem) && *tiling_mode == I915_TILING_Y))
288 /* 965 is flexible */
289 if (bufmgr_gem->gen >= 4)
290 return ROUND_UP_TO(pitch, tile_width);
292 /* The older hardware has a maximum pitch of 8192 with tiled
293 * surfaces, so fallback to untiled if it's too large.
296 *tiling_mode = I915_TILING_NONE;
297 return ALIGN(pitch, 64);
300 /* Pre-965 needs power of two tile width */
301 for (i = tile_width; i < pitch; i <<= 1)
307 static struct drm_intel_gem_bo_bucket *
308 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
313 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
314 struct drm_intel_gem_bo_bucket *bucket =
315 &bufmgr_gem->cache_bucket[i];
316 if (bucket->size >= size) {
325 drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
329 for (i = 0; i < bufmgr_gem->exec_count; i++) {
330 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
331 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
333 if (bo_gem->relocs == NULL) {
334 DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle,
339 for (j = 0; j < bo_gem->reloc_count; j++) {
340 drm_intel_bo *target_bo = bo_gem->reloc_target_info[j].bo;
341 drm_intel_bo_gem *target_gem =
342 (drm_intel_bo_gem *) target_bo;
344 DBG("%2d: %d (%s)@0x%08llx -> "
345 "%d (%s)@0x%08lx + 0x%08x\n",
347 bo_gem->gem_handle, bo_gem->name,
348 (unsigned long long)bo_gem->relocs[j].offset,
349 target_gem->gem_handle,
352 bo_gem->relocs[j].delta);
358 drm_intel_gem_bo_reference(drm_intel_bo *bo)
360 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
362 atomic_inc(&bo_gem->refcount);
366 * Adds the given buffer to the list of buffers to be validated (moved into the
367 * appropriate memory type) with the next batch submission.
369 * If a buffer is validated multiple times in a batch submission, it ends up
370 * with the intersection of the memory type flags and the union of the
374 drm_intel_add_validate_buffer(drm_intel_bo *bo)
376 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
377 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
380 if (bo_gem->validate_index != -1)
383 /* Extend the array of validation entries as necessary. */
384 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
385 int new_size = bufmgr_gem->exec_size * 2;
390 bufmgr_gem->exec_objects =
391 realloc(bufmgr_gem->exec_objects,
392 sizeof(*bufmgr_gem->exec_objects) * new_size);
393 bufmgr_gem->exec_bos =
394 realloc(bufmgr_gem->exec_bos,
395 sizeof(*bufmgr_gem->exec_bos) * new_size);
396 bufmgr_gem->exec_size = new_size;
399 index = bufmgr_gem->exec_count;
400 bo_gem->validate_index = index;
401 /* Fill in array entry */
402 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
403 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
404 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs;
405 bufmgr_gem->exec_objects[index].alignment = 0;
406 bufmgr_gem->exec_objects[index].offset = 0;
407 bufmgr_gem->exec_bos[index] = bo;
408 bufmgr_gem->exec_count++;
412 drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence)
414 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
415 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
418 if (bo_gem->validate_index != -1) {
420 bufmgr_gem->exec2_objects[bo_gem->validate_index].flags |=
421 EXEC_OBJECT_NEEDS_FENCE;
425 /* Extend the array of validation entries as necessary. */
426 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
427 int new_size = bufmgr_gem->exec_size * 2;
432 bufmgr_gem->exec2_objects =
433 realloc(bufmgr_gem->exec2_objects,
434 sizeof(*bufmgr_gem->exec2_objects) * new_size);
435 bufmgr_gem->exec_bos =
436 realloc(bufmgr_gem->exec_bos,
437 sizeof(*bufmgr_gem->exec_bos) * new_size);
438 bufmgr_gem->exec_size = new_size;
441 index = bufmgr_gem->exec_count;
442 bo_gem->validate_index = index;
443 /* Fill in array entry */
444 bufmgr_gem->exec2_objects[index].handle = bo_gem->gem_handle;
445 bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count;
446 bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
447 bufmgr_gem->exec2_objects[index].alignment = 0;
448 bufmgr_gem->exec2_objects[index].offset = 0;
449 bufmgr_gem->exec_bos[index] = bo;
450 bufmgr_gem->exec2_objects[index].flags = 0;
451 bufmgr_gem->exec2_objects[index].rsvd1 = 0;
452 bufmgr_gem->exec2_objects[index].rsvd2 = 0;
454 bufmgr_gem->exec2_objects[index].flags |=
455 EXEC_OBJECT_NEEDS_FENCE;
457 bufmgr_gem->exec_count++;
460 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
464 drm_intel_bo_gem_set_in_aperture_size(drm_intel_bufmgr_gem *bufmgr_gem,
465 drm_intel_bo_gem *bo_gem)
469 assert(!bo_gem->used_as_reloc_target);
471 /* The older chipsets are far-less flexible in terms of tiling,
472 * and require tiled buffer to be size aligned in the aperture.
473 * This means that in the worst possible case we will need a hole
474 * twice as large as the object in order for it to fit into the
475 * aperture. Optimal packing is for wimps.
477 size = bo_gem->bo.size;
478 if (bufmgr_gem->gen < 4 && bo_gem->tiling_mode != I915_TILING_NONE) {
481 if (bufmgr_gem->has_relaxed_fencing) {
482 if (bufmgr_gem->gen == 3)
483 min_size = 1024*1024;
487 while (min_size < size)
492 /* Account for worst-case alignment. */
496 bo_gem->reloc_tree_size = size;
500 drm_intel_setup_reloc_list(drm_intel_bo *bo)
502 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
503 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
504 unsigned int max_relocs = bufmgr_gem->max_relocs;
506 if (bo->size / 4 < max_relocs)
507 max_relocs = bo->size / 4;
509 bo_gem->relocs = malloc(max_relocs *
510 sizeof(struct drm_i915_gem_relocation_entry));
511 bo_gem->reloc_target_info = malloc(max_relocs *
512 sizeof(drm_intel_reloc_target));
513 if (bo_gem->relocs == NULL || bo_gem->reloc_target_info == NULL) {
514 bo_gem->has_error = true;
516 free (bo_gem->relocs);
517 bo_gem->relocs = NULL;
519 free (bo_gem->reloc_target_info);
520 bo_gem->reloc_target_info = NULL;
529 drm_intel_gem_bo_busy(drm_intel_bo *bo)
531 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
532 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
533 struct drm_i915_gem_busy busy;
536 memset(&busy, 0, sizeof(busy));
537 busy.handle = bo_gem->gem_handle;
539 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
541 return (ret == 0 && busy.busy);
545 drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem,
546 drm_intel_bo_gem *bo_gem, int state)
548 struct drm_i915_gem_madvise madv;
550 madv.handle = bo_gem->gem_handle;
553 drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
555 return madv.retained;
559 drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
561 return drm_intel_gem_bo_madvise_internal
562 ((drm_intel_bufmgr_gem *) bo->bufmgr,
563 (drm_intel_bo_gem *) bo,
567 /* drop the oldest entries that have been purged by the kernel */
569 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
570 struct drm_intel_gem_bo_bucket *bucket)
572 while (!DRMLISTEMPTY(&bucket->head)) {
573 drm_intel_bo_gem *bo_gem;
575 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
576 bucket->head.next, head);
577 if (drm_intel_gem_bo_madvise_internal
578 (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
581 DRMLISTDEL(&bo_gem->head);
582 drm_intel_gem_bo_free(&bo_gem->bo);
586 static drm_intel_bo *
587 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr,
591 uint32_t tiling_mode,
592 unsigned long stride)
594 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
595 drm_intel_bo_gem *bo_gem;
596 unsigned int page_size = getpagesize();
598 struct drm_intel_gem_bo_bucket *bucket;
599 bool alloc_from_cache;
600 unsigned long bo_size;
601 bool for_render = false;
603 if (flags & BO_ALLOC_FOR_RENDER)
606 /* Round the allocated size up to a power of two number of pages. */
607 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
609 /* If we don't have caching at this size, don't actually round the
612 if (bucket == NULL) {
614 if (bo_size < page_size)
617 bo_size = bucket->size;
620 pthread_mutex_lock(&bufmgr_gem->lock);
621 /* Get a buffer out of the cache if available */
623 alloc_from_cache = false;
624 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) {
626 /* Allocate new render-target BOs from the tail (MRU)
627 * of the list, as it will likely be hot in the GPU
628 * cache and in the aperture for us.
630 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
631 bucket->head.prev, head);
632 DRMLISTDEL(&bo_gem->head);
633 alloc_from_cache = true;
635 /* For non-render-target BOs (where we're probably
636 * going to map it first thing in order to fill it
637 * with data), check if the last BO in the cache is
638 * unbusy, and only reuse in that case. Otherwise,
639 * allocating a new buffer is probably faster than
640 * waiting for the GPU to finish.
642 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
643 bucket->head.next, head);
644 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
645 alloc_from_cache = true;
646 DRMLISTDEL(&bo_gem->head);
650 if (alloc_from_cache) {
651 if (!drm_intel_gem_bo_madvise_internal
652 (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) {
653 drm_intel_gem_bo_free(&bo_gem->bo);
654 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem,
659 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
662 drm_intel_gem_bo_free(&bo_gem->bo);
667 pthread_mutex_unlock(&bufmgr_gem->lock);
669 if (!alloc_from_cache) {
670 struct drm_i915_gem_create create;
672 bo_gem = calloc(1, sizeof(*bo_gem));
676 bo_gem->bo.size = bo_size;
677 memset(&create, 0, sizeof(create));
678 create.size = bo_size;
680 ret = drmIoctl(bufmgr_gem->fd,
681 DRM_IOCTL_I915_GEM_CREATE,
683 bo_gem->gem_handle = create.handle;
684 bo_gem->bo.handle = bo_gem->gem_handle;
689 bo_gem->bo.bufmgr = bufmgr;
691 bo_gem->tiling_mode = I915_TILING_NONE;
692 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
695 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
698 drm_intel_gem_bo_free(&bo_gem->bo);
702 DRMINITLISTHEAD(&bo_gem->name_list);
706 atomic_set(&bo_gem->refcount, 1);
707 bo_gem->validate_index = -1;
708 bo_gem->reloc_tree_fences = 0;
709 bo_gem->used_as_reloc_target = false;
710 bo_gem->has_error = false;
711 bo_gem->reusable = true;
713 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
715 DBG("bo_create: buf %d (%s) %ldb\n",
716 bo_gem->gem_handle, bo_gem->name, size);
721 static drm_intel_bo *
722 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
725 unsigned int alignment)
727 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
729 I915_TILING_NONE, 0);
732 static drm_intel_bo *
733 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr,
736 unsigned int alignment)
738 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0,
739 I915_TILING_NONE, 0);
742 static drm_intel_bo *
743 drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
744 int x, int y, int cpp, uint32_t *tiling_mode,
745 unsigned long *pitch, unsigned long flags)
747 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
748 unsigned long size, stride;
752 unsigned long aligned_y, height_alignment;
754 tiling = *tiling_mode;
756 /* If we're tiled, our allocations are in 8 or 32-row blocks,
757 * so failure to align our height means that we won't allocate
760 * If we're untiled, we still have to align to 2 rows high
761 * because the data port accesses 2x2 blocks even if the
762 * bottom row isn't to be rendered, so failure to align means
763 * we could walk off the end of the GTT and fault. This is
764 * documented on 965, and may be the case on older chipsets
765 * too so we try to be careful.
768 height_alignment = 2;
770 if (IS_GEN2(bufmgr_gem) && tiling != I915_TILING_NONE)
771 height_alignment = 16;
772 else if (tiling == I915_TILING_X
773 || (IS_915(bufmgr_gem) && tiling == I915_TILING_Y))
774 height_alignment = 8;
775 else if (tiling == I915_TILING_Y)
776 height_alignment = 32;
777 aligned_y = ALIGN(y, height_alignment);
780 stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, tiling_mode);
781 size = stride * aligned_y;
782 size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
783 } while (*tiling_mode != tiling);
786 if (tiling == I915_TILING_NONE)
789 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags,
794 * Returns a drm_intel_bo wrapping the given buffer object handle.
796 * This can be used when one application needs to pass a buffer object
800 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
804 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
805 drm_intel_bo_gem *bo_gem;
807 struct drm_gem_open open_arg;
808 struct drm_i915_gem_get_tiling get_tiling;
811 /* At the moment most applications only have a few named bo.
812 * For instance, in a DRI client only the render buffers passed
813 * between X and the client are named. And since X returns the
814 * alternating names for the front/back buffer a linear search
815 * provides a sufficiently fast match.
817 for (list = bufmgr_gem->named.next;
818 list != &bufmgr_gem->named;
820 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, list, name_list);
821 if (bo_gem->global_name == handle) {
822 drm_intel_gem_bo_reference(&bo_gem->bo);
827 bo_gem = calloc(1, sizeof(*bo_gem));
831 memset(&open_arg, 0, sizeof(open_arg));
832 open_arg.name = handle;
833 ret = drmIoctl(bufmgr_gem->fd,
837 DBG("Couldn't reference %s handle 0x%08x: %s\n",
838 name, handle, strerror(errno));
842 bo_gem->bo.size = open_arg.size;
843 bo_gem->bo.offset = 0;
844 bo_gem->bo.virtual = NULL;
845 bo_gem->bo.bufmgr = bufmgr;
847 atomic_set(&bo_gem->refcount, 1);
848 bo_gem->validate_index = -1;
849 bo_gem->gem_handle = open_arg.handle;
850 bo_gem->bo.handle = open_arg.handle;
851 bo_gem->global_name = handle;
852 bo_gem->reusable = false;
854 memset(&get_tiling, 0, sizeof(get_tiling));
855 get_tiling.handle = bo_gem->gem_handle;
856 ret = drmIoctl(bufmgr_gem->fd,
857 DRM_IOCTL_I915_GEM_GET_TILING,
860 drm_intel_gem_bo_unreference(&bo_gem->bo);
863 bo_gem->tiling_mode = get_tiling.tiling_mode;
864 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
865 /* XXX stride is unknown */
866 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
868 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
869 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
875 drm_intel_gem_bo_free(drm_intel_bo *bo)
877 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
878 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
879 struct drm_gem_close close;
882 if (bo_gem->mem_virtual)
883 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
884 if (bo_gem->gtt_virtual)
885 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
887 /* Close this object */
888 memset(&close, 0, sizeof(close));
889 close.handle = bo_gem->gem_handle;
890 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
892 DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
893 bo_gem->gem_handle, bo_gem->name, strerror(errno));
898 /** Frees all cached buffers significantly older than @time. */
900 drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time)
904 if (bufmgr_gem->time == time)
907 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
908 struct drm_intel_gem_bo_bucket *bucket =
909 &bufmgr_gem->cache_bucket[i];
911 while (!DRMLISTEMPTY(&bucket->head)) {
912 drm_intel_bo_gem *bo_gem;
914 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
915 bucket->head.next, head);
916 if (time - bo_gem->free_time <= 1)
919 DRMLISTDEL(&bo_gem->head);
921 drm_intel_gem_bo_free(&bo_gem->bo);
925 bufmgr_gem->time = time;
929 drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
931 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
932 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
933 struct drm_intel_gem_bo_bucket *bucket;
936 /* Unreference all the target buffers */
937 for (i = 0; i < bo_gem->reloc_count; i++) {
938 if (bo_gem->reloc_target_info[i].bo != bo) {
939 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
940 reloc_target_info[i].bo,
944 bo_gem->reloc_count = 0;
945 bo_gem->used_as_reloc_target = false;
947 DBG("bo_unreference final: %d (%s)\n",
948 bo_gem->gem_handle, bo_gem->name);
950 /* release memory associated with this object */
951 if (bo_gem->reloc_target_info) {
952 free(bo_gem->reloc_target_info);
953 bo_gem->reloc_target_info = NULL;
955 if (bo_gem->relocs) {
956 free(bo_gem->relocs);
957 bo_gem->relocs = NULL;
960 DRMLISTDEL(&bo_gem->name_list);
962 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
963 /* Put the buffer into our internal cache for reuse if we can. */
964 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
965 drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem,
966 I915_MADV_DONTNEED)) {
967 bo_gem->free_time = time;
970 bo_gem->validate_index = -1;
972 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
974 drm_intel_gem_bo_free(bo);
978 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
981 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
983 assert(atomic_read(&bo_gem->refcount) > 0);
984 if (atomic_dec_and_test(&bo_gem->refcount))
985 drm_intel_gem_bo_unreference_final(bo, time);
988 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
990 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
992 assert(atomic_read(&bo_gem->refcount) > 0);
993 if (atomic_dec_and_test(&bo_gem->refcount)) {
994 drm_intel_bufmgr_gem *bufmgr_gem =
995 (drm_intel_bufmgr_gem *) bo->bufmgr;
996 struct timespec time;
998 clock_gettime(CLOCK_MONOTONIC, &time);
1000 pthread_mutex_lock(&bufmgr_gem->lock);
1001 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
1002 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time.tv_sec);
1003 pthread_mutex_unlock(&bufmgr_gem->lock);
1007 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
1009 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1010 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1011 struct drm_i915_gem_set_domain set_domain;
1014 pthread_mutex_lock(&bufmgr_gem->lock);
1016 if (!bo_gem->mem_virtual) {
1017 struct drm_i915_gem_mmap mmap_arg;
1019 DBG("bo_map: %d (%s)\n", bo_gem->gem_handle, bo_gem->name);
1021 memset(&mmap_arg, 0, sizeof(mmap_arg));
1022 mmap_arg.handle = bo_gem->gem_handle;
1023 mmap_arg.offset = 0;
1024 mmap_arg.size = bo->size;
1025 ret = drmIoctl(bufmgr_gem->fd,
1026 DRM_IOCTL_I915_GEM_MMAP,
1030 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1031 __FILE__, __LINE__, bo_gem->gem_handle,
1032 bo_gem->name, strerror(errno));
1033 pthread_mutex_unlock(&bufmgr_gem->lock);
1036 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
1038 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1039 bo_gem->mem_virtual);
1040 bo->virtual = bo_gem->mem_virtual;
1042 set_domain.handle = bo_gem->gem_handle;
1043 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
1045 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
1047 set_domain.write_domain = 0;
1048 ret = drmIoctl(bufmgr_gem->fd,
1049 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1052 DBG("%s:%d: Error setting to CPU domain %d: %s\n",
1053 __FILE__, __LINE__, bo_gem->gem_handle,
1058 bo_gem->mapped_cpu_write = true;
1060 pthread_mutex_unlock(&bufmgr_gem->lock);
1065 int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
1067 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1068 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1069 struct drm_i915_gem_set_domain set_domain;
1072 pthread_mutex_lock(&bufmgr_gem->lock);
1074 /* Get a mapping of the buffer if we haven't before. */
1075 if (bo_gem->gtt_virtual == NULL) {
1076 struct drm_i915_gem_mmap_gtt mmap_arg;
1078 DBG("bo_map_gtt: mmap %d (%s)\n", bo_gem->gem_handle,
1081 memset(&mmap_arg, 0, sizeof(mmap_arg));
1082 mmap_arg.handle = bo_gem->gem_handle;
1084 /* Get the fake offset back... */
1085 ret = drmIoctl(bufmgr_gem->fd,
1086 DRM_IOCTL_I915_GEM_MMAP_GTT,
1090 DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n",
1092 bo_gem->gem_handle, bo_gem->name,
1094 pthread_mutex_unlock(&bufmgr_gem->lock);
1099 bo_gem->gtt_virtual = mmap(0, bo->size, PROT_READ | PROT_WRITE,
1100 MAP_SHARED, bufmgr_gem->fd,
1102 if (bo_gem->gtt_virtual == MAP_FAILED) {
1103 bo_gem->gtt_virtual = NULL;
1105 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1107 bo_gem->gem_handle, bo_gem->name,
1109 pthread_mutex_unlock(&bufmgr_gem->lock);
1114 bo->virtual = bo_gem->gtt_virtual;
1116 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1117 bo_gem->gtt_virtual);
1119 /* Now move it to the GTT domain so that the CPU caches are flushed */
1120 set_domain.handle = bo_gem->gem_handle;
1121 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1122 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
1123 ret = drmIoctl(bufmgr_gem->fd,
1124 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1127 DBG("%s:%d: Error setting domain %d: %s\n",
1128 __FILE__, __LINE__, bo_gem->gem_handle,
1132 pthread_mutex_unlock(&bufmgr_gem->lock);
1137 static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
1139 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1140 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1141 struct drm_i915_gem_sw_finish sw_finish;
1147 pthread_mutex_lock(&bufmgr_gem->lock);
1149 if (bo_gem->mapped_cpu_write) {
1150 /* Cause a flush to happen if the buffer's pinned for
1151 * scanout, so the results show up in a timely manner.
1152 * Unlike GTT set domains, this only does work if the
1153 * buffer should be scanout-related.
1155 sw_finish.handle = bo_gem->gem_handle;
1156 ret = drmIoctl(bufmgr_gem->fd,
1157 DRM_IOCTL_I915_GEM_SW_FINISH,
1159 ret = ret == -1 ? -errno : 0;
1161 bo_gem->mapped_cpu_write = false;
1165 pthread_mutex_unlock(&bufmgr_gem->lock);
1170 int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
1172 return drm_intel_gem_bo_unmap(bo);
1176 drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset,
1177 unsigned long size, const void *data)
1179 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1180 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1181 struct drm_i915_gem_pwrite pwrite;
1184 memset(&pwrite, 0, sizeof(pwrite));
1185 pwrite.handle = bo_gem->gem_handle;
1186 pwrite.offset = offset;
1188 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
1189 ret = drmIoctl(bufmgr_gem->fd,
1190 DRM_IOCTL_I915_GEM_PWRITE,
1194 DBG("%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
1195 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1196 (int)size, strerror(errno));
1203 drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
1205 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1206 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
1209 get_pipe_from_crtc_id.crtc_id = crtc_id;
1210 ret = drmIoctl(bufmgr_gem->fd,
1211 DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
1212 &get_pipe_from_crtc_id);
1214 /* We return -1 here to signal that we don't
1215 * know which pipe is associated with this crtc.
1216 * This lets the caller know that this information
1217 * isn't available; using the wrong pipe for
1218 * vblank waiting can cause the chipset to lock up
1223 return get_pipe_from_crtc_id.pipe;
1227 drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
1228 unsigned long size, void *data)
1230 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1231 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1232 struct drm_i915_gem_pread pread;
1235 memset(&pread, 0, sizeof(pread));
1236 pread.handle = bo_gem->gem_handle;
1237 pread.offset = offset;
1239 pread.data_ptr = (uint64_t) (uintptr_t) data;
1240 ret = drmIoctl(bufmgr_gem->fd,
1241 DRM_IOCTL_I915_GEM_PREAD,
1245 DBG("%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
1246 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1247 (int)size, strerror(errno));
1253 /** Waits for all GPU rendering with the object to have completed. */
1255 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
1257 drm_intel_gem_bo_start_gtt_access(bo, 1);
1261 * Sets the object to the GTT read and possibly write domain, used by the X
1262 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
1264 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
1265 * can do tiled pixmaps this way.
1268 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
1270 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1271 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1272 struct drm_i915_gem_set_domain set_domain;
1275 set_domain.handle = bo_gem->gem_handle;
1276 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1277 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
1278 ret = drmIoctl(bufmgr_gem->fd,
1279 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1282 DBG("%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
1283 __FILE__, __LINE__, bo_gem->gem_handle,
1284 set_domain.read_domains, set_domain.write_domain,
1290 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
1292 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1295 free(bufmgr_gem->exec2_objects);
1296 free(bufmgr_gem->exec_objects);
1297 free(bufmgr_gem->exec_bos);
1299 pthread_mutex_destroy(&bufmgr_gem->lock);
1301 /* Free any cached buffer objects we were going to reuse */
1302 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
1303 struct drm_intel_gem_bo_bucket *bucket =
1304 &bufmgr_gem->cache_bucket[i];
1305 drm_intel_bo_gem *bo_gem;
1307 while (!DRMLISTEMPTY(&bucket->head)) {
1308 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1309 bucket->head.next, head);
1310 DRMLISTDEL(&bo_gem->head);
1312 drm_intel_gem_bo_free(&bo_gem->bo);
1320 * Adds the target buffer to the validation list and adds the relocation
1321 * to the reloc_buffer's relocation list.
1323 * The relocation entry at the given offset must already contain the
1324 * precomputed relocation value, because the kernel will optimize out
1325 * the relocation entry write when the buffer hasn't moved from the
1326 * last known offset in target_bo.
1329 do_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1330 drm_intel_bo *target_bo, uint32_t target_offset,
1331 uint32_t read_domains, uint32_t write_domain,
1334 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1335 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1336 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1337 bool fenced_command;
1339 if (bo_gem->has_error)
1342 if (target_bo_gem->has_error) {
1343 bo_gem->has_error = true;
1347 /* We never use HW fences for rendering on 965+ */
1348 if (bufmgr_gem->gen >= 4)
1351 fenced_command = need_fence;
1352 if (target_bo_gem->tiling_mode == I915_TILING_NONE)
1355 /* Create a new relocation list if needed */
1356 if (bo_gem->relocs == NULL && drm_intel_setup_reloc_list(bo))
1359 /* Check overflow */
1360 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
1363 assert(offset <= bo->size - 4);
1364 assert((write_domain & (write_domain - 1)) == 0);
1366 /* Make sure that we're not adding a reloc to something whose size has
1367 * already been accounted for.
1369 assert(!bo_gem->used_as_reloc_target);
1370 if (target_bo_gem != bo_gem) {
1371 target_bo_gem->used_as_reloc_target = true;
1372 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
1374 /* An object needing a fence is a tiled buffer, so it won't have
1375 * relocs to other buffers.
1378 target_bo_gem->reloc_tree_fences = 1;
1379 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
1381 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
1382 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
1383 bo_gem->relocs[bo_gem->reloc_count].target_handle =
1384 target_bo_gem->gem_handle;
1385 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
1386 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
1387 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset;
1389 bo_gem->reloc_target_info[bo_gem->reloc_count].bo = target_bo;
1390 if (target_bo != bo)
1391 drm_intel_gem_bo_reference(target_bo);
1393 bo_gem->reloc_target_info[bo_gem->reloc_count].flags =
1394 DRM_INTEL_RELOC_FENCE;
1396 bo_gem->reloc_target_info[bo_gem->reloc_count].flags = 0;
1398 bo_gem->reloc_count++;
1404 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1405 drm_intel_bo *target_bo, uint32_t target_offset,
1406 uint32_t read_domains, uint32_t write_domain)
1408 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1410 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1411 read_domains, write_domain,
1412 !bufmgr_gem->fenced_relocs);
1416 drm_intel_gem_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
1417 drm_intel_bo *target_bo,
1418 uint32_t target_offset,
1419 uint32_t read_domains, uint32_t write_domain)
1421 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1422 read_domains, write_domain, true);
1426 drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo)
1428 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1430 return bo_gem->reloc_count;
1434 * Removes existing relocation entries in the BO after "start".
1436 * This allows a user to avoid a two-step process for state setup with
1437 * counting up all the buffer objects and doing a
1438 * drm_intel_bufmgr_check_aperture_space() before emitting any of the
1439 * relocations for the state setup. Instead, save the state of the
1440 * batchbuffer including drm_intel_gem_get_reloc_count(), emit all the
1441 * state, and then check if it still fits in the aperture.
1443 * Any further drm_intel_bufmgr_check_aperture_space() queries
1444 * involving this buffer in the tree are undefined after this call.
1447 drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start)
1449 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1451 struct timespec time;
1453 clock_gettime(CLOCK_MONOTONIC, &time);
1455 assert(bo_gem->reloc_count >= start);
1456 /* Unreference the cleared target buffers */
1457 for (i = start; i < bo_gem->reloc_count; i++) {
1458 if (bo_gem->reloc_target_info[i].bo != bo) {
1459 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
1460 reloc_target_info[i].bo,
1464 bo_gem->reloc_count = start;
1468 * Walk the tree of relocations rooted at BO and accumulate the list of
1469 * validations to be performed and update the relocation buffers with
1470 * index values into the validation list.
1473 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
1475 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1478 if (bo_gem->relocs == NULL)
1481 for (i = 0; i < bo_gem->reloc_count; i++) {
1482 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1484 if (target_bo == bo)
1487 /* Continue walking the tree depth-first. */
1488 drm_intel_gem_bo_process_reloc(target_bo);
1490 /* Add the target to the validate list */
1491 drm_intel_add_validate_buffer(target_bo);
1496 drm_intel_gem_bo_process_reloc2(drm_intel_bo *bo)
1498 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1501 if (bo_gem->relocs == NULL)
1504 for (i = 0; i < bo_gem->reloc_count; i++) {
1505 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1508 if (target_bo == bo)
1511 /* Continue walking the tree depth-first. */
1512 drm_intel_gem_bo_process_reloc2(target_bo);
1514 need_fence = (bo_gem->reloc_target_info[i].flags &
1515 DRM_INTEL_RELOC_FENCE);
1517 /* Add the target to the validate list */
1518 drm_intel_add_validate_buffer2(target_bo, need_fence);
1524 drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem)
1528 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1529 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1530 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1532 /* Update the buffer offset */
1533 if (bufmgr_gem->exec_objects[i].offset != bo->offset) {
1534 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1535 bo_gem->gem_handle, bo_gem->name, bo->offset,
1536 (unsigned long long)bufmgr_gem->exec_objects[i].
1538 bo->offset = bufmgr_gem->exec_objects[i].offset;
1544 drm_intel_update_buffer_offsets2 (drm_intel_bufmgr_gem *bufmgr_gem)
1548 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1549 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1550 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1552 /* Update the buffer offset */
1553 if (bufmgr_gem->exec2_objects[i].offset != bo->offset) {
1554 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1555 bo_gem->gem_handle, bo_gem->name, bo->offset,
1556 (unsigned long long)bufmgr_gem->exec2_objects[i].offset);
1557 bo->offset = bufmgr_gem->exec2_objects[i].offset;
1563 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
1564 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
1566 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1567 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1568 struct drm_i915_gem_execbuffer execbuf;
1571 if (bo_gem->has_error)
1574 pthread_mutex_lock(&bufmgr_gem->lock);
1575 /* Update indices and set up the validate list. */
1576 drm_intel_gem_bo_process_reloc(bo);
1578 /* Add the batch buffer to the validation list. There are no
1579 * relocations pointing to it.
1581 drm_intel_add_validate_buffer(bo);
1583 execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects;
1584 execbuf.buffer_count = bufmgr_gem->exec_count;
1585 execbuf.batch_start_offset = 0;
1586 execbuf.batch_len = used;
1587 execbuf.cliprects_ptr = (uintptr_t) cliprects;
1588 execbuf.num_cliprects = num_cliprects;
1592 ret = drmIoctl(bufmgr_gem->fd,
1593 DRM_IOCTL_I915_GEM_EXECBUFFER,
1597 if (errno == ENOSPC) {
1598 DBG("Execbuffer fails to pin. "
1599 "Estimate: %u. Actual: %u. Available: %u\n",
1600 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1603 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1606 (unsigned int)bufmgr_gem->gtt_size);
1609 drm_intel_update_buffer_offsets(bufmgr_gem);
1611 if (bufmgr_gem->bufmgr.debug)
1612 drm_intel_gem_dump_validation_list(bufmgr_gem);
1614 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1615 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1616 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1618 /* Disconnect the buffer from the validate list */
1619 bo_gem->validate_index = -1;
1620 bufmgr_gem->exec_bos[i] = NULL;
1622 bufmgr_gem->exec_count = 0;
1623 pthread_mutex_unlock(&bufmgr_gem->lock);
1629 drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used,
1630 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
1633 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1634 struct drm_i915_gem_execbuffer2 execbuf;
1637 switch (flags & 0x7) {
1641 if (!bufmgr_gem->has_blt)
1645 if (!bufmgr_gem->has_bsd)
1648 case I915_EXEC_RENDER:
1649 case I915_EXEC_DEFAULT:
1653 pthread_mutex_lock(&bufmgr_gem->lock);
1654 /* Update indices and set up the validate list. */
1655 drm_intel_gem_bo_process_reloc2(bo);
1657 /* Add the batch buffer to the validation list. There are no relocations
1660 drm_intel_add_validate_buffer2(bo, 0);
1662 execbuf.buffers_ptr = (uintptr_t)bufmgr_gem->exec2_objects;
1663 execbuf.buffer_count = bufmgr_gem->exec_count;
1664 execbuf.batch_start_offset = 0;
1665 execbuf.batch_len = used;
1666 execbuf.cliprects_ptr = (uintptr_t)cliprects;
1667 execbuf.num_cliprects = num_cliprects;
1670 execbuf.flags = flags;
1674 ret = drmIoctl(bufmgr_gem->fd,
1675 DRM_IOCTL_I915_GEM_EXECBUFFER2,
1679 if (ret == -ENOSPC) {
1680 DBG("Execbuffer fails to pin. "
1681 "Estimate: %u. Actual: %u. Available: %u\n",
1682 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1683 bufmgr_gem->exec_count),
1684 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1685 bufmgr_gem->exec_count),
1686 (unsigned int) bufmgr_gem->gtt_size);
1689 drm_intel_update_buffer_offsets2(bufmgr_gem);
1691 if (bufmgr_gem->bufmgr.debug)
1692 drm_intel_gem_dump_validation_list(bufmgr_gem);
1694 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1695 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1696 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1698 /* Disconnect the buffer from the validate list */
1699 bo_gem->validate_index = -1;
1700 bufmgr_gem->exec_bos[i] = NULL;
1702 bufmgr_gem->exec_count = 0;
1703 pthread_mutex_unlock(&bufmgr_gem->lock);
1709 drm_intel_gem_bo_exec2(drm_intel_bo *bo, int used,
1710 drm_clip_rect_t *cliprects, int num_cliprects,
1713 return drm_intel_gem_bo_mrb_exec2(bo, used,
1714 cliprects, num_cliprects, DR4,
1719 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
1721 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1722 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1723 struct drm_i915_gem_pin pin;
1726 memset(&pin, 0, sizeof(pin));
1727 pin.handle = bo_gem->gem_handle;
1728 pin.alignment = alignment;
1730 ret = drmIoctl(bufmgr_gem->fd,
1731 DRM_IOCTL_I915_GEM_PIN,
1736 bo->offset = pin.offset;
1741 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
1743 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1744 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1745 struct drm_i915_gem_unpin unpin;
1748 memset(&unpin, 0, sizeof(unpin));
1749 unpin.handle = bo_gem->gem_handle;
1751 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
1759 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
1760 uint32_t tiling_mode,
1763 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1764 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1765 struct drm_i915_gem_set_tiling set_tiling;
1768 if (bo_gem->global_name == 0 &&
1769 tiling_mode == bo_gem->tiling_mode &&
1770 stride == bo_gem->stride)
1773 memset(&set_tiling, 0, sizeof(set_tiling));
1775 /* set_tiling is slightly broken and overwrites the
1776 * input on the error path, so we have to open code
1779 set_tiling.handle = bo_gem->gem_handle;
1780 set_tiling.tiling_mode = tiling_mode;
1781 set_tiling.stride = stride;
1783 ret = ioctl(bufmgr_gem->fd,
1784 DRM_IOCTL_I915_GEM_SET_TILING,
1786 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
1790 bo_gem->tiling_mode = set_tiling.tiling_mode;
1791 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
1792 bo_gem->stride = set_tiling.stride;
1797 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1800 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1801 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1804 /* Linear buffers have no stride. By ensuring that we only ever use
1805 * stride 0 with linear buffers, we simplify our code.
1807 if (*tiling_mode == I915_TILING_NONE)
1810 ret = drm_intel_gem_bo_set_tiling_internal(bo, *tiling_mode, stride);
1812 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
1814 *tiling_mode = bo_gem->tiling_mode;
1819 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1820 uint32_t * swizzle_mode)
1822 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1824 *tiling_mode = bo_gem->tiling_mode;
1825 *swizzle_mode = bo_gem->swizzle_mode;
1830 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name)
1832 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1833 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1834 struct drm_gem_flink flink;
1837 if (!bo_gem->global_name) {
1838 memset(&flink, 0, sizeof(flink));
1839 flink.handle = bo_gem->gem_handle;
1841 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink);
1844 bo_gem->global_name = flink.name;
1845 bo_gem->reusable = false;
1847 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
1850 *name = bo_gem->global_name;
1855 * Enables unlimited caching of buffer objects for reuse.
1857 * This is potentially very memory expensive, as the cache at each bucket
1858 * size is only bounded by how many buffers of that size we've managed to have
1859 * in flight at once.
1862 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
1864 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1866 bufmgr_gem->bo_reuse = true;
1870 * Enable use of fenced reloc type.
1872 * New code should enable this to avoid unnecessary fence register
1873 * allocation. If this option is not enabled, all relocs will have fence
1874 * register allocated.
1877 drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr)
1879 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
1881 if (bufmgr_gem->bufmgr.bo_exec == drm_intel_gem_bo_exec2)
1882 bufmgr_gem->fenced_relocs = true;
1886 * Return the additional aperture space required by the tree of buffer objects
1890 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
1892 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1896 if (bo == NULL || bo_gem->included_in_check_aperture)
1900 bo_gem->included_in_check_aperture = true;
1902 for (i = 0; i < bo_gem->reloc_count; i++)
1904 drm_intel_gem_bo_get_aperture_space(bo_gem->
1905 reloc_target_info[i].bo);
1911 * Count the number of buffers in this list that need a fence reg
1913 * If the count is greater than the number of available regs, we'll have
1914 * to ask the caller to resubmit a batch with fewer tiled buffers.
1916 * This function over-counts if the same buffer is used multiple times.
1919 drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count)
1922 unsigned int total = 0;
1924 for (i = 0; i < count; i++) {
1925 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1930 total += bo_gem->reloc_tree_fences;
1936 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
1937 * for the next drm_intel_bufmgr_check_aperture_space() call.
1940 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
1942 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1945 if (bo == NULL || !bo_gem->included_in_check_aperture)
1948 bo_gem->included_in_check_aperture = false;
1950 for (i = 0; i < bo_gem->reloc_count; i++)
1951 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->
1952 reloc_target_info[i].bo);
1956 * Return a conservative estimate for the amount of aperture required
1957 * for a collection of buffers. This may double-count some buffers.
1960 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
1963 unsigned int total = 0;
1965 for (i = 0; i < count; i++) {
1966 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1968 total += bo_gem->reloc_tree_size;
1974 * Return the amount of aperture needed for a collection of buffers.
1975 * This avoids double counting any buffers, at the cost of looking
1976 * at every buffer in the set.
1979 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
1982 unsigned int total = 0;
1984 for (i = 0; i < count; i++) {
1985 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
1986 /* For the first buffer object in the array, we get an
1987 * accurate count back for its reloc_tree size (since nothing
1988 * had been flagged as being counted yet). We can save that
1989 * value out as a more conservative reloc_tree_size that
1990 * avoids double-counting target buffers. Since the first
1991 * buffer happens to usually be the batch buffer in our
1992 * callers, this can pull us back from doing the tree
1993 * walk on every new batch emit.
1996 drm_intel_bo_gem *bo_gem =
1997 (drm_intel_bo_gem *) bo_array[i];
1998 bo_gem->reloc_tree_size = total;
2002 for (i = 0; i < count; i++)
2003 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
2008 * Return -1 if the batchbuffer should be flushed before attempting to
2009 * emit rendering referencing the buffers pointed to by bo_array.
2011 * This is required because if we try to emit a batchbuffer with relocations
2012 * to a tree of buffers that won't simultaneously fit in the aperture,
2013 * the rendering will return an error at a point where the software is not
2014 * prepared to recover from it.
2016 * However, we also want to emit the batchbuffer significantly before we reach
2017 * the limit, as a series of batchbuffers each of which references buffers
2018 * covering almost all of the aperture means that at each emit we end up
2019 * waiting to evict a buffer from the last rendering, and we get synchronous
2020 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
2021 * get better parallelism.
2024 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
2026 drm_intel_bufmgr_gem *bufmgr_gem =
2027 (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr;
2028 unsigned int total = 0;
2029 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
2032 /* Check for fence reg constraints if necessary */
2033 if (bufmgr_gem->available_fences) {
2034 total_fences = drm_intel_gem_total_fences(bo_array, count);
2035 if (total_fences > bufmgr_gem->available_fences)
2039 total = drm_intel_gem_estimate_batch_space(bo_array, count);
2041 if (total > threshold)
2042 total = drm_intel_gem_compute_batch_space(bo_array, count);
2044 if (total > threshold) {
2045 DBG("check_space: overflowed available aperture, "
2047 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
2050 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024,
2051 (int)bufmgr_gem->gtt_size / 1024);
2057 * Disable buffer reuse for objects which are shared with the kernel
2058 * as scanout buffers
2061 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
2063 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2065 bo_gem->reusable = false;
2070 drm_intel_gem_bo_is_reusable(drm_intel_bo *bo)
2072 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2074 return bo_gem->reusable;
2078 _drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2080 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2083 for (i = 0; i < bo_gem->reloc_count; i++) {
2084 if (bo_gem->reloc_target_info[i].bo == target_bo)
2086 if (bo == bo_gem->reloc_target_info[i].bo)
2088 if (_drm_intel_gem_bo_references(bo_gem->reloc_target_info[i].bo,
2096 /** Return true if target_bo is referenced by bo's relocation tree. */
2098 drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2100 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
2102 if (bo == NULL || target_bo == NULL)
2104 if (target_bo_gem->used_as_reloc_target)
2105 return _drm_intel_gem_bo_references(bo, target_bo);
2110 add_bucket(drm_intel_bufmgr_gem *bufmgr_gem, int size)
2112 unsigned int i = bufmgr_gem->num_buckets;
2114 assert(i < ARRAY_SIZE(bufmgr_gem->cache_bucket));
2116 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
2117 bufmgr_gem->cache_bucket[i].size = size;
2118 bufmgr_gem->num_buckets++;
2122 init_cache_buckets(drm_intel_bufmgr_gem *bufmgr_gem)
2124 unsigned long size, cache_max_size = 64 * 1024 * 1024;
2126 /* OK, so power of two buckets was too wasteful of memory.
2127 * Give 3 other sizes between each power of two, to hopefully
2128 * cover things accurately enough. (The alternative is
2129 * probably to just go for exact matching of sizes, and assume
2130 * that for things like composited window resize the tiled
2131 * width/height alignment and rounding of sizes to pages will
2132 * get us useful cache hit rates anyway)
2134 add_bucket(bufmgr_gem, 4096);
2135 add_bucket(bufmgr_gem, 4096 * 2);
2136 add_bucket(bufmgr_gem, 4096 * 3);
2138 /* Initialize the linked lists for BO reuse cache. */
2139 for (size = 4 * 4096; size <= cache_max_size; size *= 2) {
2140 add_bucket(bufmgr_gem, size);
2142 add_bucket(bufmgr_gem, size + size * 1 / 4);
2143 add_bucket(bufmgr_gem, size + size * 2 / 4);
2144 add_bucket(bufmgr_gem, size + size * 3 / 4);
2149 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
2150 * and manage map buffer objections.
2152 * \param fd File descriptor of the opened DRM device.
2155 drm_intel_bufmgr_gem_init(int fd, int batch_size)
2157 drm_intel_bufmgr_gem *bufmgr_gem;
2158 struct drm_i915_gem_get_aperture aperture;
2159 drm_i915_getparam_t gp;
2163 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
2164 if (bufmgr_gem == NULL)
2167 bufmgr_gem->fd = fd;
2169 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
2174 ret = drmIoctl(bufmgr_gem->fd,
2175 DRM_IOCTL_I915_GEM_GET_APERTURE,
2179 bufmgr_gem->gtt_size = aperture.aper_available_size;
2181 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
2183 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
2184 fprintf(stderr, "Assuming %dkB available aperture size.\n"
2185 "May lead to reduced performance or incorrect "
2187 (int)bufmgr_gem->gtt_size / 1024);
2190 gp.param = I915_PARAM_CHIPSET_ID;
2191 gp.value = &bufmgr_gem->pci_device;
2192 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2194 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
2195 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
2198 if (IS_GEN2(bufmgr_gem))
2199 bufmgr_gem->gen = 2;
2200 else if (IS_GEN3(bufmgr_gem))
2201 bufmgr_gem->gen = 3;
2202 else if (IS_GEN4(bufmgr_gem))
2203 bufmgr_gem->gen = 4;
2205 bufmgr_gem->gen = 6;
2209 gp.param = I915_PARAM_HAS_EXECBUF2;
2210 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2214 gp.param = I915_PARAM_HAS_BSD;
2215 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2216 bufmgr_gem->has_bsd = ret == 0;
2218 gp.param = I915_PARAM_HAS_BLT;
2219 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2220 bufmgr_gem->has_blt = ret == 0;
2222 gp.param = I915_PARAM_HAS_RELAXED_FENCING;
2223 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2224 bufmgr_gem->has_relaxed_fencing = ret == 0;
2226 if (bufmgr_gem->gen < 4) {
2227 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
2228 gp.value = &bufmgr_gem->available_fences;
2229 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2231 fprintf(stderr, "get fences failed: %d [%d]\n", ret,
2233 fprintf(stderr, "param: %d, val: %d\n", gp.param,
2235 bufmgr_gem->available_fences = 0;
2237 /* XXX The kernel reports the total number of fences,
2238 * including any that may be pinned.
2240 * We presume that there will be at least one pinned
2241 * fence for the scanout buffer, but there may be more
2242 * than one scanout and the user may be manually
2243 * pinning buffers. Let's move to execbuffer2 and
2244 * thereby forget the insanity of using fences...
2246 bufmgr_gem->available_fences -= 2;
2247 if (bufmgr_gem->available_fences < 0)
2248 bufmgr_gem->available_fences = 0;
2252 /* Let's go with one relocation per every 2 dwords (but round down a bit
2253 * since a power of two will mean an extra page allocation for the reloc
2256 * Every 4 was too few for the blender benchmark.
2258 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
2260 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
2261 bufmgr_gem->bufmgr.bo_alloc_for_render =
2262 drm_intel_gem_bo_alloc_for_render;
2263 bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled;
2264 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
2265 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
2266 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
2267 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
2268 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
2269 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
2270 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
2271 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
2272 bufmgr_gem->bufmgr.bo_emit_reloc_fence = drm_intel_gem_bo_emit_reloc_fence;
2273 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
2274 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
2275 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
2276 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
2277 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
2278 /* Use the new one if available */
2280 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec2;
2281 bufmgr_gem->bufmgr.bo_mrb_exec = drm_intel_gem_bo_mrb_exec2;
2283 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
2284 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
2285 bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise;
2286 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_destroy;
2287 bufmgr_gem->bufmgr.debug = 0;
2288 bufmgr_gem->bufmgr.check_aperture_space =
2289 drm_intel_gem_check_aperture_space;
2290 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
2291 bufmgr_gem->bufmgr.bo_is_reusable = drm_intel_gem_bo_is_reusable;
2292 bufmgr_gem->bufmgr.get_pipe_from_crtc_id =
2293 drm_intel_gem_get_pipe_from_crtc_id;
2294 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
2296 DRMINITLISTHEAD(&bufmgr_gem->named);
2297 init_cache_buckets(bufmgr_gem);
2299 return &bufmgr_gem->bufmgr;