1 /**************************************************************************
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007-2012 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 **************************************************************************/
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
42 #include <xf86atomic.h>
50 #include <sys/ioctl.h>
53 #include <sys/types.h>
58 #define ETIME ETIMEDOUT
61 #include "libdrm_lists.h"
62 #include "intel_bufmgr.h"
63 #include "intel_bufmgr_priv.h"
64 #include "intel_chipset.h"
65 #include "intel_aub.h"
78 #define VG_CLEAR(s) VG(memset(&s, 0, sizeof(s)))
80 #define DBG(...) do { \
81 if (bufmgr_gem->bufmgr.debug) \
82 fprintf(stderr, __VA_ARGS__); \
85 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
87 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
89 struct drm_intel_gem_bo_bucket {
94 typedef struct _drm_intel_bufmgr_gem {
95 drm_intel_bufmgr bufmgr;
101 pthread_mutex_t lock;
103 struct drm_i915_gem_exec_object *exec_objects;
104 struct drm_i915_gem_exec_object2 *exec2_objects;
105 drm_intel_bo **exec_bos;
109 /** Array of lists of cached gem objects of power-of-two sizes */
110 struct drm_intel_gem_bo_bucket cache_bucket[14 * 4];
115 drmMMListHead vma_cache;
116 int vma_count, vma_open, vma_max;
119 int available_fences;
122 unsigned int has_bsd : 1;
123 unsigned int has_blt : 1;
124 unsigned int has_relaxed_fencing : 1;
125 unsigned int has_llc : 1;
126 unsigned int has_wait_timeout : 1;
127 unsigned int bo_reuse : 1;
128 unsigned int no_exec : 1;
129 unsigned int has_vebox : 1;
135 } drm_intel_bufmgr_gem;
137 #define DRM_INTEL_RELOC_FENCE (1<<0)
139 typedef struct _drm_intel_reloc_target_info {
142 } drm_intel_reloc_target;
144 struct _drm_intel_bo_gem {
152 * Kenel-assigned global name for this object
154 * List contains both flink named and prime fd'd objects
156 unsigned int global_name;
157 drmMMListHead name_list;
160 * Index of the buffer within the validation list while preparing a
161 * batchbuffer execution.
166 * Current tiling mode
168 uint32_t tiling_mode;
169 uint32_t swizzle_mode;
170 unsigned long stride;
174 /** Array passed to the DRM containing relocation information. */
175 struct drm_i915_gem_relocation_entry *relocs;
177 * Array of info structs corresponding to relocs[i].target_handle etc
179 drm_intel_reloc_target *reloc_target_info;
180 /** Number of entries in relocs */
182 /** Mapped address for the buffer, saved across map/unmap cycles */
184 /** GTT virtual address for the buffer, saved across map/unmap cycles */
187 drmMMListHead vma_list;
193 * Boolean of whether this BO and its children have been included in
194 * the current drm_intel_bufmgr_check_aperture_space() total.
196 bool included_in_check_aperture;
199 * Boolean of whether this buffer has been used as a relocation
200 * target and had its size accounted for, and thus can't have any
201 * further relocations added to it.
203 bool used_as_reloc_target;
206 * Boolean of whether we have encountered an error whilst building the relocation tree.
211 * Boolean of whether this buffer can be re-used
216 * Boolean of whether the GPU is definitely not accessing the buffer.
218 * This is only valid when reusable, since non-reusable
219 * buffers are those that have been shared wth other
220 * processes, so we don't know their state.
225 * Size in bytes of this buffer and its relocation descendents.
227 * Used to avoid costly tree walking in
228 * drm_intel_bufmgr_check_aperture in the common case.
233 * Number of potential fence registers required by this buffer and its
236 int reloc_tree_fences;
238 /** Flags that we may need to do the SW_FINSIH ioctl on unmap. */
239 bool mapped_cpu_write;
243 drm_intel_aub_annotation *aub_annotations;
244 unsigned aub_annotation_count;
248 drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count);
251 drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count);
254 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
255 uint32_t * swizzle_mode);
258 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
259 uint32_t tiling_mode,
262 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
265 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo);
267 static void drm_intel_gem_bo_free(drm_intel_bo *bo);
270 drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
271 uint32_t *tiling_mode)
273 unsigned long min_size, max_size;
276 if (*tiling_mode == I915_TILING_NONE)
279 /* 965+ just need multiples of page size for tiling */
280 if (bufmgr_gem->gen >= 4)
281 return ROUND_UP_TO(size, 4096);
283 /* Older chips need powers of two, of at least 512k or 1M */
284 if (bufmgr_gem->gen == 3) {
285 min_size = 1024*1024;
286 max_size = 128*1024*1024;
289 max_size = 64*1024*1024;
292 if (size > max_size) {
293 *tiling_mode = I915_TILING_NONE;
297 /* Do we need to allocate every page for the fence? */
298 if (bufmgr_gem->has_relaxed_fencing)
299 return ROUND_UP_TO(size, 4096);
301 for (i = min_size; i < size; i <<= 1)
308 * Round a given pitch up to the minimum required for X tiling on a
309 * given chip. We use 512 as the minimum to allow for a later tiling
313 drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
314 unsigned long pitch, uint32_t *tiling_mode)
316 unsigned long tile_width;
319 /* If untiled, then just align it so that we can do rendering
320 * to it with the 3D engine.
322 if (*tiling_mode == I915_TILING_NONE)
323 return ALIGN(pitch, 64);
325 if (*tiling_mode == I915_TILING_X
326 || (IS_915(bufmgr_gem->pci_device)
327 && *tiling_mode == I915_TILING_Y))
332 /* 965 is flexible */
333 if (bufmgr_gem->gen >= 4)
334 return ROUND_UP_TO(pitch, tile_width);
336 /* The older hardware has a maximum pitch of 8192 with tiled
337 * surfaces, so fallback to untiled if it's too large.
340 *tiling_mode = I915_TILING_NONE;
341 return ALIGN(pitch, 64);
344 /* Pre-965 needs power of two tile width */
345 for (i = tile_width; i < pitch; i <<= 1)
351 static struct drm_intel_gem_bo_bucket *
352 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
357 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
358 struct drm_intel_gem_bo_bucket *bucket =
359 &bufmgr_gem->cache_bucket[i];
360 if (bucket->size >= size) {
369 drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
373 for (i = 0; i < bufmgr_gem->exec_count; i++) {
374 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
375 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
377 if (bo_gem->relocs == NULL) {
378 DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle,
383 for (j = 0; j < bo_gem->reloc_count; j++) {
384 drm_intel_bo *target_bo = bo_gem->reloc_target_info[j].bo;
385 drm_intel_bo_gem *target_gem =
386 (drm_intel_bo_gem *) target_bo;
388 DBG("%2d: %d (%s)@0x%08llx -> "
389 "%d (%s)@0x%08lx + 0x%08x\n",
391 bo_gem->gem_handle, bo_gem->name,
392 (unsigned long long)bo_gem->relocs[j].offset,
393 target_gem->gem_handle,
396 bo_gem->relocs[j].delta);
402 drm_intel_gem_bo_reference(drm_intel_bo *bo)
404 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
406 atomic_inc(&bo_gem->refcount);
410 * Adds the given buffer to the list of buffers to be validated (moved into the
411 * appropriate memory type) with the next batch submission.
413 * If a buffer is validated multiple times in a batch submission, it ends up
414 * with the intersection of the memory type flags and the union of the
418 drm_intel_add_validate_buffer(drm_intel_bo *bo)
420 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
421 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
424 if (bo_gem->validate_index != -1)
427 /* Extend the array of validation entries as necessary. */
428 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
429 int new_size = bufmgr_gem->exec_size * 2;
434 bufmgr_gem->exec_objects =
435 realloc(bufmgr_gem->exec_objects,
436 sizeof(*bufmgr_gem->exec_objects) * new_size);
437 bufmgr_gem->exec_bos =
438 realloc(bufmgr_gem->exec_bos,
439 sizeof(*bufmgr_gem->exec_bos) * new_size);
440 bufmgr_gem->exec_size = new_size;
443 index = bufmgr_gem->exec_count;
444 bo_gem->validate_index = index;
445 /* Fill in array entry */
446 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
447 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
448 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs;
449 bufmgr_gem->exec_objects[index].alignment = 0;
450 bufmgr_gem->exec_objects[index].offset = 0;
451 bufmgr_gem->exec_bos[index] = bo;
452 bufmgr_gem->exec_count++;
456 drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence)
458 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
459 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
462 if (bo_gem->validate_index != -1) {
464 bufmgr_gem->exec2_objects[bo_gem->validate_index].flags |=
465 EXEC_OBJECT_NEEDS_FENCE;
469 /* Extend the array of validation entries as necessary. */
470 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
471 int new_size = bufmgr_gem->exec_size * 2;
476 bufmgr_gem->exec2_objects =
477 realloc(bufmgr_gem->exec2_objects,
478 sizeof(*bufmgr_gem->exec2_objects) * new_size);
479 bufmgr_gem->exec_bos =
480 realloc(bufmgr_gem->exec_bos,
481 sizeof(*bufmgr_gem->exec_bos) * new_size);
482 bufmgr_gem->exec_size = new_size;
485 index = bufmgr_gem->exec_count;
486 bo_gem->validate_index = index;
487 /* Fill in array entry */
488 bufmgr_gem->exec2_objects[index].handle = bo_gem->gem_handle;
489 bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count;
490 bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
491 bufmgr_gem->exec2_objects[index].alignment = 0;
492 bufmgr_gem->exec2_objects[index].offset = 0;
493 bufmgr_gem->exec_bos[index] = bo;
494 bufmgr_gem->exec2_objects[index].flags = 0;
495 bufmgr_gem->exec2_objects[index].rsvd1 = 0;
496 bufmgr_gem->exec2_objects[index].rsvd2 = 0;
498 bufmgr_gem->exec2_objects[index].flags |=
499 EXEC_OBJECT_NEEDS_FENCE;
501 bufmgr_gem->exec_count++;
504 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
508 drm_intel_bo_gem_set_in_aperture_size(drm_intel_bufmgr_gem *bufmgr_gem,
509 drm_intel_bo_gem *bo_gem)
513 assert(!bo_gem->used_as_reloc_target);
515 /* The older chipsets are far-less flexible in terms of tiling,
516 * and require tiled buffer to be size aligned in the aperture.
517 * This means that in the worst possible case we will need a hole
518 * twice as large as the object in order for it to fit into the
519 * aperture. Optimal packing is for wimps.
521 size = bo_gem->bo.size;
522 if (bufmgr_gem->gen < 4 && bo_gem->tiling_mode != I915_TILING_NONE) {
525 if (bufmgr_gem->has_relaxed_fencing) {
526 if (bufmgr_gem->gen == 3)
527 min_size = 1024*1024;
531 while (min_size < size)
536 /* Account for worst-case alignment. */
540 bo_gem->reloc_tree_size = size;
544 drm_intel_setup_reloc_list(drm_intel_bo *bo)
546 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
547 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
548 unsigned int max_relocs = bufmgr_gem->max_relocs;
550 if (bo->size / 4 < max_relocs)
551 max_relocs = bo->size / 4;
553 bo_gem->relocs = malloc(max_relocs *
554 sizeof(struct drm_i915_gem_relocation_entry));
555 bo_gem->reloc_target_info = malloc(max_relocs *
556 sizeof(drm_intel_reloc_target));
557 if (bo_gem->relocs == NULL || bo_gem->reloc_target_info == NULL) {
558 bo_gem->has_error = true;
560 free (bo_gem->relocs);
561 bo_gem->relocs = NULL;
563 free (bo_gem->reloc_target_info);
564 bo_gem->reloc_target_info = NULL;
573 drm_intel_gem_bo_busy(drm_intel_bo *bo)
575 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
576 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
577 struct drm_i915_gem_busy busy;
580 if (bo_gem->reusable && bo_gem->idle)
584 busy.handle = bo_gem->gem_handle;
586 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
588 bo_gem->idle = !busy.busy;
593 return (ret == 0 && busy.busy);
597 drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem,
598 drm_intel_bo_gem *bo_gem, int state)
600 struct drm_i915_gem_madvise madv;
603 madv.handle = bo_gem->gem_handle;
606 drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
608 return madv.retained;
612 drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
614 return drm_intel_gem_bo_madvise_internal
615 ((drm_intel_bufmgr_gem *) bo->bufmgr,
616 (drm_intel_bo_gem *) bo,
620 /* drop the oldest entries that have been purged by the kernel */
622 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
623 struct drm_intel_gem_bo_bucket *bucket)
625 while (!DRMLISTEMPTY(&bucket->head)) {
626 drm_intel_bo_gem *bo_gem;
628 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
629 bucket->head.next, head);
630 if (drm_intel_gem_bo_madvise_internal
631 (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
634 DRMLISTDEL(&bo_gem->head);
635 drm_intel_gem_bo_free(&bo_gem->bo);
639 static drm_intel_bo *
640 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr,
644 uint32_t tiling_mode,
645 unsigned long stride)
647 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
648 drm_intel_bo_gem *bo_gem;
649 unsigned int page_size = getpagesize();
651 struct drm_intel_gem_bo_bucket *bucket;
652 bool alloc_from_cache;
653 unsigned long bo_size;
654 bool for_render = false;
656 if (flags & BO_ALLOC_FOR_RENDER)
659 /* Round the allocated size up to a power of two number of pages. */
660 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
662 /* If we don't have caching at this size, don't actually round the
665 if (bucket == NULL) {
667 if (bo_size < page_size)
670 bo_size = bucket->size;
673 pthread_mutex_lock(&bufmgr_gem->lock);
674 /* Get a buffer out of the cache if available */
676 alloc_from_cache = false;
677 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) {
679 /* Allocate new render-target BOs from the tail (MRU)
680 * of the list, as it will likely be hot in the GPU
681 * cache and in the aperture for us.
683 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
684 bucket->head.prev, head);
685 DRMLISTDEL(&bo_gem->head);
686 alloc_from_cache = true;
688 /* For non-render-target BOs (where we're probably
689 * going to map it first thing in order to fill it
690 * with data), check if the last BO in the cache is
691 * unbusy, and only reuse in that case. Otherwise,
692 * allocating a new buffer is probably faster than
693 * waiting for the GPU to finish.
695 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
696 bucket->head.next, head);
697 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
698 alloc_from_cache = true;
699 DRMLISTDEL(&bo_gem->head);
703 if (alloc_from_cache) {
704 if (!drm_intel_gem_bo_madvise_internal
705 (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) {
706 drm_intel_gem_bo_free(&bo_gem->bo);
707 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem,
712 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
715 drm_intel_gem_bo_free(&bo_gem->bo);
720 pthread_mutex_unlock(&bufmgr_gem->lock);
722 if (!alloc_from_cache) {
723 struct drm_i915_gem_create create;
725 bo_gem = calloc(1, sizeof(*bo_gem));
729 bo_gem->bo.size = bo_size;
732 create.size = bo_size;
734 ret = drmIoctl(bufmgr_gem->fd,
735 DRM_IOCTL_I915_GEM_CREATE,
737 bo_gem->gem_handle = create.handle;
738 bo_gem->bo.handle = bo_gem->gem_handle;
743 bo_gem->bo.bufmgr = bufmgr;
745 bo_gem->tiling_mode = I915_TILING_NONE;
746 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
749 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
752 drm_intel_gem_bo_free(&bo_gem->bo);
756 DRMINITLISTHEAD(&bo_gem->name_list);
757 DRMINITLISTHEAD(&bo_gem->vma_list);
761 atomic_set(&bo_gem->refcount, 1);
762 bo_gem->validate_index = -1;
763 bo_gem->reloc_tree_fences = 0;
764 bo_gem->used_as_reloc_target = false;
765 bo_gem->has_error = false;
766 bo_gem->reusable = true;
767 bo_gem->aub_annotations = NULL;
768 bo_gem->aub_annotation_count = 0;
770 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
772 DBG("bo_create: buf %d (%s) %ldb\n",
773 bo_gem->gem_handle, bo_gem->name, size);
778 static drm_intel_bo *
779 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
782 unsigned int alignment)
784 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
786 I915_TILING_NONE, 0);
789 static drm_intel_bo *
790 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr,
793 unsigned int alignment)
795 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0,
796 I915_TILING_NONE, 0);
799 static drm_intel_bo *
800 drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
801 int x, int y, int cpp, uint32_t *tiling_mode,
802 unsigned long *pitch, unsigned long flags)
804 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
805 unsigned long size, stride;
809 unsigned long aligned_y, height_alignment;
811 tiling = *tiling_mode;
813 /* If we're tiled, our allocations are in 8 or 32-row blocks,
814 * so failure to align our height means that we won't allocate
817 * If we're untiled, we still have to align to 2 rows high
818 * because the data port accesses 2x2 blocks even if the
819 * bottom row isn't to be rendered, so failure to align means
820 * we could walk off the end of the GTT and fault. This is
821 * documented on 965, and may be the case on older chipsets
822 * too so we try to be careful.
825 height_alignment = 2;
827 if ((bufmgr_gem->gen == 2) && tiling != I915_TILING_NONE)
828 height_alignment = 16;
829 else if (tiling == I915_TILING_X
830 || (IS_915(bufmgr_gem->pci_device)
831 && tiling == I915_TILING_Y))
832 height_alignment = 8;
833 else if (tiling == I915_TILING_Y)
834 height_alignment = 32;
835 aligned_y = ALIGN(y, height_alignment);
838 stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, tiling_mode);
839 size = stride * aligned_y;
840 size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
841 } while (*tiling_mode != tiling);
844 if (tiling == I915_TILING_NONE)
847 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags,
852 * Returns a drm_intel_bo wrapping the given buffer object handle.
854 * This can be used when one application needs to pass a buffer object
857 drm_public drm_intel_bo *
858 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
862 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
863 drm_intel_bo_gem *bo_gem;
865 struct drm_gem_open open_arg;
866 struct drm_i915_gem_get_tiling get_tiling;
869 /* At the moment most applications only have a few named bo.
870 * For instance, in a DRI client only the render buffers passed
871 * between X and the client are named. And since X returns the
872 * alternating names for the front/back buffer a linear search
873 * provides a sufficiently fast match.
875 for (list = bufmgr_gem->named.next;
876 list != &bufmgr_gem->named;
878 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, list, name_list);
879 if (bo_gem->global_name == handle) {
880 drm_intel_gem_bo_reference(&bo_gem->bo);
886 open_arg.name = handle;
887 ret = drmIoctl(bufmgr_gem->fd,
891 DBG("Couldn't reference %s handle 0x%08x: %s\n",
892 name, handle, strerror(errno));
895 /* Now see if someone has used a prime handle to get this
896 * object from the kernel before by looking through the list
897 * again for a matching gem_handle
899 for (list = bufmgr_gem->named.next;
900 list != &bufmgr_gem->named;
902 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, list, name_list);
903 if (bo_gem->gem_handle == open_arg.handle) {
904 drm_intel_gem_bo_reference(&bo_gem->bo);
909 bo_gem = calloc(1, sizeof(*bo_gem));
913 bo_gem->bo.size = open_arg.size;
914 bo_gem->bo.offset = 0;
915 bo_gem->bo.offset64 = 0;
916 bo_gem->bo.virtual = NULL;
917 bo_gem->bo.bufmgr = bufmgr;
919 atomic_set(&bo_gem->refcount, 1);
920 bo_gem->validate_index = -1;
921 bo_gem->gem_handle = open_arg.handle;
922 bo_gem->bo.handle = open_arg.handle;
923 bo_gem->global_name = handle;
924 bo_gem->reusable = false;
926 VG_CLEAR(get_tiling);
927 get_tiling.handle = bo_gem->gem_handle;
928 ret = drmIoctl(bufmgr_gem->fd,
929 DRM_IOCTL_I915_GEM_GET_TILING,
932 drm_intel_gem_bo_unreference(&bo_gem->bo);
935 bo_gem->tiling_mode = get_tiling.tiling_mode;
936 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
937 /* XXX stride is unknown */
938 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
940 DRMINITLISTHEAD(&bo_gem->vma_list);
941 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
942 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
948 drm_intel_gem_bo_free(drm_intel_bo *bo)
950 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
951 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
952 struct drm_gem_close close;
955 DRMLISTDEL(&bo_gem->vma_list);
956 if (bo_gem->mem_virtual) {
957 VG(VALGRIND_FREELIKE_BLOCK(bo_gem->mem_virtual, 0));
958 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
959 bufmgr_gem->vma_count--;
961 if (bo_gem->gtt_virtual) {
962 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
963 bufmgr_gem->vma_count--;
966 /* Close this object */
968 close.handle = bo_gem->gem_handle;
969 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
971 DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
972 bo_gem->gem_handle, bo_gem->name, strerror(errno));
974 free(bo_gem->aub_annotations);
979 drm_intel_gem_bo_mark_mmaps_incoherent(drm_intel_bo *bo)
982 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
984 if (bo_gem->mem_virtual)
985 VALGRIND_MAKE_MEM_NOACCESS(bo_gem->mem_virtual, bo->size);
987 if (bo_gem->gtt_virtual)
988 VALGRIND_MAKE_MEM_NOACCESS(bo_gem->gtt_virtual, bo->size);
992 /** Frees all cached buffers significantly older than @time. */
994 drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time)
998 if (bufmgr_gem->time == time)
1001 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
1002 struct drm_intel_gem_bo_bucket *bucket =
1003 &bufmgr_gem->cache_bucket[i];
1005 while (!DRMLISTEMPTY(&bucket->head)) {
1006 drm_intel_bo_gem *bo_gem;
1008 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1009 bucket->head.next, head);
1010 if (time - bo_gem->free_time <= 1)
1013 DRMLISTDEL(&bo_gem->head);
1015 drm_intel_gem_bo_free(&bo_gem->bo);
1019 bufmgr_gem->time = time;
1022 static void drm_intel_gem_bo_purge_vma_cache(drm_intel_bufmgr_gem *bufmgr_gem)
1026 DBG("%s: cached=%d, open=%d, limit=%d\n", __FUNCTION__,
1027 bufmgr_gem->vma_count, bufmgr_gem->vma_open, bufmgr_gem->vma_max);
1029 if (bufmgr_gem->vma_max < 0)
1032 /* We may need to evict a few entries in order to create new mmaps */
1033 limit = bufmgr_gem->vma_max - 2*bufmgr_gem->vma_open;
1037 while (bufmgr_gem->vma_count > limit) {
1038 drm_intel_bo_gem *bo_gem;
1040 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1041 bufmgr_gem->vma_cache.next,
1043 assert(bo_gem->map_count == 0);
1044 DRMLISTDELINIT(&bo_gem->vma_list);
1046 if (bo_gem->mem_virtual) {
1047 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
1048 bo_gem->mem_virtual = NULL;
1049 bufmgr_gem->vma_count--;
1051 if (bo_gem->gtt_virtual) {
1052 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
1053 bo_gem->gtt_virtual = NULL;
1054 bufmgr_gem->vma_count--;
1059 static void drm_intel_gem_bo_close_vma(drm_intel_bufmgr_gem *bufmgr_gem,
1060 drm_intel_bo_gem *bo_gem)
1062 bufmgr_gem->vma_open--;
1063 DRMLISTADDTAIL(&bo_gem->vma_list, &bufmgr_gem->vma_cache);
1064 if (bo_gem->mem_virtual)
1065 bufmgr_gem->vma_count++;
1066 if (bo_gem->gtt_virtual)
1067 bufmgr_gem->vma_count++;
1068 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
1071 static void drm_intel_gem_bo_open_vma(drm_intel_bufmgr_gem *bufmgr_gem,
1072 drm_intel_bo_gem *bo_gem)
1074 bufmgr_gem->vma_open++;
1075 DRMLISTDEL(&bo_gem->vma_list);
1076 if (bo_gem->mem_virtual)
1077 bufmgr_gem->vma_count--;
1078 if (bo_gem->gtt_virtual)
1079 bufmgr_gem->vma_count--;
1080 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
1084 drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
1086 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1087 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1088 struct drm_intel_gem_bo_bucket *bucket;
1091 /* Unreference all the target buffers */
1092 for (i = 0; i < bo_gem->reloc_count; i++) {
1093 if (bo_gem->reloc_target_info[i].bo != bo) {
1094 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
1095 reloc_target_info[i].bo,
1099 bo_gem->reloc_count = 0;
1100 bo_gem->used_as_reloc_target = false;
1102 DBG("bo_unreference final: %d (%s)\n",
1103 bo_gem->gem_handle, bo_gem->name);
1105 /* release memory associated with this object */
1106 if (bo_gem->reloc_target_info) {
1107 free(bo_gem->reloc_target_info);
1108 bo_gem->reloc_target_info = NULL;
1110 if (bo_gem->relocs) {
1111 free(bo_gem->relocs);
1112 bo_gem->relocs = NULL;
1115 /* Clear any left-over mappings */
1116 if (bo_gem->map_count) {
1117 DBG("bo freed with non-zero map-count %d\n", bo_gem->map_count);
1118 bo_gem->map_count = 0;
1119 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1120 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1123 DRMLISTDEL(&bo_gem->name_list);
1125 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
1126 /* Put the buffer into our internal cache for reuse if we can. */
1127 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
1128 drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem,
1129 I915_MADV_DONTNEED)) {
1130 bo_gem->free_time = time;
1132 bo_gem->name = NULL;
1133 bo_gem->validate_index = -1;
1135 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
1137 drm_intel_gem_bo_free(bo);
1141 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
1144 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1146 assert(atomic_read(&bo_gem->refcount) > 0);
1147 if (atomic_dec_and_test(&bo_gem->refcount))
1148 drm_intel_gem_bo_unreference_final(bo, time);
1151 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
1153 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1155 assert(atomic_read(&bo_gem->refcount) > 0);
1156 if (atomic_dec_and_test(&bo_gem->refcount)) {
1157 drm_intel_bufmgr_gem *bufmgr_gem =
1158 (drm_intel_bufmgr_gem *) bo->bufmgr;
1159 struct timespec time;
1161 clock_gettime(CLOCK_MONOTONIC, &time);
1163 pthread_mutex_lock(&bufmgr_gem->lock);
1164 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
1165 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time.tv_sec);
1166 pthread_mutex_unlock(&bufmgr_gem->lock);
1170 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
1172 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1173 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1174 struct drm_i915_gem_set_domain set_domain;
1177 pthread_mutex_lock(&bufmgr_gem->lock);
1179 if (bo_gem->map_count++ == 0)
1180 drm_intel_gem_bo_open_vma(bufmgr_gem, bo_gem);
1182 if (!bo_gem->mem_virtual) {
1183 struct drm_i915_gem_mmap mmap_arg;
1185 DBG("bo_map: %d (%s), map_count=%d\n",
1186 bo_gem->gem_handle, bo_gem->name, bo_gem->map_count);
1189 mmap_arg.handle = bo_gem->gem_handle;
1190 mmap_arg.offset = 0;
1191 mmap_arg.size = bo->size;
1192 ret = drmIoctl(bufmgr_gem->fd,
1193 DRM_IOCTL_I915_GEM_MMAP,
1197 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1198 __FILE__, __LINE__, bo_gem->gem_handle,
1199 bo_gem->name, strerror(errno));
1200 if (--bo_gem->map_count == 0)
1201 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1202 pthread_mutex_unlock(&bufmgr_gem->lock);
1205 VG(VALGRIND_MALLOCLIKE_BLOCK(mmap_arg.addr_ptr, mmap_arg.size, 0, 1));
1206 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
1208 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1209 bo_gem->mem_virtual);
1210 bo->virtual = bo_gem->mem_virtual;
1212 VG_CLEAR(set_domain);
1213 set_domain.handle = bo_gem->gem_handle;
1214 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
1216 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
1218 set_domain.write_domain = 0;
1219 ret = drmIoctl(bufmgr_gem->fd,
1220 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1223 DBG("%s:%d: Error setting to CPU domain %d: %s\n",
1224 __FILE__, __LINE__, bo_gem->gem_handle,
1229 bo_gem->mapped_cpu_write = true;
1231 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1232 VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->mem_virtual, bo->size));
1233 pthread_mutex_unlock(&bufmgr_gem->lock);
1239 map_gtt(drm_intel_bo *bo)
1241 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1242 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1245 if (bo_gem->map_count++ == 0)
1246 drm_intel_gem_bo_open_vma(bufmgr_gem, bo_gem);
1248 /* Get a mapping of the buffer if we haven't before. */
1249 if (bo_gem->gtt_virtual == NULL) {
1250 struct drm_i915_gem_mmap_gtt mmap_arg;
1252 DBG("bo_map_gtt: mmap %d (%s), map_count=%d\n",
1253 bo_gem->gem_handle, bo_gem->name, bo_gem->map_count);
1256 mmap_arg.handle = bo_gem->gem_handle;
1258 /* Get the fake offset back... */
1259 ret = drmIoctl(bufmgr_gem->fd,
1260 DRM_IOCTL_I915_GEM_MMAP_GTT,
1264 DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n",
1266 bo_gem->gem_handle, bo_gem->name,
1268 if (--bo_gem->map_count == 0)
1269 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1274 bo_gem->gtt_virtual = mmap(0, bo->size, PROT_READ | PROT_WRITE,
1275 MAP_SHARED, bufmgr_gem->fd,
1277 if (bo_gem->gtt_virtual == MAP_FAILED) {
1278 bo_gem->gtt_virtual = NULL;
1280 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1282 bo_gem->gem_handle, bo_gem->name,
1284 if (--bo_gem->map_count == 0)
1285 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1290 bo->virtual = bo_gem->gtt_virtual;
1292 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1293 bo_gem->gtt_virtual);
1299 drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
1301 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1302 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1303 struct drm_i915_gem_set_domain set_domain;
1306 pthread_mutex_lock(&bufmgr_gem->lock);
1310 pthread_mutex_unlock(&bufmgr_gem->lock);
1314 /* Now move it to the GTT domain so that the GPU and CPU
1315 * caches are flushed and the GPU isn't actively using the
1318 * The pagefault handler does this domain change for us when
1319 * it has unbound the BO from the GTT, but it's up to us to
1320 * tell it when we're about to use things if we had done
1321 * rendering and it still happens to be bound to the GTT.
1323 VG_CLEAR(set_domain);
1324 set_domain.handle = bo_gem->gem_handle;
1325 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1326 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
1327 ret = drmIoctl(bufmgr_gem->fd,
1328 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1331 DBG("%s:%d: Error setting domain %d: %s\n",
1332 __FILE__, __LINE__, bo_gem->gem_handle,
1336 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1337 VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->gtt_virtual, bo->size));
1338 pthread_mutex_unlock(&bufmgr_gem->lock);
1344 * Performs a mapping of the buffer object like the normal GTT
1345 * mapping, but avoids waiting for the GPU to be done reading from or
1346 * rendering to the buffer.
1348 * This is used in the implementation of GL_ARB_map_buffer_range: The
1349 * user asks to create a buffer, then does a mapping, fills some
1350 * space, runs a drawing command, then asks to map it again without
1351 * synchronizing because it guarantees that it won't write over the
1352 * data that the GPU is busy using (or, more specifically, that if it
1353 * does write over the data, it acknowledges that rendering is
1358 drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo)
1360 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1361 #ifdef HAVE_VALGRIND
1362 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1366 /* If the CPU cache isn't coherent with the GTT, then use a
1367 * regular synchronized mapping. The problem is that we don't
1368 * track where the buffer was last used on the CPU side in
1369 * terms of drm_intel_bo_map vs drm_intel_gem_bo_map_gtt, so
1370 * we would potentially corrupt the buffer even when the user
1371 * does reasonable things.
1373 if (!bufmgr_gem->has_llc)
1374 return drm_intel_gem_bo_map_gtt(bo);
1376 pthread_mutex_lock(&bufmgr_gem->lock);
1380 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1381 VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->gtt_virtual, bo->size));
1384 pthread_mutex_unlock(&bufmgr_gem->lock);
1389 static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
1391 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1392 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1398 pthread_mutex_lock(&bufmgr_gem->lock);
1400 if (bo_gem->map_count <= 0) {
1401 DBG("attempted to unmap an unmapped bo\n");
1402 pthread_mutex_unlock(&bufmgr_gem->lock);
1403 /* Preserve the old behaviour of just treating this as a
1404 * no-op rather than reporting the error.
1409 if (bo_gem->mapped_cpu_write) {
1410 struct drm_i915_gem_sw_finish sw_finish;
1412 /* Cause a flush to happen if the buffer's pinned for
1413 * scanout, so the results show up in a timely manner.
1414 * Unlike GTT set domains, this only does work if the
1415 * buffer should be scanout-related.
1417 VG_CLEAR(sw_finish);
1418 sw_finish.handle = bo_gem->gem_handle;
1419 ret = drmIoctl(bufmgr_gem->fd,
1420 DRM_IOCTL_I915_GEM_SW_FINISH,
1422 ret = ret == -1 ? -errno : 0;
1424 bo_gem->mapped_cpu_write = false;
1427 /* We need to unmap after every innovation as we cannot track
1428 * an open vma for every bo as that will exhaasut the system
1429 * limits and cause later failures.
1431 if (--bo_gem->map_count == 0) {
1432 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1433 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1436 pthread_mutex_unlock(&bufmgr_gem->lock);
1442 drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
1444 return drm_intel_gem_bo_unmap(bo);
1448 drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset,
1449 unsigned long size, const void *data)
1451 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1452 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1453 struct drm_i915_gem_pwrite pwrite;
1457 pwrite.handle = bo_gem->gem_handle;
1458 pwrite.offset = offset;
1460 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
1461 ret = drmIoctl(bufmgr_gem->fd,
1462 DRM_IOCTL_I915_GEM_PWRITE,
1466 DBG("%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
1467 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1468 (int)size, strerror(errno));
1475 drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
1477 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1478 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
1481 VG_CLEAR(get_pipe_from_crtc_id);
1482 get_pipe_from_crtc_id.crtc_id = crtc_id;
1483 ret = drmIoctl(bufmgr_gem->fd,
1484 DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
1485 &get_pipe_from_crtc_id);
1487 /* We return -1 here to signal that we don't
1488 * know which pipe is associated with this crtc.
1489 * This lets the caller know that this information
1490 * isn't available; using the wrong pipe for
1491 * vblank waiting can cause the chipset to lock up
1496 return get_pipe_from_crtc_id.pipe;
1500 drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
1501 unsigned long size, void *data)
1503 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1504 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1505 struct drm_i915_gem_pread pread;
1509 pread.handle = bo_gem->gem_handle;
1510 pread.offset = offset;
1512 pread.data_ptr = (uint64_t) (uintptr_t) data;
1513 ret = drmIoctl(bufmgr_gem->fd,
1514 DRM_IOCTL_I915_GEM_PREAD,
1518 DBG("%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
1519 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1520 (int)size, strerror(errno));
1526 /** Waits for all GPU rendering with the object to have completed. */
1528 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
1530 drm_intel_gem_bo_start_gtt_access(bo, 1);
1534 * Waits on a BO for the given amount of time.
1536 * @bo: buffer object to wait for
1537 * @timeout_ns: amount of time to wait in nanoseconds.
1538 * If value is less than 0, an infinite wait will occur.
1540 * Returns 0 if the wait was successful ie. the last batch referencing the
1541 * object has completed within the allotted time. Otherwise some negative return
1542 * value describes the error. Of particular interest is -ETIME when the wait has
1543 * failed to yield the desired result.
1545 * Similar to drm_intel_gem_bo_wait_rendering except a timeout parameter allows
1546 * the operation to give up after a certain amount of time. Another subtle
1547 * difference is the internal locking semantics are different (this variant does
1548 * not hold the lock for the duration of the wait). This makes the wait subject
1549 * to a larger userspace race window.
1551 * The implementation shall wait until the object is no longer actively
1552 * referenced within a batch buffer at the time of the call. The wait will
1553 * not guarantee that the buffer is re-issued via another thread, or an flinked
1554 * handle. Userspace must make sure this race does not occur if such precision
1558 drm_intel_gem_bo_wait(drm_intel_bo *bo, int64_t timeout_ns)
1560 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1561 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1562 struct drm_i915_gem_wait wait;
1565 if (!bufmgr_gem->has_wait_timeout) {
1566 DBG("%s:%d: Timed wait is not supported. Falling back to "
1567 "infinite wait\n", __FILE__, __LINE__);
1569 drm_intel_gem_bo_wait_rendering(bo);
1572 return drm_intel_gem_bo_busy(bo) ? -ETIME : 0;
1576 wait.bo_handle = bo_gem->gem_handle;
1577 wait.timeout_ns = timeout_ns;
1579 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_WAIT, &wait);
1587 * Sets the object to the GTT read and possibly write domain, used by the X
1588 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
1590 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
1591 * can do tiled pixmaps this way.
1594 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
1596 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1597 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1598 struct drm_i915_gem_set_domain set_domain;
1601 VG_CLEAR(set_domain);
1602 set_domain.handle = bo_gem->gem_handle;
1603 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1604 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
1605 ret = drmIoctl(bufmgr_gem->fd,
1606 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1609 DBG("%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
1610 __FILE__, __LINE__, bo_gem->gem_handle,
1611 set_domain.read_domains, set_domain.write_domain,
1617 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
1619 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1622 free(bufmgr_gem->exec2_objects);
1623 free(bufmgr_gem->exec_objects);
1624 free(bufmgr_gem->exec_bos);
1625 free(bufmgr_gem->aub_filename);
1627 pthread_mutex_destroy(&bufmgr_gem->lock);
1629 /* Free any cached buffer objects we were going to reuse */
1630 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
1631 struct drm_intel_gem_bo_bucket *bucket =
1632 &bufmgr_gem->cache_bucket[i];
1633 drm_intel_bo_gem *bo_gem;
1635 while (!DRMLISTEMPTY(&bucket->head)) {
1636 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1637 bucket->head.next, head);
1638 DRMLISTDEL(&bo_gem->head);
1640 drm_intel_gem_bo_free(&bo_gem->bo);
1648 * Adds the target buffer to the validation list and adds the relocation
1649 * to the reloc_buffer's relocation list.
1651 * The relocation entry at the given offset must already contain the
1652 * precomputed relocation value, because the kernel will optimize out
1653 * the relocation entry write when the buffer hasn't moved from the
1654 * last known offset in target_bo.
1657 do_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1658 drm_intel_bo *target_bo, uint32_t target_offset,
1659 uint32_t read_domains, uint32_t write_domain,
1662 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1663 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1664 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1665 bool fenced_command;
1667 if (bo_gem->has_error)
1670 if (target_bo_gem->has_error) {
1671 bo_gem->has_error = true;
1675 /* We never use HW fences for rendering on 965+ */
1676 if (bufmgr_gem->gen >= 4)
1679 fenced_command = need_fence;
1680 if (target_bo_gem->tiling_mode == I915_TILING_NONE)
1683 /* Create a new relocation list if needed */
1684 if (bo_gem->relocs == NULL && drm_intel_setup_reloc_list(bo))
1687 /* Check overflow */
1688 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
1691 assert(offset <= bo->size - 4);
1692 assert((write_domain & (write_domain - 1)) == 0);
1694 /* Make sure that we're not adding a reloc to something whose size has
1695 * already been accounted for.
1697 assert(!bo_gem->used_as_reloc_target);
1698 if (target_bo_gem != bo_gem) {
1699 target_bo_gem->used_as_reloc_target = true;
1700 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
1702 /* An object needing a fence is a tiled buffer, so it won't have
1703 * relocs to other buffers.
1706 target_bo_gem->reloc_tree_fences = 1;
1707 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
1709 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
1710 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
1711 bo_gem->relocs[bo_gem->reloc_count].target_handle =
1712 target_bo_gem->gem_handle;
1713 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
1714 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
1715 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset64;
1717 bo_gem->reloc_target_info[bo_gem->reloc_count].bo = target_bo;
1718 if (target_bo != bo)
1719 drm_intel_gem_bo_reference(target_bo);
1721 bo_gem->reloc_target_info[bo_gem->reloc_count].flags =
1722 DRM_INTEL_RELOC_FENCE;
1724 bo_gem->reloc_target_info[bo_gem->reloc_count].flags = 0;
1726 bo_gem->reloc_count++;
1732 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1733 drm_intel_bo *target_bo, uint32_t target_offset,
1734 uint32_t read_domains, uint32_t write_domain)
1736 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1738 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1739 read_domains, write_domain,
1740 !bufmgr_gem->fenced_relocs);
1744 drm_intel_gem_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
1745 drm_intel_bo *target_bo,
1746 uint32_t target_offset,
1747 uint32_t read_domains, uint32_t write_domain)
1749 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1750 read_domains, write_domain, true);
1754 drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo)
1756 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1758 return bo_gem->reloc_count;
1762 * Removes existing relocation entries in the BO after "start".
1764 * This allows a user to avoid a two-step process for state setup with
1765 * counting up all the buffer objects and doing a
1766 * drm_intel_bufmgr_check_aperture_space() before emitting any of the
1767 * relocations for the state setup. Instead, save the state of the
1768 * batchbuffer including drm_intel_gem_get_reloc_count(), emit all the
1769 * state, and then check if it still fits in the aperture.
1771 * Any further drm_intel_bufmgr_check_aperture_space() queries
1772 * involving this buffer in the tree are undefined after this call.
1775 drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start)
1777 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1779 struct timespec time;
1781 clock_gettime(CLOCK_MONOTONIC, &time);
1783 assert(bo_gem->reloc_count >= start);
1784 /* Unreference the cleared target buffers */
1785 for (i = start; i < bo_gem->reloc_count; i++) {
1786 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) bo_gem->reloc_target_info[i].bo;
1787 if (&target_bo_gem->bo != bo) {
1788 bo_gem->reloc_tree_fences -= target_bo_gem->reloc_tree_fences;
1789 drm_intel_gem_bo_unreference_locked_timed(&target_bo_gem->bo,
1793 bo_gem->reloc_count = start;
1797 * Walk the tree of relocations rooted at BO and accumulate the list of
1798 * validations to be performed and update the relocation buffers with
1799 * index values into the validation list.
1802 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
1804 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1807 if (bo_gem->relocs == NULL)
1810 for (i = 0; i < bo_gem->reloc_count; i++) {
1811 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1813 if (target_bo == bo)
1816 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1818 /* Continue walking the tree depth-first. */
1819 drm_intel_gem_bo_process_reloc(target_bo);
1821 /* Add the target to the validate list */
1822 drm_intel_add_validate_buffer(target_bo);
1827 drm_intel_gem_bo_process_reloc2(drm_intel_bo *bo)
1829 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1832 if (bo_gem->relocs == NULL)
1835 for (i = 0; i < bo_gem->reloc_count; i++) {
1836 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1839 if (target_bo == bo)
1842 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1844 /* Continue walking the tree depth-first. */
1845 drm_intel_gem_bo_process_reloc2(target_bo);
1847 need_fence = (bo_gem->reloc_target_info[i].flags &
1848 DRM_INTEL_RELOC_FENCE);
1850 /* Add the target to the validate list */
1851 drm_intel_add_validate_buffer2(target_bo, need_fence);
1857 drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem)
1861 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1862 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1863 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1865 /* Update the buffer offset */
1866 if (bufmgr_gem->exec_objects[i].offset != bo->offset64) {
1867 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1868 bo_gem->gem_handle, bo_gem->name, bo->offset64,
1869 (unsigned long long)bufmgr_gem->exec_objects[i].
1871 bo->offset64 = bufmgr_gem->exec_objects[i].offset;
1872 bo->offset = bufmgr_gem->exec_objects[i].offset;
1878 drm_intel_update_buffer_offsets2 (drm_intel_bufmgr_gem *bufmgr_gem)
1882 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1883 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1884 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1886 /* Update the buffer offset */
1887 if (bufmgr_gem->exec2_objects[i].offset != bo->offset64) {
1888 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1889 bo_gem->gem_handle, bo_gem->name, bo->offset64,
1890 (unsigned long long)bufmgr_gem->exec2_objects[i].offset);
1891 bo->offset64 = bufmgr_gem->exec2_objects[i].offset;
1892 bo->offset = bufmgr_gem->exec2_objects[i].offset;
1898 aub_out(drm_intel_bufmgr_gem *bufmgr_gem, uint32_t data)
1900 fwrite(&data, 1, 4, bufmgr_gem->aub_file);
1904 aub_out_data(drm_intel_bufmgr_gem *bufmgr_gem, void *data, size_t size)
1906 fwrite(data, 1, size, bufmgr_gem->aub_file);
1910 aub_write_bo_data(drm_intel_bo *bo, uint32_t offset, uint32_t size)
1912 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1913 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1917 data = malloc(bo->size);
1918 drm_intel_bo_get_subdata(bo, offset, size, data);
1920 /* Easy mode: write out bo with no relocations */
1921 if (!bo_gem->reloc_count) {
1922 aub_out_data(bufmgr_gem, data, size);
1927 /* Otherwise, handle the relocations while writing. */
1928 for (i = 0; i < size / 4; i++) {
1930 for (r = 0; r < bo_gem->reloc_count; r++) {
1931 struct drm_i915_gem_relocation_entry *reloc;
1932 drm_intel_reloc_target *info;
1934 reloc = &bo_gem->relocs[r];
1935 info = &bo_gem->reloc_target_info[r];
1937 if (reloc->offset == offset + i * 4) {
1938 drm_intel_bo_gem *target_gem;
1941 target_gem = (drm_intel_bo_gem *)info->bo;
1944 val += target_gem->aub_offset;
1946 aub_out(bufmgr_gem, val);
1951 if (r == bo_gem->reloc_count) {
1952 /* no relocation, just the data */
1953 aub_out(bufmgr_gem, data[i]);
1961 aub_bo_get_address(drm_intel_bo *bo)
1963 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1964 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1966 /* Give the object a graphics address in the AUB file. We
1967 * don't just use the GEM object address because we do AUB
1968 * dumping before execution -- we want to successfully log
1969 * when the hardware might hang, and we might even want to aub
1970 * capture for a driver trying to execute on a different
1971 * generation of hardware by disabling the actual kernel exec
1974 bo_gem->aub_offset = bufmgr_gem->aub_offset;
1975 bufmgr_gem->aub_offset += bo->size;
1976 /* XXX: Handle aperture overflow. */
1977 assert(bufmgr_gem->aub_offset < 256 * 1024 * 1024);
1981 aub_write_trace_block(drm_intel_bo *bo, uint32_t type, uint32_t subtype,
1982 uint32_t offset, uint32_t size)
1984 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1985 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1988 CMD_AUB_TRACE_HEADER_BLOCK |
1989 ((bufmgr_gem->gen >= 8 ? 6 : 5) - 2));
1991 AUB_TRACE_MEMTYPE_GTT | type | AUB_TRACE_OP_DATA_WRITE);
1992 aub_out(bufmgr_gem, subtype);
1993 aub_out(bufmgr_gem, bo_gem->aub_offset + offset);
1994 aub_out(bufmgr_gem, size);
1995 if (bufmgr_gem->gen >= 8)
1996 aub_out(bufmgr_gem, 0);
1997 aub_write_bo_data(bo, offset, size);
2001 * Break up large objects into multiple writes. Otherwise a 128kb VBO
2002 * would overflow the 16 bits of size field in the packet header and
2003 * everything goes badly after that.
2006 aub_write_large_trace_block(drm_intel_bo *bo, uint32_t type, uint32_t subtype,
2007 uint32_t offset, uint32_t size)
2009 uint32_t block_size;
2010 uint32_t sub_offset;
2012 for (sub_offset = 0; sub_offset < size; sub_offset += block_size) {
2013 block_size = size - sub_offset;
2015 if (block_size > 8 * 4096)
2016 block_size = 8 * 4096;
2018 aub_write_trace_block(bo, type, subtype, offset + sub_offset,
2024 aub_write_bo(drm_intel_bo *bo)
2026 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2027 uint32_t offset = 0;
2030 aub_bo_get_address(bo);
2032 /* Write out each annotated section separately. */
2033 for (i = 0; i < bo_gem->aub_annotation_count; ++i) {
2034 drm_intel_aub_annotation *annotation =
2035 &bo_gem->aub_annotations[i];
2036 uint32_t ending_offset = annotation->ending_offset;
2037 if (ending_offset > bo->size)
2038 ending_offset = bo->size;
2039 if (ending_offset > offset) {
2040 aub_write_large_trace_block(bo, annotation->type,
2041 annotation->subtype,
2043 ending_offset - offset);
2044 offset = ending_offset;
2048 /* Write out any remaining unannotated data */
2049 if (offset < bo->size) {
2050 aub_write_large_trace_block(bo, AUB_TRACE_TYPE_NOTYPE, 0,
2051 offset, bo->size - offset);
2056 * Make a ringbuffer on fly and dump it
2059 aub_build_dump_ringbuffer(drm_intel_bufmgr_gem *bufmgr_gem,
2060 uint32_t batch_buffer, int ring_flag)
2062 uint32_t ringbuffer[4096];
2063 int ring = AUB_TRACE_TYPE_RING_PRB0; /* The default ring */
2066 if (ring_flag == I915_EXEC_BSD)
2067 ring = AUB_TRACE_TYPE_RING_PRB1;
2068 else if (ring_flag == I915_EXEC_BLT)
2069 ring = AUB_TRACE_TYPE_RING_PRB2;
2071 /* Make a ring buffer to execute our batchbuffer. */
2072 memset(ringbuffer, 0, sizeof(ringbuffer));
2073 if (bufmgr_gem->gen >= 8) {
2074 ringbuffer[ring_count++] = AUB_MI_BATCH_BUFFER_START | (3 - 2);
2075 ringbuffer[ring_count++] = batch_buffer;
2076 ringbuffer[ring_count++] = 0;
2078 ringbuffer[ring_count++] = AUB_MI_BATCH_BUFFER_START;
2079 ringbuffer[ring_count++] = batch_buffer;
2082 /* Write out the ring. This appears to trigger execution of
2083 * the ring in the simulator.
2086 CMD_AUB_TRACE_HEADER_BLOCK |
2087 ((bufmgr_gem->gen >= 8 ? 6 : 5) - 2));
2089 AUB_TRACE_MEMTYPE_GTT | ring | AUB_TRACE_OP_COMMAND_WRITE);
2090 aub_out(bufmgr_gem, 0); /* general/surface subtype */
2091 aub_out(bufmgr_gem, bufmgr_gem->aub_offset);
2092 aub_out(bufmgr_gem, ring_count * 4);
2093 if (bufmgr_gem->gen >= 8)
2094 aub_out(bufmgr_gem, 0);
2096 /* FIXME: Need some flush operations here? */
2097 aub_out_data(bufmgr_gem, ringbuffer, ring_count * 4);
2099 /* Update offset pointer */
2100 bufmgr_gem->aub_offset += 4096;
2104 drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo,
2105 int x1, int y1, int width, int height,
2106 enum aub_dump_bmp_format format,
2107 int pitch, int offset)
2109 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2110 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
2114 case AUB_DUMP_BMP_FORMAT_8BIT:
2117 case AUB_DUMP_BMP_FORMAT_ARGB_4444:
2120 case AUB_DUMP_BMP_FORMAT_ARGB_0888:
2121 case AUB_DUMP_BMP_FORMAT_ARGB_8888:
2125 printf("Unknown AUB dump format %d\n", format);
2129 if (!bufmgr_gem->aub_file)
2132 aub_out(bufmgr_gem, CMD_AUB_DUMP_BMP | 4);
2133 aub_out(bufmgr_gem, (y1 << 16) | x1);
2138 aub_out(bufmgr_gem, (height << 16) | width);
2139 aub_out(bufmgr_gem, bo_gem->aub_offset + offset);
2141 ((bo_gem->tiling_mode != I915_TILING_NONE) ? (1 << 2) : 0) |
2142 ((bo_gem->tiling_mode == I915_TILING_Y) ? (1 << 3) : 0));
2146 aub_exec(drm_intel_bo *bo, int ring_flag, int used)
2148 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2149 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2151 bool batch_buffer_needs_annotations;
2153 if (!bufmgr_gem->aub_file)
2156 /* If batch buffer is not annotated, annotate it the best we
2159 batch_buffer_needs_annotations = bo_gem->aub_annotation_count == 0;
2160 if (batch_buffer_needs_annotations) {
2161 drm_intel_aub_annotation annotations[2] = {
2162 { AUB_TRACE_TYPE_BATCH, 0, used },
2163 { AUB_TRACE_TYPE_NOTYPE, 0, bo->size }
2165 drm_intel_bufmgr_gem_set_aub_annotations(bo, annotations, 2);
2168 /* Write out all buffers to AUB memory */
2169 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2170 aub_write_bo(bufmgr_gem->exec_bos[i]);
2173 /* Remove any annotations we added */
2174 if (batch_buffer_needs_annotations)
2175 drm_intel_bufmgr_gem_set_aub_annotations(bo, NULL, 0);
2177 /* Dump ring buffer */
2178 aub_build_dump_ringbuffer(bufmgr_gem, bo_gem->aub_offset, ring_flag);
2180 fflush(bufmgr_gem->aub_file);
2183 * One frame has been dumped. So reset the aub_offset for the next frame.
2185 * FIXME: Can we do this?
2187 bufmgr_gem->aub_offset = 0x10000;
2191 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
2192 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
2194 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2195 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2196 struct drm_i915_gem_execbuffer execbuf;
2199 if (bo_gem->has_error)
2202 pthread_mutex_lock(&bufmgr_gem->lock);
2203 /* Update indices and set up the validate list. */
2204 drm_intel_gem_bo_process_reloc(bo);
2206 /* Add the batch buffer to the validation list. There are no
2207 * relocations pointing to it.
2209 drm_intel_add_validate_buffer(bo);
2212 execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects;
2213 execbuf.buffer_count = bufmgr_gem->exec_count;
2214 execbuf.batch_start_offset = 0;
2215 execbuf.batch_len = used;
2216 execbuf.cliprects_ptr = (uintptr_t) cliprects;
2217 execbuf.num_cliprects = num_cliprects;
2221 ret = drmIoctl(bufmgr_gem->fd,
2222 DRM_IOCTL_I915_GEM_EXECBUFFER,
2226 if (errno == ENOSPC) {
2227 DBG("Execbuffer fails to pin. "
2228 "Estimate: %u. Actual: %u. Available: %u\n",
2229 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
2232 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
2235 (unsigned int)bufmgr_gem->gtt_size);
2238 drm_intel_update_buffer_offsets(bufmgr_gem);
2240 if (bufmgr_gem->bufmgr.debug)
2241 drm_intel_gem_dump_validation_list(bufmgr_gem);
2243 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2244 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
2245 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2247 bo_gem->idle = false;
2249 /* Disconnect the buffer from the validate list */
2250 bo_gem->validate_index = -1;
2251 bufmgr_gem->exec_bos[i] = NULL;
2253 bufmgr_gem->exec_count = 0;
2254 pthread_mutex_unlock(&bufmgr_gem->lock);
2260 do_exec2(drm_intel_bo *bo, int used, drm_intel_context *ctx,
2261 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
2264 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
2265 struct drm_i915_gem_execbuffer2 execbuf;
2269 switch (flags & 0x7) {
2273 if (!bufmgr_gem->has_blt)
2277 if (!bufmgr_gem->has_bsd)
2280 case I915_EXEC_VEBOX:
2281 if (!bufmgr_gem->has_vebox)
2284 case I915_EXEC_RENDER:
2285 case I915_EXEC_DEFAULT:
2289 pthread_mutex_lock(&bufmgr_gem->lock);
2290 /* Update indices and set up the validate list. */
2291 drm_intel_gem_bo_process_reloc2(bo);
2293 /* Add the batch buffer to the validation list. There are no relocations
2296 drm_intel_add_validate_buffer2(bo, 0);
2299 execbuf.buffers_ptr = (uintptr_t)bufmgr_gem->exec2_objects;
2300 execbuf.buffer_count = bufmgr_gem->exec_count;
2301 execbuf.batch_start_offset = 0;
2302 execbuf.batch_len = used;
2303 execbuf.cliprects_ptr = (uintptr_t)cliprects;
2304 execbuf.num_cliprects = num_cliprects;
2307 execbuf.flags = flags;
2309 i915_execbuffer2_set_context_id(execbuf, 0);
2311 i915_execbuffer2_set_context_id(execbuf, ctx->ctx_id);
2314 aub_exec(bo, flags, used);
2316 if (bufmgr_gem->no_exec)
2317 goto skip_execution;
2319 ret = drmIoctl(bufmgr_gem->fd,
2320 DRM_IOCTL_I915_GEM_EXECBUFFER2,
2324 if (ret == -ENOSPC) {
2325 DBG("Execbuffer fails to pin. "
2326 "Estimate: %u. Actual: %u. Available: %u\n",
2327 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
2328 bufmgr_gem->exec_count),
2329 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
2330 bufmgr_gem->exec_count),
2331 (unsigned int) bufmgr_gem->gtt_size);
2334 drm_intel_update_buffer_offsets2(bufmgr_gem);
2337 if (bufmgr_gem->bufmgr.debug)
2338 drm_intel_gem_dump_validation_list(bufmgr_gem);
2340 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2341 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
2342 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
2344 bo_gem->idle = false;
2346 /* Disconnect the buffer from the validate list */
2347 bo_gem->validate_index = -1;
2348 bufmgr_gem->exec_bos[i] = NULL;
2350 bufmgr_gem->exec_count = 0;
2351 pthread_mutex_unlock(&bufmgr_gem->lock);
2357 drm_intel_gem_bo_exec2(drm_intel_bo *bo, int used,
2358 drm_clip_rect_t *cliprects, int num_cliprects,
2361 return do_exec2(bo, used, NULL, cliprects, num_cliprects, DR4,
2366 drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used,
2367 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
2370 return do_exec2(bo, used, NULL, cliprects, num_cliprects, DR4,
2375 drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx,
2376 int used, unsigned int flags)
2378 return do_exec2(bo, used, ctx, NULL, 0, 0, flags);
2382 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
2384 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2385 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2386 struct drm_i915_gem_pin pin;
2390 pin.handle = bo_gem->gem_handle;
2391 pin.alignment = alignment;
2393 ret = drmIoctl(bufmgr_gem->fd,
2394 DRM_IOCTL_I915_GEM_PIN,
2399 bo->offset64 = pin.offset;
2400 bo->offset = pin.offset;
2405 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
2407 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2408 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2409 struct drm_i915_gem_unpin unpin;
2413 unpin.handle = bo_gem->gem_handle;
2415 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
2423 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
2424 uint32_t tiling_mode,
2427 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2428 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2429 struct drm_i915_gem_set_tiling set_tiling;
2432 if (bo_gem->global_name == 0 &&
2433 tiling_mode == bo_gem->tiling_mode &&
2434 stride == bo_gem->stride)
2437 memset(&set_tiling, 0, sizeof(set_tiling));
2439 /* set_tiling is slightly broken and overwrites the
2440 * input on the error path, so we have to open code
2443 set_tiling.handle = bo_gem->gem_handle;
2444 set_tiling.tiling_mode = tiling_mode;
2445 set_tiling.stride = stride;
2447 ret = ioctl(bufmgr_gem->fd,
2448 DRM_IOCTL_I915_GEM_SET_TILING,
2450 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
2454 bo_gem->tiling_mode = set_tiling.tiling_mode;
2455 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
2456 bo_gem->stride = set_tiling.stride;
2461 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
2464 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2465 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2468 /* Linear buffers have no stride. By ensuring that we only ever use
2469 * stride 0 with linear buffers, we simplify our code.
2471 if (*tiling_mode == I915_TILING_NONE)
2474 ret = drm_intel_gem_bo_set_tiling_internal(bo, *tiling_mode, stride);
2476 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
2478 *tiling_mode = bo_gem->tiling_mode;
2483 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
2484 uint32_t * swizzle_mode)
2486 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2488 *tiling_mode = bo_gem->tiling_mode;
2489 *swizzle_mode = bo_gem->swizzle_mode;
2493 drm_public drm_intel_bo *
2494 drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr, int prime_fd, int size)
2496 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
2499 drm_intel_bo_gem *bo_gem;
2500 struct drm_i915_gem_get_tiling get_tiling;
2501 drmMMListHead *list;
2503 ret = drmPrimeFDToHandle(bufmgr_gem->fd, prime_fd, &handle);
2506 * See if the kernel has already returned this buffer to us. Just as
2507 * for named buffers, we must not create two bo's pointing at the same
2510 for (list = bufmgr_gem->named.next;
2511 list != &bufmgr_gem->named;
2512 list = list->next) {
2513 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, list, name_list);
2514 if (bo_gem->gem_handle == handle) {
2515 drm_intel_gem_bo_reference(&bo_gem->bo);
2521 fprintf(stderr,"ret is %d %d\n", ret, errno);
2525 bo_gem = calloc(1, sizeof(*bo_gem));
2529 /* Determine size of bo. The fd-to-handle ioctl really should
2530 * return the size, but it doesn't. If we have kernel 3.12 or
2531 * later, we can lseek on the prime fd to get the size. Older
2532 * kernels will just fail, in which case we fall back to the
2533 * provided (estimated or guess size). */
2534 ret = lseek(prime_fd, 0, SEEK_END);
2536 bo_gem->bo.size = ret;
2538 bo_gem->bo.size = size;
2540 bo_gem->bo.handle = handle;
2541 bo_gem->bo.bufmgr = bufmgr;
2543 bo_gem->gem_handle = handle;
2545 atomic_set(&bo_gem->refcount, 1);
2547 bo_gem->name = "prime";
2548 bo_gem->validate_index = -1;
2549 bo_gem->reloc_tree_fences = 0;
2550 bo_gem->used_as_reloc_target = false;
2551 bo_gem->has_error = false;
2552 bo_gem->reusable = false;
2554 DRMINITLISTHEAD(&bo_gem->vma_list);
2555 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
2557 VG_CLEAR(get_tiling);
2558 get_tiling.handle = bo_gem->gem_handle;
2559 ret = drmIoctl(bufmgr_gem->fd,
2560 DRM_IOCTL_I915_GEM_GET_TILING,
2563 drm_intel_gem_bo_unreference(&bo_gem->bo);
2566 bo_gem->tiling_mode = get_tiling.tiling_mode;
2567 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
2568 /* XXX stride is unknown */
2569 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
2575 drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int *prime_fd)
2577 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2578 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2580 if (DRMLISTEMPTY(&bo_gem->name_list))
2581 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
2583 if (drmPrimeHandleToFD(bufmgr_gem->fd, bo_gem->gem_handle,
2584 DRM_CLOEXEC, prime_fd) != 0)
2587 bo_gem->reusable = false;
2593 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name)
2595 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2596 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2599 if (!bo_gem->global_name) {
2600 struct drm_gem_flink flink;
2603 flink.handle = bo_gem->gem_handle;
2605 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink);
2609 bo_gem->global_name = flink.name;
2610 bo_gem->reusable = false;
2612 if (DRMLISTEMPTY(&bo_gem->name_list))
2613 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
2616 *name = bo_gem->global_name;
2621 * Enables unlimited caching of buffer objects for reuse.
2623 * This is potentially very memory expensive, as the cache at each bucket
2624 * size is only bounded by how many buffers of that size we've managed to have
2625 * in flight at once.
2628 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
2630 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
2632 bufmgr_gem->bo_reuse = true;
2636 * Enable use of fenced reloc type.
2638 * New code should enable this to avoid unnecessary fence register
2639 * allocation. If this option is not enabled, all relocs will have fence
2640 * register allocated.
2643 drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr)
2645 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2647 if (bufmgr_gem->bufmgr.bo_exec == drm_intel_gem_bo_exec2)
2648 bufmgr_gem->fenced_relocs = true;
2652 * Return the additional aperture space required by the tree of buffer objects
2656 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
2658 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2662 if (bo == NULL || bo_gem->included_in_check_aperture)
2666 bo_gem->included_in_check_aperture = true;
2668 for (i = 0; i < bo_gem->reloc_count; i++)
2670 drm_intel_gem_bo_get_aperture_space(bo_gem->
2671 reloc_target_info[i].bo);
2677 * Count the number of buffers in this list that need a fence reg
2679 * If the count is greater than the number of available regs, we'll have
2680 * to ask the caller to resubmit a batch with fewer tiled buffers.
2682 * This function over-counts if the same buffer is used multiple times.
2685 drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count)
2688 unsigned int total = 0;
2690 for (i = 0; i < count; i++) {
2691 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
2696 total += bo_gem->reloc_tree_fences;
2702 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
2703 * for the next drm_intel_bufmgr_check_aperture_space() call.
2706 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
2708 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2711 if (bo == NULL || !bo_gem->included_in_check_aperture)
2714 bo_gem->included_in_check_aperture = false;
2716 for (i = 0; i < bo_gem->reloc_count; i++)
2717 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->
2718 reloc_target_info[i].bo);
2722 * Return a conservative estimate for the amount of aperture required
2723 * for a collection of buffers. This may double-count some buffers.
2726 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
2729 unsigned int total = 0;
2731 for (i = 0; i < count; i++) {
2732 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
2734 total += bo_gem->reloc_tree_size;
2740 * Return the amount of aperture needed for a collection of buffers.
2741 * This avoids double counting any buffers, at the cost of looking
2742 * at every buffer in the set.
2745 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
2748 unsigned int total = 0;
2750 for (i = 0; i < count; i++) {
2751 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
2752 /* For the first buffer object in the array, we get an
2753 * accurate count back for its reloc_tree size (since nothing
2754 * had been flagged as being counted yet). We can save that
2755 * value out as a more conservative reloc_tree_size that
2756 * avoids double-counting target buffers. Since the first
2757 * buffer happens to usually be the batch buffer in our
2758 * callers, this can pull us back from doing the tree
2759 * walk on every new batch emit.
2762 drm_intel_bo_gem *bo_gem =
2763 (drm_intel_bo_gem *) bo_array[i];
2764 bo_gem->reloc_tree_size = total;
2768 for (i = 0; i < count; i++)
2769 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
2774 * Return -1 if the batchbuffer should be flushed before attempting to
2775 * emit rendering referencing the buffers pointed to by bo_array.
2777 * This is required because if we try to emit a batchbuffer with relocations
2778 * to a tree of buffers that won't simultaneously fit in the aperture,
2779 * the rendering will return an error at a point where the software is not
2780 * prepared to recover from it.
2782 * However, we also want to emit the batchbuffer significantly before we reach
2783 * the limit, as a series of batchbuffers each of which references buffers
2784 * covering almost all of the aperture means that at each emit we end up
2785 * waiting to evict a buffer from the last rendering, and we get synchronous
2786 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
2787 * get better parallelism.
2790 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
2792 drm_intel_bufmgr_gem *bufmgr_gem =
2793 (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr;
2794 unsigned int total = 0;
2795 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
2798 /* Check for fence reg constraints if necessary */
2799 if (bufmgr_gem->available_fences) {
2800 total_fences = drm_intel_gem_total_fences(bo_array, count);
2801 if (total_fences > bufmgr_gem->available_fences)
2805 total = drm_intel_gem_estimate_batch_space(bo_array, count);
2807 if (total > threshold)
2808 total = drm_intel_gem_compute_batch_space(bo_array, count);
2810 if (total > threshold) {
2811 DBG("check_space: overflowed available aperture, "
2813 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
2816 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024,
2817 (int)bufmgr_gem->gtt_size / 1024);
2823 * Disable buffer reuse for objects which are shared with the kernel
2824 * as scanout buffers
2827 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
2829 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2831 bo_gem->reusable = false;
2836 drm_intel_gem_bo_is_reusable(drm_intel_bo *bo)
2838 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2840 return bo_gem->reusable;
2844 _drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2846 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2849 for (i = 0; i < bo_gem->reloc_count; i++) {
2850 if (bo_gem->reloc_target_info[i].bo == target_bo)
2852 if (bo == bo_gem->reloc_target_info[i].bo)
2854 if (_drm_intel_gem_bo_references(bo_gem->reloc_target_info[i].bo,
2862 /** Return true if target_bo is referenced by bo's relocation tree. */
2864 drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2866 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
2868 if (bo == NULL || target_bo == NULL)
2870 if (target_bo_gem->used_as_reloc_target)
2871 return _drm_intel_gem_bo_references(bo, target_bo);
2876 add_bucket(drm_intel_bufmgr_gem *bufmgr_gem, int size)
2878 unsigned int i = bufmgr_gem->num_buckets;
2880 assert(i < ARRAY_SIZE(bufmgr_gem->cache_bucket));
2882 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
2883 bufmgr_gem->cache_bucket[i].size = size;
2884 bufmgr_gem->num_buckets++;
2888 init_cache_buckets(drm_intel_bufmgr_gem *bufmgr_gem)
2890 unsigned long size, cache_max_size = 64 * 1024 * 1024;
2892 /* OK, so power of two buckets was too wasteful of memory.
2893 * Give 3 other sizes between each power of two, to hopefully
2894 * cover things accurately enough. (The alternative is
2895 * probably to just go for exact matching of sizes, and assume
2896 * that for things like composited window resize the tiled
2897 * width/height alignment and rounding of sizes to pages will
2898 * get us useful cache hit rates anyway)
2900 add_bucket(bufmgr_gem, 4096);
2901 add_bucket(bufmgr_gem, 4096 * 2);
2902 add_bucket(bufmgr_gem, 4096 * 3);
2904 /* Initialize the linked lists for BO reuse cache. */
2905 for (size = 4 * 4096; size <= cache_max_size; size *= 2) {
2906 add_bucket(bufmgr_gem, size);
2908 add_bucket(bufmgr_gem, size + size * 1 / 4);
2909 add_bucket(bufmgr_gem, size + size * 2 / 4);
2910 add_bucket(bufmgr_gem, size + size * 3 / 4);
2915 drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr, int limit)
2917 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2919 bufmgr_gem->vma_max = limit;
2921 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
2925 * Get the PCI ID for the device. This can be overridden by setting the
2926 * INTEL_DEVID_OVERRIDE environment variable to the desired ID.
2929 get_pci_device_id(drm_intel_bufmgr_gem *bufmgr_gem)
2931 char *devid_override;
2934 drm_i915_getparam_t gp;
2936 if (geteuid() == getuid()) {
2937 devid_override = getenv("INTEL_DEVID_OVERRIDE");
2938 if (devid_override) {
2939 bufmgr_gem->no_exec = true;
2940 return strtod(devid_override, NULL);
2946 gp.param = I915_PARAM_CHIPSET_ID;
2948 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2950 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
2951 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
2957 drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr)
2959 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2961 return bufmgr_gem->pci_device;
2965 * Sets the AUB filename.
2967 * This function has to be called before drm_intel_bufmgr_gem_set_aub_dump()
2968 * for it to have any effect.
2971 drm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr,
2972 const char *filename)
2974 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2976 free(bufmgr_gem->aub_filename);
2978 bufmgr_gem->aub_filename = strdup(filename);
2982 * Sets up AUB dumping.
2984 * This is a trace file format that can be used with the simulator.
2985 * Packets are emitted in a format somewhat like GPU command packets.
2986 * You can set up a GTT and upload your objects into the referenced
2987 * space, then send off batchbuffers and get BMPs out the other end.
2990 drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable)
2992 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2993 int entry = 0x200003;
2995 int gtt_size = 0x10000;
2996 const char *filename;
2999 if (bufmgr_gem->aub_file) {
3000 fclose(bufmgr_gem->aub_file);
3001 bufmgr_gem->aub_file = NULL;
3006 if (geteuid() != getuid())
3009 if (bufmgr_gem->aub_filename)
3010 filename = bufmgr_gem->aub_filename;
3012 filename = "intel.aub";
3013 bufmgr_gem->aub_file = fopen(filename, "w+");
3014 if (!bufmgr_gem->aub_file)
3017 /* Start allocating objects from just after the GTT. */
3018 bufmgr_gem->aub_offset = gtt_size;
3020 /* Start with a (required) version packet. */
3021 aub_out(bufmgr_gem, CMD_AUB_HEADER | (13 - 2));
3023 (4 << AUB_HEADER_MAJOR_SHIFT) |
3024 (0 << AUB_HEADER_MINOR_SHIFT));
3025 for (i = 0; i < 8; i++) {
3026 aub_out(bufmgr_gem, 0); /* app name */
3028 aub_out(bufmgr_gem, 0); /* timestamp */
3029 aub_out(bufmgr_gem, 0); /* timestamp */
3030 aub_out(bufmgr_gem, 0); /* comment len */
3032 /* Set up the GTT. The max we can handle is 256M */
3033 aub_out(bufmgr_gem, CMD_AUB_TRACE_HEADER_BLOCK | ((bufmgr_gem->gen >= 8 ? 6 : 5) - 2));
3034 aub_out(bufmgr_gem, AUB_TRACE_MEMTYPE_NONLOCAL | 0 | AUB_TRACE_OP_DATA_WRITE);
3035 aub_out(bufmgr_gem, 0); /* subtype */
3036 aub_out(bufmgr_gem, 0); /* offset */
3037 aub_out(bufmgr_gem, gtt_size); /* size */
3038 if (bufmgr_gem->gen >= 8)
3039 aub_out(bufmgr_gem, 0);
3040 for (i = 0x000; i < gtt_size; i += 4, entry += 0x1000) {
3041 aub_out(bufmgr_gem, entry);
3045 drm_public drm_intel_context *
3046 drm_intel_gem_context_create(drm_intel_bufmgr *bufmgr)
3048 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3049 struct drm_i915_gem_context_create create;
3050 drm_intel_context *context = NULL;
3053 context = calloc(1, sizeof(*context));
3058 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE, &create);
3060 DBG("DRM_IOCTL_I915_GEM_CONTEXT_CREATE failed: %s\n",
3066 context->ctx_id = create.ctx_id;
3067 context->bufmgr = bufmgr;
3073 drm_intel_gem_context_destroy(drm_intel_context *ctx)
3075 drm_intel_bufmgr_gem *bufmgr_gem;
3076 struct drm_i915_gem_context_destroy destroy;
3084 bufmgr_gem = (drm_intel_bufmgr_gem *)ctx->bufmgr;
3085 destroy.ctx_id = ctx->ctx_id;
3086 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_CONTEXT_DESTROY,
3089 fprintf(stderr, "DRM_IOCTL_I915_GEM_CONTEXT_DESTROY failed: %s\n",
3096 drm_intel_get_reset_stats(drm_intel_context *ctx,
3097 uint32_t *reset_count,
3101 drm_intel_bufmgr_gem *bufmgr_gem;
3102 struct drm_i915_reset_stats stats;
3108 memset(&stats, 0, sizeof(stats));
3110 bufmgr_gem = (drm_intel_bufmgr_gem *)ctx->bufmgr;
3111 stats.ctx_id = ctx->ctx_id;
3112 ret = drmIoctl(bufmgr_gem->fd,
3113 DRM_IOCTL_I915_GET_RESET_STATS,
3116 if (reset_count != NULL)
3117 *reset_count = stats.reset_count;
3120 *active = stats.batch_active;
3122 if (pending != NULL)
3123 *pending = stats.batch_pending;
3130 drm_intel_reg_read(drm_intel_bufmgr *bufmgr,
3134 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3135 struct drm_i915_reg_read reg_read;
3139 reg_read.offset = offset;
3141 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_REG_READ, ®_read);
3143 *result = reg_read.val;
3149 * Annotate the given bo for use in aub dumping.
3151 * \param annotations is an array of drm_intel_aub_annotation objects
3152 * describing the type of data in various sections of the bo. Each
3153 * element of the array specifies the type and subtype of a section of
3154 * the bo, and the past-the-end offset of that section. The elements
3155 * of \c annotations must be sorted so that ending_offset is
3158 * \param count is the number of elements in the \c annotations array.
3159 * If \c count is zero, then \c annotations will not be dereferenced.
3161 * Annotations are copied into a private data structure, so caller may
3162 * re-use the memory pointed to by \c annotations after the call
3165 * Annotations are stored for the lifetime of the bo; to reset to the
3166 * default state (no annotations), call this function with a \c count
3170 drm_intel_bufmgr_gem_set_aub_annotations(drm_intel_bo *bo,
3171 drm_intel_aub_annotation *annotations,
3174 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
3175 unsigned size = sizeof(*annotations) * count;
3176 drm_intel_aub_annotation *new_annotations =
3177 count > 0 ? realloc(bo_gem->aub_annotations, size) : NULL;
3178 if (new_annotations == NULL) {
3179 free(bo_gem->aub_annotations);
3180 bo_gem->aub_annotations = NULL;
3181 bo_gem->aub_annotation_count = 0;
3184 memcpy(new_annotations, annotations, size);
3185 bo_gem->aub_annotations = new_annotations;
3186 bo_gem->aub_annotation_count = count;
3190 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
3191 * and manage map buffer objections.
3193 * \param fd File descriptor of the opened DRM device.
3195 drm_public drm_intel_bufmgr *
3196 drm_intel_bufmgr_gem_init(int fd, int batch_size)
3198 drm_intel_bufmgr_gem *bufmgr_gem;
3199 struct drm_i915_gem_get_aperture aperture;
3200 drm_i915_getparam_t gp;
3204 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
3205 if (bufmgr_gem == NULL)
3208 bufmgr_gem->fd = fd;
3210 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
3215 ret = drmIoctl(bufmgr_gem->fd,
3216 DRM_IOCTL_I915_GEM_GET_APERTURE,
3220 bufmgr_gem->gtt_size = aperture.aper_available_size;
3222 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
3224 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
3225 fprintf(stderr, "Assuming %dkB available aperture size.\n"
3226 "May lead to reduced performance or incorrect "
3228 (int)bufmgr_gem->gtt_size / 1024);
3231 bufmgr_gem->pci_device = get_pci_device_id(bufmgr_gem);
3233 if (IS_GEN2(bufmgr_gem->pci_device))
3234 bufmgr_gem->gen = 2;
3235 else if (IS_GEN3(bufmgr_gem->pci_device))
3236 bufmgr_gem->gen = 3;
3237 else if (IS_GEN4(bufmgr_gem->pci_device))
3238 bufmgr_gem->gen = 4;
3239 else if (IS_GEN5(bufmgr_gem->pci_device))
3240 bufmgr_gem->gen = 5;
3241 else if (IS_GEN6(bufmgr_gem->pci_device))
3242 bufmgr_gem->gen = 6;
3243 else if (IS_GEN7(bufmgr_gem->pci_device))
3244 bufmgr_gem->gen = 7;
3245 else if (IS_GEN8(bufmgr_gem->pci_device))
3246 bufmgr_gem->gen = 8;
3252 if (IS_GEN3(bufmgr_gem->pci_device) &&
3253 bufmgr_gem->gtt_size > 256*1024*1024) {
3254 /* The unmappable part of gtt on gen 3 (i.e. above 256MB) can't
3255 * be used for tiled blits. To simplify the accounting, just
3256 * substract the unmappable part (fixed to 256MB on all known
3257 * gen3 devices) if the kernel advertises it. */
3258 bufmgr_gem->gtt_size -= 256*1024*1024;
3264 gp.param = I915_PARAM_HAS_EXECBUF2;
3265 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3269 gp.param = I915_PARAM_HAS_BSD;
3270 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3271 bufmgr_gem->has_bsd = ret == 0;
3273 gp.param = I915_PARAM_HAS_BLT;
3274 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3275 bufmgr_gem->has_blt = ret == 0;
3277 gp.param = I915_PARAM_HAS_RELAXED_FENCING;
3278 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3279 bufmgr_gem->has_relaxed_fencing = ret == 0;
3281 gp.param = I915_PARAM_HAS_WAIT_TIMEOUT;
3282 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3283 bufmgr_gem->has_wait_timeout = ret == 0;
3285 gp.param = I915_PARAM_HAS_LLC;
3286 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3288 /* Kernel does not supports HAS_LLC query, fallback to GPU
3289 * generation detection and assume that we have LLC on GEN6/7
3291 bufmgr_gem->has_llc = (IS_GEN6(bufmgr_gem->pci_device) |
3292 IS_GEN7(bufmgr_gem->pci_device));
3294 bufmgr_gem->has_llc = *gp.value;
3296 gp.param = I915_PARAM_HAS_VEBOX;
3297 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3298 bufmgr_gem->has_vebox = (ret == 0) & (*gp.value > 0);
3300 if (bufmgr_gem->gen < 4) {
3301 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
3302 gp.value = &bufmgr_gem->available_fences;
3303 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3305 fprintf(stderr, "get fences failed: %d [%d]\n", ret,
3307 fprintf(stderr, "param: %d, val: %d\n", gp.param,
3309 bufmgr_gem->available_fences = 0;
3311 /* XXX The kernel reports the total number of fences,
3312 * including any that may be pinned.
3314 * We presume that there will be at least one pinned
3315 * fence for the scanout buffer, but there may be more
3316 * than one scanout and the user may be manually
3317 * pinning buffers. Let's move to execbuffer2 and
3318 * thereby forget the insanity of using fences...
3320 bufmgr_gem->available_fences -= 2;
3321 if (bufmgr_gem->available_fences < 0)
3322 bufmgr_gem->available_fences = 0;
3326 /* Let's go with one relocation per every 2 dwords (but round down a bit
3327 * since a power of two will mean an extra page allocation for the reloc
3330 * Every 4 was too few for the blender benchmark.
3332 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
3334 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
3335 bufmgr_gem->bufmgr.bo_alloc_for_render =
3336 drm_intel_gem_bo_alloc_for_render;
3337 bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled;
3338 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
3339 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
3340 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
3341 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
3342 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
3343 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
3344 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
3345 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
3346 bufmgr_gem->bufmgr.bo_emit_reloc_fence = drm_intel_gem_bo_emit_reloc_fence;
3347 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
3348 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
3349 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
3350 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
3351 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
3352 /* Use the new one if available */
3354 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec2;
3355 bufmgr_gem->bufmgr.bo_mrb_exec = drm_intel_gem_bo_mrb_exec2;
3357 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
3358 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
3359 bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise;
3360 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_destroy;
3361 bufmgr_gem->bufmgr.debug = 0;
3362 bufmgr_gem->bufmgr.check_aperture_space =
3363 drm_intel_gem_check_aperture_space;
3364 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
3365 bufmgr_gem->bufmgr.bo_is_reusable = drm_intel_gem_bo_is_reusable;
3366 bufmgr_gem->bufmgr.get_pipe_from_crtc_id =
3367 drm_intel_gem_get_pipe_from_crtc_id;
3368 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
3370 DRMINITLISTHEAD(&bufmgr_gem->named);
3371 init_cache_buckets(bufmgr_gem);
3373 DRMINITLISTHEAD(&bufmgr_gem->vma_cache);
3374 bufmgr_gem->vma_max = -1; /* unlimited by default */
3376 return &bufmgr_gem->bufmgr;