1 /**************************************************************************
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007-2012 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 **************************************************************************/
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
42 #include <xf86atomic.h>
50 #include <sys/ioctl.h>
53 #include <sys/types.h>
58 #define ETIME ETIMEDOUT
60 #include "libdrm_lists.h"
61 #include "intel_bufmgr.h"
62 #include "intel_bufmgr_priv.h"
63 #include "intel_chipset.h"
64 #include "intel_aub.h"
77 #define VG_CLEAR(s) VG(memset(&s, 0, sizeof(s)))
79 #define DBG(...) do { \
80 if (bufmgr_gem->bufmgr.debug) \
81 fprintf(stderr, __VA_ARGS__); \
84 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
86 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
88 struct drm_intel_gem_bo_bucket {
93 typedef struct _drm_intel_bufmgr_gem {
94 drm_intel_bufmgr bufmgr;
100 pthread_mutex_t lock;
102 struct drm_i915_gem_exec_object *exec_objects;
103 struct drm_i915_gem_exec_object2 *exec2_objects;
104 drm_intel_bo **exec_bos;
108 /** Array of lists of cached gem objects of power-of-two sizes */
109 struct drm_intel_gem_bo_bucket cache_bucket[14 * 4];
114 drmMMListHead vma_cache;
115 int vma_count, vma_open, vma_max;
118 int available_fences;
121 unsigned int has_bsd : 1;
122 unsigned int has_blt : 1;
123 unsigned int has_relaxed_fencing : 1;
124 unsigned int has_llc : 1;
125 unsigned int has_wait_timeout : 1;
126 unsigned int bo_reuse : 1;
127 unsigned int no_exec : 1;
128 unsigned int has_vebox : 1;
134 } drm_intel_bufmgr_gem;
136 #define DRM_INTEL_RELOC_FENCE (1<<0)
138 typedef struct _drm_intel_reloc_target_info {
141 } drm_intel_reloc_target;
143 struct _drm_intel_bo_gem {
151 * Kenel-assigned global name for this object
153 * List contains both flink named and prime fd'd objects
155 unsigned int global_name;
156 drmMMListHead name_list;
159 * Index of the buffer within the validation list while preparing a
160 * batchbuffer execution.
165 * Current tiling mode
167 uint32_t tiling_mode;
168 uint32_t swizzle_mode;
169 unsigned long stride;
173 /** Array passed to the DRM containing relocation information. */
174 struct drm_i915_gem_relocation_entry *relocs;
176 * Array of info structs corresponding to relocs[i].target_handle etc
178 drm_intel_reloc_target *reloc_target_info;
179 /** Number of entries in relocs */
181 /** Mapped address for the buffer, saved across map/unmap cycles */
183 /** GTT virtual address for the buffer, saved across map/unmap cycles */
186 drmMMListHead vma_list;
192 * Boolean of whether this BO and its children have been included in
193 * the current drm_intel_bufmgr_check_aperture_space() total.
195 bool included_in_check_aperture;
198 * Boolean of whether this buffer has been used as a relocation
199 * target and had its size accounted for, and thus can't have any
200 * further relocations added to it.
202 bool used_as_reloc_target;
205 * Boolean of whether we have encountered an error whilst building the relocation tree.
210 * Boolean of whether this buffer can be re-used
215 * Size in bytes of this buffer and its relocation descendents.
217 * Used to avoid costly tree walking in
218 * drm_intel_bufmgr_check_aperture in the common case.
223 * Number of potential fence registers required by this buffer and its
226 int reloc_tree_fences;
228 /** Flags that we may need to do the SW_FINSIH ioctl on unmap. */
229 bool mapped_cpu_write;
233 drm_intel_aub_annotation *aub_annotations;
234 unsigned aub_annotation_count;
238 drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count);
241 drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count);
244 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
245 uint32_t * swizzle_mode);
248 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
249 uint32_t tiling_mode,
252 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
255 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo);
257 static void drm_intel_gem_bo_free(drm_intel_bo *bo);
260 drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
261 uint32_t *tiling_mode)
263 unsigned long min_size, max_size;
266 if (*tiling_mode == I915_TILING_NONE)
269 /* 965+ just need multiples of page size for tiling */
270 if (bufmgr_gem->gen >= 4)
271 return ROUND_UP_TO(size, 4096);
273 /* Older chips need powers of two, of at least 512k or 1M */
274 if (bufmgr_gem->gen == 3) {
275 min_size = 1024*1024;
276 max_size = 128*1024*1024;
279 max_size = 64*1024*1024;
282 if (size > max_size) {
283 *tiling_mode = I915_TILING_NONE;
287 /* Do we need to allocate every page for the fence? */
288 if (bufmgr_gem->has_relaxed_fencing)
289 return ROUND_UP_TO(size, 4096);
291 for (i = min_size; i < size; i <<= 1)
298 * Round a given pitch up to the minimum required for X tiling on a
299 * given chip. We use 512 as the minimum to allow for a later tiling
303 drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
304 unsigned long pitch, uint32_t *tiling_mode)
306 unsigned long tile_width;
309 /* If untiled, then just align it so that we can do rendering
310 * to it with the 3D engine.
312 if (*tiling_mode == I915_TILING_NONE)
313 return ALIGN(pitch, 64);
315 if (*tiling_mode == I915_TILING_X
316 || (IS_915(bufmgr_gem->pci_device)
317 && *tiling_mode == I915_TILING_Y))
322 /* 965 is flexible */
323 if (bufmgr_gem->gen >= 4)
324 return ROUND_UP_TO(pitch, tile_width);
326 /* The older hardware has a maximum pitch of 8192 with tiled
327 * surfaces, so fallback to untiled if it's too large.
330 *tiling_mode = I915_TILING_NONE;
331 return ALIGN(pitch, 64);
334 /* Pre-965 needs power of two tile width */
335 for (i = tile_width; i < pitch; i <<= 1)
341 static struct drm_intel_gem_bo_bucket *
342 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
347 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
348 struct drm_intel_gem_bo_bucket *bucket =
349 &bufmgr_gem->cache_bucket[i];
350 if (bucket->size >= size) {
359 drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
363 for (i = 0; i < bufmgr_gem->exec_count; i++) {
364 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
365 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
367 if (bo_gem->relocs == NULL) {
368 DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle,
373 for (j = 0; j < bo_gem->reloc_count; j++) {
374 drm_intel_bo *target_bo = bo_gem->reloc_target_info[j].bo;
375 drm_intel_bo_gem *target_gem =
376 (drm_intel_bo_gem *) target_bo;
378 DBG("%2d: %d (%s)@0x%08llx -> "
379 "%d (%s)@0x%08lx + 0x%08x\n",
381 bo_gem->gem_handle, bo_gem->name,
382 (unsigned long long)bo_gem->relocs[j].offset,
383 target_gem->gem_handle,
386 bo_gem->relocs[j].delta);
392 drm_intel_gem_bo_reference(drm_intel_bo *bo)
394 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
396 atomic_inc(&bo_gem->refcount);
400 * Adds the given buffer to the list of buffers to be validated (moved into the
401 * appropriate memory type) with the next batch submission.
403 * If a buffer is validated multiple times in a batch submission, it ends up
404 * with the intersection of the memory type flags and the union of the
408 drm_intel_add_validate_buffer(drm_intel_bo *bo)
410 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
411 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
414 if (bo_gem->validate_index != -1)
417 /* Extend the array of validation entries as necessary. */
418 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
419 int new_size = bufmgr_gem->exec_size * 2;
424 bufmgr_gem->exec_objects =
425 realloc(bufmgr_gem->exec_objects,
426 sizeof(*bufmgr_gem->exec_objects) * new_size);
427 bufmgr_gem->exec_bos =
428 realloc(bufmgr_gem->exec_bos,
429 sizeof(*bufmgr_gem->exec_bos) * new_size);
430 bufmgr_gem->exec_size = new_size;
433 index = bufmgr_gem->exec_count;
434 bo_gem->validate_index = index;
435 /* Fill in array entry */
436 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
437 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
438 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs;
439 bufmgr_gem->exec_objects[index].alignment = 0;
440 bufmgr_gem->exec_objects[index].offset = 0;
441 bufmgr_gem->exec_bos[index] = bo;
442 bufmgr_gem->exec_count++;
446 drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence)
448 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
449 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
452 if (bo_gem->validate_index != -1) {
454 bufmgr_gem->exec2_objects[bo_gem->validate_index].flags |=
455 EXEC_OBJECT_NEEDS_FENCE;
459 /* Extend the array of validation entries as necessary. */
460 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
461 int new_size = bufmgr_gem->exec_size * 2;
466 bufmgr_gem->exec2_objects =
467 realloc(bufmgr_gem->exec2_objects,
468 sizeof(*bufmgr_gem->exec2_objects) * new_size);
469 bufmgr_gem->exec_bos =
470 realloc(bufmgr_gem->exec_bos,
471 sizeof(*bufmgr_gem->exec_bos) * new_size);
472 bufmgr_gem->exec_size = new_size;
475 index = bufmgr_gem->exec_count;
476 bo_gem->validate_index = index;
477 /* Fill in array entry */
478 bufmgr_gem->exec2_objects[index].handle = bo_gem->gem_handle;
479 bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count;
480 bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
481 bufmgr_gem->exec2_objects[index].alignment = 0;
482 bufmgr_gem->exec2_objects[index].offset = 0;
483 bufmgr_gem->exec_bos[index] = bo;
484 bufmgr_gem->exec2_objects[index].flags = 0;
485 bufmgr_gem->exec2_objects[index].rsvd1 = 0;
486 bufmgr_gem->exec2_objects[index].rsvd2 = 0;
488 bufmgr_gem->exec2_objects[index].flags |=
489 EXEC_OBJECT_NEEDS_FENCE;
491 bufmgr_gem->exec_count++;
494 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
498 drm_intel_bo_gem_set_in_aperture_size(drm_intel_bufmgr_gem *bufmgr_gem,
499 drm_intel_bo_gem *bo_gem)
503 assert(!bo_gem->used_as_reloc_target);
505 /* The older chipsets are far-less flexible in terms of tiling,
506 * and require tiled buffer to be size aligned in the aperture.
507 * This means that in the worst possible case we will need a hole
508 * twice as large as the object in order for it to fit into the
509 * aperture. Optimal packing is for wimps.
511 size = bo_gem->bo.size;
512 if (bufmgr_gem->gen < 4 && bo_gem->tiling_mode != I915_TILING_NONE) {
515 if (bufmgr_gem->has_relaxed_fencing) {
516 if (bufmgr_gem->gen == 3)
517 min_size = 1024*1024;
521 while (min_size < size)
526 /* Account for worst-case alignment. */
530 bo_gem->reloc_tree_size = size;
534 drm_intel_setup_reloc_list(drm_intel_bo *bo)
536 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
537 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
538 unsigned int max_relocs = bufmgr_gem->max_relocs;
540 if (bo->size / 4 < max_relocs)
541 max_relocs = bo->size / 4;
543 bo_gem->relocs = malloc(max_relocs *
544 sizeof(struct drm_i915_gem_relocation_entry));
545 bo_gem->reloc_target_info = malloc(max_relocs *
546 sizeof(drm_intel_reloc_target));
547 if (bo_gem->relocs == NULL || bo_gem->reloc_target_info == NULL) {
548 bo_gem->has_error = true;
550 free (bo_gem->relocs);
551 bo_gem->relocs = NULL;
553 free (bo_gem->reloc_target_info);
554 bo_gem->reloc_target_info = NULL;
563 drm_intel_gem_bo_busy(drm_intel_bo *bo)
565 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
566 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
567 struct drm_i915_gem_busy busy;
571 busy.handle = bo_gem->gem_handle;
573 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
575 return (ret == 0 && busy.busy);
579 drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem,
580 drm_intel_bo_gem *bo_gem, int state)
582 struct drm_i915_gem_madvise madv;
585 madv.handle = bo_gem->gem_handle;
588 drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
590 return madv.retained;
594 drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
596 return drm_intel_gem_bo_madvise_internal
597 ((drm_intel_bufmgr_gem *) bo->bufmgr,
598 (drm_intel_bo_gem *) bo,
602 /* drop the oldest entries that have been purged by the kernel */
604 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
605 struct drm_intel_gem_bo_bucket *bucket)
607 while (!DRMLISTEMPTY(&bucket->head)) {
608 drm_intel_bo_gem *bo_gem;
610 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
611 bucket->head.next, head);
612 if (drm_intel_gem_bo_madvise_internal
613 (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
616 DRMLISTDEL(&bo_gem->head);
617 drm_intel_gem_bo_free(&bo_gem->bo);
621 static drm_intel_bo *
622 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr,
626 uint32_t tiling_mode,
627 unsigned long stride)
629 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
630 drm_intel_bo_gem *bo_gem;
631 unsigned int page_size = getpagesize();
633 struct drm_intel_gem_bo_bucket *bucket;
634 bool alloc_from_cache;
635 unsigned long bo_size;
636 bool for_render = false;
638 if (flags & BO_ALLOC_FOR_RENDER)
641 /* Round the allocated size up to a power of two number of pages. */
642 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
644 /* If we don't have caching at this size, don't actually round the
647 if (bucket == NULL) {
649 if (bo_size < page_size)
652 bo_size = bucket->size;
655 pthread_mutex_lock(&bufmgr_gem->lock);
656 /* Get a buffer out of the cache if available */
658 alloc_from_cache = false;
659 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) {
661 /* Allocate new render-target BOs from the tail (MRU)
662 * of the list, as it will likely be hot in the GPU
663 * cache and in the aperture for us.
665 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
666 bucket->head.prev, head);
667 DRMLISTDEL(&bo_gem->head);
668 alloc_from_cache = true;
670 /* For non-render-target BOs (where we're probably
671 * going to map it first thing in order to fill it
672 * with data), check if the last BO in the cache is
673 * unbusy, and only reuse in that case. Otherwise,
674 * allocating a new buffer is probably faster than
675 * waiting for the GPU to finish.
677 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
678 bucket->head.next, head);
679 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
680 alloc_from_cache = true;
681 DRMLISTDEL(&bo_gem->head);
685 if (alloc_from_cache) {
686 if (!drm_intel_gem_bo_madvise_internal
687 (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) {
688 drm_intel_gem_bo_free(&bo_gem->bo);
689 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem,
694 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
697 drm_intel_gem_bo_free(&bo_gem->bo);
702 pthread_mutex_unlock(&bufmgr_gem->lock);
704 if (!alloc_from_cache) {
705 struct drm_i915_gem_create create;
707 bo_gem = calloc(1, sizeof(*bo_gem));
711 bo_gem->bo.size = bo_size;
714 create.size = bo_size;
716 ret = drmIoctl(bufmgr_gem->fd,
717 DRM_IOCTL_I915_GEM_CREATE,
719 bo_gem->gem_handle = create.handle;
720 bo_gem->bo.handle = bo_gem->gem_handle;
725 bo_gem->bo.bufmgr = bufmgr;
727 bo_gem->tiling_mode = I915_TILING_NONE;
728 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
731 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
734 drm_intel_gem_bo_free(&bo_gem->bo);
738 DRMINITLISTHEAD(&bo_gem->name_list);
739 DRMINITLISTHEAD(&bo_gem->vma_list);
743 atomic_set(&bo_gem->refcount, 1);
744 bo_gem->validate_index = -1;
745 bo_gem->reloc_tree_fences = 0;
746 bo_gem->used_as_reloc_target = false;
747 bo_gem->has_error = false;
748 bo_gem->reusable = true;
749 bo_gem->aub_annotations = NULL;
750 bo_gem->aub_annotation_count = 0;
752 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
754 DBG("bo_create: buf %d (%s) %ldb\n",
755 bo_gem->gem_handle, bo_gem->name, size);
760 static drm_intel_bo *
761 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
764 unsigned int alignment)
766 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
768 I915_TILING_NONE, 0);
771 static drm_intel_bo *
772 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr,
775 unsigned int alignment)
777 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0,
778 I915_TILING_NONE, 0);
781 static drm_intel_bo *
782 drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
783 int x, int y, int cpp, uint32_t *tiling_mode,
784 unsigned long *pitch, unsigned long flags)
786 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
787 unsigned long size, stride;
791 unsigned long aligned_y, height_alignment;
793 tiling = *tiling_mode;
795 /* If we're tiled, our allocations are in 8 or 32-row blocks,
796 * so failure to align our height means that we won't allocate
799 * If we're untiled, we still have to align to 2 rows high
800 * because the data port accesses 2x2 blocks even if the
801 * bottom row isn't to be rendered, so failure to align means
802 * we could walk off the end of the GTT and fault. This is
803 * documented on 965, and may be the case on older chipsets
804 * too so we try to be careful.
807 height_alignment = 2;
809 if ((bufmgr_gem->gen == 2) && tiling != I915_TILING_NONE)
810 height_alignment = 16;
811 else if (tiling == I915_TILING_X
812 || (IS_915(bufmgr_gem->pci_device)
813 && tiling == I915_TILING_Y))
814 height_alignment = 8;
815 else if (tiling == I915_TILING_Y)
816 height_alignment = 32;
817 aligned_y = ALIGN(y, height_alignment);
820 stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, tiling_mode);
821 size = stride * aligned_y;
822 size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
823 } while (*tiling_mode != tiling);
826 if (tiling == I915_TILING_NONE)
829 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags,
834 * Returns a drm_intel_bo wrapping the given buffer object handle.
836 * This can be used when one application needs to pass a buffer object
840 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
844 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
845 drm_intel_bo_gem *bo_gem;
847 struct drm_gem_open open_arg;
848 struct drm_i915_gem_get_tiling get_tiling;
851 /* At the moment most applications only have a few named bo.
852 * For instance, in a DRI client only the render buffers passed
853 * between X and the client are named. And since X returns the
854 * alternating names for the front/back buffer a linear search
855 * provides a sufficiently fast match.
857 for (list = bufmgr_gem->named.next;
858 list != &bufmgr_gem->named;
860 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, list, name_list);
861 if (bo_gem->global_name == handle) {
862 drm_intel_gem_bo_reference(&bo_gem->bo);
868 open_arg.name = handle;
869 ret = drmIoctl(bufmgr_gem->fd,
873 DBG("Couldn't reference %s handle 0x%08x: %s\n",
874 name, handle, strerror(errno));
877 /* Now see if someone has used a prime handle to get this
878 * object from the kernel before by looking through the list
879 * again for a matching gem_handle
881 for (list = bufmgr_gem->named.next;
882 list != &bufmgr_gem->named;
884 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, list, name_list);
885 if (bo_gem->gem_handle == open_arg.handle) {
886 drm_intel_gem_bo_reference(&bo_gem->bo);
891 bo_gem = calloc(1, sizeof(*bo_gem));
895 bo_gem->bo.size = open_arg.size;
896 bo_gem->bo.offset = 0;
897 bo_gem->bo.virtual = NULL;
898 bo_gem->bo.bufmgr = bufmgr;
900 atomic_set(&bo_gem->refcount, 1);
901 bo_gem->validate_index = -1;
902 bo_gem->gem_handle = open_arg.handle;
903 bo_gem->bo.handle = open_arg.handle;
904 bo_gem->global_name = handle;
905 bo_gem->reusable = false;
907 VG_CLEAR(get_tiling);
908 get_tiling.handle = bo_gem->gem_handle;
909 ret = drmIoctl(bufmgr_gem->fd,
910 DRM_IOCTL_I915_GEM_GET_TILING,
913 drm_intel_gem_bo_unreference(&bo_gem->bo);
916 bo_gem->tiling_mode = get_tiling.tiling_mode;
917 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
918 /* XXX stride is unknown */
919 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
921 DRMINITLISTHEAD(&bo_gem->vma_list);
922 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
923 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
929 drm_intel_gem_bo_free(drm_intel_bo *bo)
931 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
932 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
933 struct drm_gem_close close;
936 DRMLISTDEL(&bo_gem->vma_list);
937 if (bo_gem->mem_virtual) {
938 VG(VALGRIND_FREELIKE_BLOCK(bo_gem->mem_virtual, 0));
939 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
940 bufmgr_gem->vma_count--;
942 if (bo_gem->gtt_virtual) {
943 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
944 bufmgr_gem->vma_count--;
947 /* Close this object */
949 close.handle = bo_gem->gem_handle;
950 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
952 DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
953 bo_gem->gem_handle, bo_gem->name, strerror(errno));
955 free(bo_gem->aub_annotations);
960 drm_intel_gem_bo_mark_mmaps_incoherent(drm_intel_bo *bo)
963 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
965 if (bo_gem->mem_virtual)
966 VALGRIND_MAKE_MEM_NOACCESS(bo_gem->mem_virtual, bo->size);
968 if (bo_gem->gtt_virtual)
969 VALGRIND_MAKE_MEM_NOACCESS(bo_gem->gtt_virtual, bo->size);
973 /** Frees all cached buffers significantly older than @time. */
975 drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time)
979 if (bufmgr_gem->time == time)
982 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
983 struct drm_intel_gem_bo_bucket *bucket =
984 &bufmgr_gem->cache_bucket[i];
986 while (!DRMLISTEMPTY(&bucket->head)) {
987 drm_intel_bo_gem *bo_gem;
989 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
990 bucket->head.next, head);
991 if (time - bo_gem->free_time <= 1)
994 DRMLISTDEL(&bo_gem->head);
996 drm_intel_gem_bo_free(&bo_gem->bo);
1000 bufmgr_gem->time = time;
1003 static void drm_intel_gem_bo_purge_vma_cache(drm_intel_bufmgr_gem *bufmgr_gem)
1007 DBG("%s: cached=%d, open=%d, limit=%d\n", __FUNCTION__,
1008 bufmgr_gem->vma_count, bufmgr_gem->vma_open, bufmgr_gem->vma_max);
1010 if (bufmgr_gem->vma_max < 0)
1013 /* We may need to evict a few entries in order to create new mmaps */
1014 limit = bufmgr_gem->vma_max - 2*bufmgr_gem->vma_open;
1018 while (bufmgr_gem->vma_count > limit) {
1019 drm_intel_bo_gem *bo_gem;
1021 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1022 bufmgr_gem->vma_cache.next,
1024 assert(bo_gem->map_count == 0);
1025 DRMLISTDELINIT(&bo_gem->vma_list);
1027 if (bo_gem->mem_virtual) {
1028 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
1029 bo_gem->mem_virtual = NULL;
1030 bufmgr_gem->vma_count--;
1032 if (bo_gem->gtt_virtual) {
1033 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
1034 bo_gem->gtt_virtual = NULL;
1035 bufmgr_gem->vma_count--;
1040 static void drm_intel_gem_bo_close_vma(drm_intel_bufmgr_gem *bufmgr_gem,
1041 drm_intel_bo_gem *bo_gem)
1043 bufmgr_gem->vma_open--;
1044 DRMLISTADDTAIL(&bo_gem->vma_list, &bufmgr_gem->vma_cache);
1045 if (bo_gem->mem_virtual)
1046 bufmgr_gem->vma_count++;
1047 if (bo_gem->gtt_virtual)
1048 bufmgr_gem->vma_count++;
1049 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
1052 static void drm_intel_gem_bo_open_vma(drm_intel_bufmgr_gem *bufmgr_gem,
1053 drm_intel_bo_gem *bo_gem)
1055 bufmgr_gem->vma_open++;
1056 DRMLISTDEL(&bo_gem->vma_list);
1057 if (bo_gem->mem_virtual)
1058 bufmgr_gem->vma_count--;
1059 if (bo_gem->gtt_virtual)
1060 bufmgr_gem->vma_count--;
1061 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
1065 drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
1067 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1068 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1069 struct drm_intel_gem_bo_bucket *bucket;
1072 /* Unreference all the target buffers */
1073 for (i = 0; i < bo_gem->reloc_count; i++) {
1074 if (bo_gem->reloc_target_info[i].bo != bo) {
1075 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
1076 reloc_target_info[i].bo,
1080 bo_gem->reloc_count = 0;
1081 bo_gem->used_as_reloc_target = false;
1083 DBG("bo_unreference final: %d (%s)\n",
1084 bo_gem->gem_handle, bo_gem->name);
1086 /* release memory associated with this object */
1087 if (bo_gem->reloc_target_info) {
1088 free(bo_gem->reloc_target_info);
1089 bo_gem->reloc_target_info = NULL;
1091 if (bo_gem->relocs) {
1092 free(bo_gem->relocs);
1093 bo_gem->relocs = NULL;
1096 /* Clear any left-over mappings */
1097 if (bo_gem->map_count) {
1098 DBG("bo freed with non-zero map-count %d\n", bo_gem->map_count);
1099 bo_gem->map_count = 0;
1100 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1101 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1104 DRMLISTDEL(&bo_gem->name_list);
1106 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
1107 /* Put the buffer into our internal cache for reuse if we can. */
1108 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
1109 drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem,
1110 I915_MADV_DONTNEED)) {
1111 bo_gem->free_time = time;
1113 bo_gem->name = NULL;
1114 bo_gem->validate_index = -1;
1116 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
1118 drm_intel_gem_bo_free(bo);
1122 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
1125 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1127 assert(atomic_read(&bo_gem->refcount) > 0);
1128 if (atomic_dec_and_test(&bo_gem->refcount))
1129 drm_intel_gem_bo_unreference_final(bo, time);
1132 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
1134 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1136 assert(atomic_read(&bo_gem->refcount) > 0);
1137 if (atomic_dec_and_test(&bo_gem->refcount)) {
1138 drm_intel_bufmgr_gem *bufmgr_gem =
1139 (drm_intel_bufmgr_gem *) bo->bufmgr;
1140 struct timespec time;
1142 clock_gettime(CLOCK_MONOTONIC, &time);
1144 pthread_mutex_lock(&bufmgr_gem->lock);
1145 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
1146 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time.tv_sec);
1147 pthread_mutex_unlock(&bufmgr_gem->lock);
1151 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
1153 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1154 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1155 struct drm_i915_gem_set_domain set_domain;
1158 pthread_mutex_lock(&bufmgr_gem->lock);
1160 if (bo_gem->map_count++ == 0)
1161 drm_intel_gem_bo_open_vma(bufmgr_gem, bo_gem);
1163 if (!bo_gem->mem_virtual) {
1164 struct drm_i915_gem_mmap mmap_arg;
1166 DBG("bo_map: %d (%s), map_count=%d\n",
1167 bo_gem->gem_handle, bo_gem->name, bo_gem->map_count);
1170 mmap_arg.handle = bo_gem->gem_handle;
1171 mmap_arg.offset = 0;
1172 mmap_arg.size = bo->size;
1173 ret = drmIoctl(bufmgr_gem->fd,
1174 DRM_IOCTL_I915_GEM_MMAP,
1178 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1179 __FILE__, __LINE__, bo_gem->gem_handle,
1180 bo_gem->name, strerror(errno));
1181 if (--bo_gem->map_count == 0)
1182 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1183 pthread_mutex_unlock(&bufmgr_gem->lock);
1186 VG(VALGRIND_MALLOCLIKE_BLOCK(mmap_arg.addr_ptr, mmap_arg.size, 0, 1));
1187 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
1189 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1190 bo_gem->mem_virtual);
1191 bo->virtual = bo_gem->mem_virtual;
1193 VG_CLEAR(set_domain);
1194 set_domain.handle = bo_gem->gem_handle;
1195 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
1197 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
1199 set_domain.write_domain = 0;
1200 ret = drmIoctl(bufmgr_gem->fd,
1201 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1204 DBG("%s:%d: Error setting to CPU domain %d: %s\n",
1205 __FILE__, __LINE__, bo_gem->gem_handle,
1210 bo_gem->mapped_cpu_write = true;
1212 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1213 VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->mem_virtual, bo->size));
1214 pthread_mutex_unlock(&bufmgr_gem->lock);
1220 map_gtt(drm_intel_bo *bo)
1222 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1223 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1226 if (bo_gem->map_count++ == 0)
1227 drm_intel_gem_bo_open_vma(bufmgr_gem, bo_gem);
1229 /* Get a mapping of the buffer if we haven't before. */
1230 if (bo_gem->gtt_virtual == NULL) {
1231 struct drm_i915_gem_mmap_gtt mmap_arg;
1233 DBG("bo_map_gtt: mmap %d (%s), map_count=%d\n",
1234 bo_gem->gem_handle, bo_gem->name, bo_gem->map_count);
1237 mmap_arg.handle = bo_gem->gem_handle;
1239 /* Get the fake offset back... */
1240 ret = drmIoctl(bufmgr_gem->fd,
1241 DRM_IOCTL_I915_GEM_MMAP_GTT,
1245 DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n",
1247 bo_gem->gem_handle, bo_gem->name,
1249 if (--bo_gem->map_count == 0)
1250 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1255 bo_gem->gtt_virtual = mmap(0, bo->size, PROT_READ | PROT_WRITE,
1256 MAP_SHARED, bufmgr_gem->fd,
1258 if (bo_gem->gtt_virtual == MAP_FAILED) {
1259 bo_gem->gtt_virtual = NULL;
1261 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1263 bo_gem->gem_handle, bo_gem->name,
1265 if (--bo_gem->map_count == 0)
1266 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1271 bo->virtual = bo_gem->gtt_virtual;
1273 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1274 bo_gem->gtt_virtual);
1279 int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
1281 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1282 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1283 struct drm_i915_gem_set_domain set_domain;
1286 pthread_mutex_lock(&bufmgr_gem->lock);
1290 pthread_mutex_unlock(&bufmgr_gem->lock);
1294 /* Now move it to the GTT domain so that the GPU and CPU
1295 * caches are flushed and the GPU isn't actively using the
1298 * The pagefault handler does this domain change for us when
1299 * it has unbound the BO from the GTT, but it's up to us to
1300 * tell it when we're about to use things if we had done
1301 * rendering and it still happens to be bound to the GTT.
1303 VG_CLEAR(set_domain);
1304 set_domain.handle = bo_gem->gem_handle;
1305 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1306 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
1307 ret = drmIoctl(bufmgr_gem->fd,
1308 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1311 DBG("%s:%d: Error setting domain %d: %s\n",
1312 __FILE__, __LINE__, bo_gem->gem_handle,
1316 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1317 VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->gtt_virtual, bo->size));
1318 pthread_mutex_unlock(&bufmgr_gem->lock);
1324 * Performs a mapping of the buffer object like the normal GTT
1325 * mapping, but avoids waiting for the GPU to be done reading from or
1326 * rendering to the buffer.
1328 * This is used in the implementation of GL_ARB_map_buffer_range: The
1329 * user asks to create a buffer, then does a mapping, fills some
1330 * space, runs a drawing command, then asks to map it again without
1331 * synchronizing because it guarantees that it won't write over the
1332 * data that the GPU is busy using (or, more specifically, that if it
1333 * does write over the data, it acknowledges that rendering is
1337 int drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo)
1339 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1340 #ifdef HAVE_VALGRIND
1341 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1345 /* If the CPU cache isn't coherent with the GTT, then use a
1346 * regular synchronized mapping. The problem is that we don't
1347 * track where the buffer was last used on the CPU side in
1348 * terms of drm_intel_bo_map vs drm_intel_gem_bo_map_gtt, so
1349 * we would potentially corrupt the buffer even when the user
1350 * does reasonable things.
1352 if (!bufmgr_gem->has_llc)
1353 return drm_intel_gem_bo_map_gtt(bo);
1355 pthread_mutex_lock(&bufmgr_gem->lock);
1359 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1360 VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->gtt_virtual, bo->size));
1363 pthread_mutex_unlock(&bufmgr_gem->lock);
1368 static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
1370 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1371 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1377 pthread_mutex_lock(&bufmgr_gem->lock);
1379 if (bo_gem->map_count <= 0) {
1380 DBG("attempted to unmap an unmapped bo\n");
1381 pthread_mutex_unlock(&bufmgr_gem->lock);
1382 /* Preserve the old behaviour of just treating this as a
1383 * no-op rather than reporting the error.
1388 if (bo_gem->mapped_cpu_write) {
1389 struct drm_i915_gem_sw_finish sw_finish;
1391 /* Cause a flush to happen if the buffer's pinned for
1392 * scanout, so the results show up in a timely manner.
1393 * Unlike GTT set domains, this only does work if the
1394 * buffer should be scanout-related.
1396 VG_CLEAR(sw_finish);
1397 sw_finish.handle = bo_gem->gem_handle;
1398 ret = drmIoctl(bufmgr_gem->fd,
1399 DRM_IOCTL_I915_GEM_SW_FINISH,
1401 ret = ret == -1 ? -errno : 0;
1403 bo_gem->mapped_cpu_write = false;
1406 /* We need to unmap after every innovation as we cannot track
1407 * an open vma for every bo as that will exhaasut the system
1408 * limits and cause later failures.
1410 if (--bo_gem->map_count == 0) {
1411 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1412 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1415 pthread_mutex_unlock(&bufmgr_gem->lock);
1420 int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
1422 return drm_intel_gem_bo_unmap(bo);
1426 drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset,
1427 unsigned long size, const void *data)
1429 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1430 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1431 struct drm_i915_gem_pwrite pwrite;
1435 pwrite.handle = bo_gem->gem_handle;
1436 pwrite.offset = offset;
1438 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
1439 ret = drmIoctl(bufmgr_gem->fd,
1440 DRM_IOCTL_I915_GEM_PWRITE,
1444 DBG("%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
1445 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1446 (int)size, strerror(errno));
1453 drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
1455 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1456 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
1459 VG_CLEAR(get_pipe_from_crtc_id);
1460 get_pipe_from_crtc_id.crtc_id = crtc_id;
1461 ret = drmIoctl(bufmgr_gem->fd,
1462 DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
1463 &get_pipe_from_crtc_id);
1465 /* We return -1 here to signal that we don't
1466 * know which pipe is associated with this crtc.
1467 * This lets the caller know that this information
1468 * isn't available; using the wrong pipe for
1469 * vblank waiting can cause the chipset to lock up
1474 return get_pipe_from_crtc_id.pipe;
1478 drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
1479 unsigned long size, void *data)
1481 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1482 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1483 struct drm_i915_gem_pread pread;
1487 pread.handle = bo_gem->gem_handle;
1488 pread.offset = offset;
1490 pread.data_ptr = (uint64_t) (uintptr_t) data;
1491 ret = drmIoctl(bufmgr_gem->fd,
1492 DRM_IOCTL_I915_GEM_PREAD,
1496 DBG("%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
1497 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1498 (int)size, strerror(errno));
1504 /** Waits for all GPU rendering with the object to have completed. */
1506 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
1508 drm_intel_gem_bo_start_gtt_access(bo, 1);
1512 * Waits on a BO for the given amount of time.
1514 * @bo: buffer object to wait for
1515 * @timeout_ns: amount of time to wait in nanoseconds.
1516 * If value is less than 0, an infinite wait will occur.
1518 * Returns 0 if the wait was successful ie. the last batch referencing the
1519 * object has completed within the allotted time. Otherwise some negative return
1520 * value describes the error. Of particular interest is -ETIME when the wait has
1521 * failed to yield the desired result.
1523 * Similar to drm_intel_gem_bo_wait_rendering except a timeout parameter allows
1524 * the operation to give up after a certain amount of time. Another subtle
1525 * difference is the internal locking semantics are different (this variant does
1526 * not hold the lock for the duration of the wait). This makes the wait subject
1527 * to a larger userspace race window.
1529 * The implementation shall wait until the object is no longer actively
1530 * referenced within a batch buffer at the time of the call. The wait will
1531 * not guarantee that the buffer is re-issued via another thread, or an flinked
1532 * handle. Userspace must make sure this race does not occur if such precision
1535 int drm_intel_gem_bo_wait(drm_intel_bo *bo, int64_t timeout_ns)
1537 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1538 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1539 struct drm_i915_gem_wait wait;
1542 if (!bufmgr_gem->has_wait_timeout) {
1543 DBG("%s:%d: Timed wait is not supported. Falling back to "
1544 "infinite wait\n", __FILE__, __LINE__);
1546 drm_intel_gem_bo_wait_rendering(bo);
1549 return drm_intel_gem_bo_busy(bo) ? -ETIME : 0;
1553 wait.bo_handle = bo_gem->gem_handle;
1554 wait.timeout_ns = timeout_ns;
1556 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_WAIT, &wait);
1564 * Sets the object to the GTT read and possibly write domain, used by the X
1565 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
1567 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
1568 * can do tiled pixmaps this way.
1571 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
1573 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1574 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1575 struct drm_i915_gem_set_domain set_domain;
1578 VG_CLEAR(set_domain);
1579 set_domain.handle = bo_gem->gem_handle;
1580 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1581 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
1582 ret = drmIoctl(bufmgr_gem->fd,
1583 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1586 DBG("%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
1587 __FILE__, __LINE__, bo_gem->gem_handle,
1588 set_domain.read_domains, set_domain.write_domain,
1594 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
1596 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1599 free(bufmgr_gem->exec2_objects);
1600 free(bufmgr_gem->exec_objects);
1601 free(bufmgr_gem->exec_bos);
1602 free(bufmgr_gem->aub_filename);
1604 pthread_mutex_destroy(&bufmgr_gem->lock);
1606 /* Free any cached buffer objects we were going to reuse */
1607 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
1608 struct drm_intel_gem_bo_bucket *bucket =
1609 &bufmgr_gem->cache_bucket[i];
1610 drm_intel_bo_gem *bo_gem;
1612 while (!DRMLISTEMPTY(&bucket->head)) {
1613 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1614 bucket->head.next, head);
1615 DRMLISTDEL(&bo_gem->head);
1617 drm_intel_gem_bo_free(&bo_gem->bo);
1625 * Adds the target buffer to the validation list and adds the relocation
1626 * to the reloc_buffer's relocation list.
1628 * The relocation entry at the given offset must already contain the
1629 * precomputed relocation value, because the kernel will optimize out
1630 * the relocation entry write when the buffer hasn't moved from the
1631 * last known offset in target_bo.
1634 do_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1635 drm_intel_bo *target_bo, uint32_t target_offset,
1636 uint32_t read_domains, uint32_t write_domain,
1639 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1640 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1641 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1642 bool fenced_command;
1644 if (bo_gem->has_error)
1647 if (target_bo_gem->has_error) {
1648 bo_gem->has_error = true;
1652 /* We never use HW fences for rendering on 965+ */
1653 if (bufmgr_gem->gen >= 4)
1656 fenced_command = need_fence;
1657 if (target_bo_gem->tiling_mode == I915_TILING_NONE)
1660 /* Create a new relocation list if needed */
1661 if (bo_gem->relocs == NULL && drm_intel_setup_reloc_list(bo))
1664 /* Check overflow */
1665 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
1668 assert(offset <= bo->size - 4);
1669 assert((write_domain & (write_domain - 1)) == 0);
1671 /* Make sure that we're not adding a reloc to something whose size has
1672 * already been accounted for.
1674 assert(!bo_gem->used_as_reloc_target);
1675 if (target_bo_gem != bo_gem) {
1676 target_bo_gem->used_as_reloc_target = true;
1677 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
1679 /* An object needing a fence is a tiled buffer, so it won't have
1680 * relocs to other buffers.
1683 target_bo_gem->reloc_tree_fences = 1;
1684 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
1686 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
1687 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
1688 bo_gem->relocs[bo_gem->reloc_count].target_handle =
1689 target_bo_gem->gem_handle;
1690 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
1691 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
1692 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset;
1694 bo_gem->reloc_target_info[bo_gem->reloc_count].bo = target_bo;
1695 if (target_bo != bo)
1696 drm_intel_gem_bo_reference(target_bo);
1698 bo_gem->reloc_target_info[bo_gem->reloc_count].flags =
1699 DRM_INTEL_RELOC_FENCE;
1701 bo_gem->reloc_target_info[bo_gem->reloc_count].flags = 0;
1703 bo_gem->reloc_count++;
1709 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1710 drm_intel_bo *target_bo, uint32_t target_offset,
1711 uint32_t read_domains, uint32_t write_domain)
1713 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1715 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1716 read_domains, write_domain,
1717 !bufmgr_gem->fenced_relocs);
1721 drm_intel_gem_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
1722 drm_intel_bo *target_bo,
1723 uint32_t target_offset,
1724 uint32_t read_domains, uint32_t write_domain)
1726 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1727 read_domains, write_domain, true);
1731 drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo)
1733 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1735 return bo_gem->reloc_count;
1739 * Removes existing relocation entries in the BO after "start".
1741 * This allows a user to avoid a two-step process for state setup with
1742 * counting up all the buffer objects and doing a
1743 * drm_intel_bufmgr_check_aperture_space() before emitting any of the
1744 * relocations for the state setup. Instead, save the state of the
1745 * batchbuffer including drm_intel_gem_get_reloc_count(), emit all the
1746 * state, and then check if it still fits in the aperture.
1748 * Any further drm_intel_bufmgr_check_aperture_space() queries
1749 * involving this buffer in the tree are undefined after this call.
1752 drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start)
1754 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1756 struct timespec time;
1758 clock_gettime(CLOCK_MONOTONIC, &time);
1760 assert(bo_gem->reloc_count >= start);
1761 /* Unreference the cleared target buffers */
1762 for (i = start; i < bo_gem->reloc_count; i++) {
1763 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) bo_gem->reloc_target_info[i].bo;
1764 if (&target_bo_gem->bo != bo) {
1765 bo_gem->reloc_tree_fences -= target_bo_gem->reloc_tree_fences;
1766 drm_intel_gem_bo_unreference_locked_timed(&target_bo_gem->bo,
1770 bo_gem->reloc_count = start;
1774 * Walk the tree of relocations rooted at BO and accumulate the list of
1775 * validations to be performed and update the relocation buffers with
1776 * index values into the validation list.
1779 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
1781 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1784 if (bo_gem->relocs == NULL)
1787 for (i = 0; i < bo_gem->reloc_count; i++) {
1788 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1790 if (target_bo == bo)
1793 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1795 /* Continue walking the tree depth-first. */
1796 drm_intel_gem_bo_process_reloc(target_bo);
1798 /* Add the target to the validate list */
1799 drm_intel_add_validate_buffer(target_bo);
1804 drm_intel_gem_bo_process_reloc2(drm_intel_bo *bo)
1806 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1809 if (bo_gem->relocs == NULL)
1812 for (i = 0; i < bo_gem->reloc_count; i++) {
1813 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1816 if (target_bo == bo)
1819 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1821 /* Continue walking the tree depth-first. */
1822 drm_intel_gem_bo_process_reloc2(target_bo);
1824 need_fence = (bo_gem->reloc_target_info[i].flags &
1825 DRM_INTEL_RELOC_FENCE);
1827 /* Add the target to the validate list */
1828 drm_intel_add_validate_buffer2(target_bo, need_fence);
1834 drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem)
1838 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1839 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1840 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1842 /* Update the buffer offset */
1843 if (bufmgr_gem->exec_objects[i].offset != bo->offset) {
1844 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1845 bo_gem->gem_handle, bo_gem->name, bo->offset,
1846 (unsigned long long)bufmgr_gem->exec_objects[i].
1848 bo->offset = bufmgr_gem->exec_objects[i].offset;
1854 drm_intel_update_buffer_offsets2 (drm_intel_bufmgr_gem *bufmgr_gem)
1858 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1859 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1860 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1862 /* Update the buffer offset */
1863 if (bufmgr_gem->exec2_objects[i].offset != bo->offset) {
1864 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1865 bo_gem->gem_handle, bo_gem->name, bo->offset,
1866 (unsigned long long)bufmgr_gem->exec2_objects[i].offset);
1867 bo->offset = bufmgr_gem->exec2_objects[i].offset;
1873 aub_out(drm_intel_bufmgr_gem *bufmgr_gem, uint32_t data)
1875 fwrite(&data, 1, 4, bufmgr_gem->aub_file);
1879 aub_out_data(drm_intel_bufmgr_gem *bufmgr_gem, void *data, size_t size)
1881 fwrite(data, 1, size, bufmgr_gem->aub_file);
1885 aub_write_bo_data(drm_intel_bo *bo, uint32_t offset, uint32_t size)
1887 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1888 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1892 data = malloc(bo->size);
1893 drm_intel_bo_get_subdata(bo, offset, size, data);
1895 /* Easy mode: write out bo with no relocations */
1896 if (!bo_gem->reloc_count) {
1897 aub_out_data(bufmgr_gem, data, size);
1902 /* Otherwise, handle the relocations while writing. */
1903 for (i = 0; i < size / 4; i++) {
1905 for (r = 0; r < bo_gem->reloc_count; r++) {
1906 struct drm_i915_gem_relocation_entry *reloc;
1907 drm_intel_reloc_target *info;
1909 reloc = &bo_gem->relocs[r];
1910 info = &bo_gem->reloc_target_info[r];
1912 if (reloc->offset == offset + i * 4) {
1913 drm_intel_bo_gem *target_gem;
1916 target_gem = (drm_intel_bo_gem *)info->bo;
1919 val += target_gem->aub_offset;
1921 aub_out(bufmgr_gem, val);
1926 if (r == bo_gem->reloc_count) {
1927 /* no relocation, just the data */
1928 aub_out(bufmgr_gem, data[i]);
1936 aub_bo_get_address(drm_intel_bo *bo)
1938 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1939 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1941 /* Give the object a graphics address in the AUB file. We
1942 * don't just use the GEM object address because we do AUB
1943 * dumping before execution -- we want to successfully log
1944 * when the hardware might hang, and we might even want to aub
1945 * capture for a driver trying to execute on a different
1946 * generation of hardware by disabling the actual kernel exec
1949 bo_gem->aub_offset = bufmgr_gem->aub_offset;
1950 bufmgr_gem->aub_offset += bo->size;
1951 /* XXX: Handle aperture overflow. */
1952 assert(bufmgr_gem->aub_offset < 256 * 1024 * 1024);
1956 aub_write_trace_block(drm_intel_bo *bo, uint32_t type, uint32_t subtype,
1957 uint32_t offset, uint32_t size)
1959 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1960 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1963 CMD_AUB_TRACE_HEADER_BLOCK |
1964 ((bufmgr_gem->gen >= 8 ? 6 : 5) - 2));
1966 AUB_TRACE_MEMTYPE_GTT | type | AUB_TRACE_OP_DATA_WRITE);
1967 aub_out(bufmgr_gem, subtype);
1968 aub_out(bufmgr_gem, bo_gem->aub_offset + offset);
1969 aub_out(bufmgr_gem, size);
1970 if (bufmgr_gem->gen >= 8)
1971 aub_out(bufmgr_gem, 0);
1972 aub_write_bo_data(bo, offset, size);
1976 * Break up large objects into multiple writes. Otherwise a 128kb VBO
1977 * would overflow the 16 bits of size field in the packet header and
1978 * everything goes badly after that.
1981 aub_write_large_trace_block(drm_intel_bo *bo, uint32_t type, uint32_t subtype,
1982 uint32_t offset, uint32_t size)
1984 uint32_t block_size;
1985 uint32_t sub_offset;
1987 for (sub_offset = 0; sub_offset < size; sub_offset += block_size) {
1988 block_size = size - sub_offset;
1990 if (block_size > 8 * 4096)
1991 block_size = 8 * 4096;
1993 aub_write_trace_block(bo, type, subtype, offset + sub_offset,
1999 aub_write_bo(drm_intel_bo *bo)
2001 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2002 uint32_t offset = 0;
2005 aub_bo_get_address(bo);
2007 /* Write out each annotated section separately. */
2008 for (i = 0; i < bo_gem->aub_annotation_count; ++i) {
2009 drm_intel_aub_annotation *annotation =
2010 &bo_gem->aub_annotations[i];
2011 uint32_t ending_offset = annotation->ending_offset;
2012 if (ending_offset > bo->size)
2013 ending_offset = bo->size;
2014 if (ending_offset > offset) {
2015 aub_write_large_trace_block(bo, annotation->type,
2016 annotation->subtype,
2018 ending_offset - offset);
2019 offset = ending_offset;
2023 /* Write out any remaining unannotated data */
2024 if (offset < bo->size) {
2025 aub_write_large_trace_block(bo, AUB_TRACE_TYPE_NOTYPE, 0,
2026 offset, bo->size - offset);
2031 * Make a ringbuffer on fly and dump it
2034 aub_build_dump_ringbuffer(drm_intel_bufmgr_gem *bufmgr_gem,
2035 uint32_t batch_buffer, int ring_flag)
2037 uint32_t ringbuffer[4096];
2038 int ring = AUB_TRACE_TYPE_RING_PRB0; /* The default ring */
2041 if (ring_flag == I915_EXEC_BSD)
2042 ring = AUB_TRACE_TYPE_RING_PRB1;
2043 else if (ring_flag == I915_EXEC_BLT)
2044 ring = AUB_TRACE_TYPE_RING_PRB2;
2046 /* Make a ring buffer to execute our batchbuffer. */
2047 memset(ringbuffer, 0, sizeof(ringbuffer));
2048 if (bufmgr_gem->gen >= 8) {
2049 ringbuffer[ring_count++] = AUB_MI_BATCH_BUFFER_START | (3 - 2);
2050 ringbuffer[ring_count++] = batch_buffer;
2051 ringbuffer[ring_count++] = 0;
2053 ringbuffer[ring_count++] = AUB_MI_BATCH_BUFFER_START;
2054 ringbuffer[ring_count++] = batch_buffer;
2057 /* Write out the ring. This appears to trigger execution of
2058 * the ring in the simulator.
2061 CMD_AUB_TRACE_HEADER_BLOCK |
2062 ((bufmgr_gem->gen >= 8 ? 6 : 5) - 2));
2064 AUB_TRACE_MEMTYPE_GTT | ring | AUB_TRACE_OP_COMMAND_WRITE);
2065 aub_out(bufmgr_gem, 0); /* general/surface subtype */
2066 aub_out(bufmgr_gem, bufmgr_gem->aub_offset);
2067 aub_out(bufmgr_gem, ring_count * 4);
2068 if (bufmgr_gem->gen >= 8)
2069 aub_out(bufmgr_gem, 0);
2071 /* FIXME: Need some flush operations here? */
2072 aub_out_data(bufmgr_gem, ringbuffer, ring_count * 4);
2074 /* Update offset pointer */
2075 bufmgr_gem->aub_offset += 4096;
2079 drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo,
2080 int x1, int y1, int width, int height,
2081 enum aub_dump_bmp_format format,
2082 int pitch, int offset)
2084 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2085 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
2089 case AUB_DUMP_BMP_FORMAT_8BIT:
2092 case AUB_DUMP_BMP_FORMAT_ARGB_4444:
2095 case AUB_DUMP_BMP_FORMAT_ARGB_0888:
2096 case AUB_DUMP_BMP_FORMAT_ARGB_8888:
2100 printf("Unknown AUB dump format %d\n", format);
2104 if (!bufmgr_gem->aub_file)
2107 aub_out(bufmgr_gem, CMD_AUB_DUMP_BMP | 4);
2108 aub_out(bufmgr_gem, (y1 << 16) | x1);
2113 aub_out(bufmgr_gem, (height << 16) | width);
2114 aub_out(bufmgr_gem, bo_gem->aub_offset + offset);
2116 ((bo_gem->tiling_mode != I915_TILING_NONE) ? (1 << 2) : 0) |
2117 ((bo_gem->tiling_mode == I915_TILING_Y) ? (1 << 3) : 0));
2121 aub_exec(drm_intel_bo *bo, int ring_flag, int used)
2123 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2124 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2126 bool batch_buffer_needs_annotations;
2128 if (!bufmgr_gem->aub_file)
2131 /* If batch buffer is not annotated, annotate it the best we
2134 batch_buffer_needs_annotations = bo_gem->aub_annotation_count == 0;
2135 if (batch_buffer_needs_annotations) {
2136 drm_intel_aub_annotation annotations[2] = {
2137 { AUB_TRACE_TYPE_BATCH, 0, used },
2138 { AUB_TRACE_TYPE_NOTYPE, 0, bo->size }
2140 drm_intel_bufmgr_gem_set_aub_annotations(bo, annotations, 2);
2143 /* Write out all buffers to AUB memory */
2144 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2145 aub_write_bo(bufmgr_gem->exec_bos[i]);
2148 /* Remove any annotations we added */
2149 if (batch_buffer_needs_annotations)
2150 drm_intel_bufmgr_gem_set_aub_annotations(bo, NULL, 0);
2152 /* Dump ring buffer */
2153 aub_build_dump_ringbuffer(bufmgr_gem, bo_gem->aub_offset, ring_flag);
2155 fflush(bufmgr_gem->aub_file);
2158 * One frame has been dumped. So reset the aub_offset for the next frame.
2160 * FIXME: Can we do this?
2162 bufmgr_gem->aub_offset = 0x10000;
2166 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
2167 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
2169 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2170 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2171 struct drm_i915_gem_execbuffer execbuf;
2174 if (bo_gem->has_error)
2177 pthread_mutex_lock(&bufmgr_gem->lock);
2178 /* Update indices and set up the validate list. */
2179 drm_intel_gem_bo_process_reloc(bo);
2181 /* Add the batch buffer to the validation list. There are no
2182 * relocations pointing to it.
2184 drm_intel_add_validate_buffer(bo);
2187 execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects;
2188 execbuf.buffer_count = bufmgr_gem->exec_count;
2189 execbuf.batch_start_offset = 0;
2190 execbuf.batch_len = used;
2191 execbuf.cliprects_ptr = (uintptr_t) cliprects;
2192 execbuf.num_cliprects = num_cliprects;
2196 ret = drmIoctl(bufmgr_gem->fd,
2197 DRM_IOCTL_I915_GEM_EXECBUFFER,
2201 if (errno == ENOSPC) {
2202 DBG("Execbuffer fails to pin. "
2203 "Estimate: %u. Actual: %u. Available: %u\n",
2204 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
2207 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
2210 (unsigned int)bufmgr_gem->gtt_size);
2213 drm_intel_update_buffer_offsets(bufmgr_gem);
2215 if (bufmgr_gem->bufmgr.debug)
2216 drm_intel_gem_dump_validation_list(bufmgr_gem);
2218 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2219 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
2220 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2222 /* Disconnect the buffer from the validate list */
2223 bo_gem->validate_index = -1;
2224 bufmgr_gem->exec_bos[i] = NULL;
2226 bufmgr_gem->exec_count = 0;
2227 pthread_mutex_unlock(&bufmgr_gem->lock);
2233 do_exec2(drm_intel_bo *bo, int used, drm_intel_context *ctx,
2234 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
2237 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
2238 struct drm_i915_gem_execbuffer2 execbuf;
2242 switch (flags & 0x7) {
2246 if (!bufmgr_gem->has_blt)
2250 if (!bufmgr_gem->has_bsd)
2253 case I915_EXEC_VEBOX:
2254 if (!bufmgr_gem->has_vebox)
2257 case I915_EXEC_RENDER:
2258 case I915_EXEC_DEFAULT:
2262 pthread_mutex_lock(&bufmgr_gem->lock);
2263 /* Update indices and set up the validate list. */
2264 drm_intel_gem_bo_process_reloc2(bo);
2266 /* Add the batch buffer to the validation list. There are no relocations
2269 drm_intel_add_validate_buffer2(bo, 0);
2272 execbuf.buffers_ptr = (uintptr_t)bufmgr_gem->exec2_objects;
2273 execbuf.buffer_count = bufmgr_gem->exec_count;
2274 execbuf.batch_start_offset = 0;
2275 execbuf.batch_len = used;
2276 execbuf.cliprects_ptr = (uintptr_t)cliprects;
2277 execbuf.num_cliprects = num_cliprects;
2280 execbuf.flags = flags;
2282 i915_execbuffer2_set_context_id(execbuf, 0);
2284 i915_execbuffer2_set_context_id(execbuf, ctx->ctx_id);
2287 aub_exec(bo, flags, used);
2289 if (bufmgr_gem->no_exec)
2290 goto skip_execution;
2292 ret = drmIoctl(bufmgr_gem->fd,
2293 DRM_IOCTL_I915_GEM_EXECBUFFER2,
2297 if (ret == -ENOSPC) {
2298 DBG("Execbuffer fails to pin. "
2299 "Estimate: %u. Actual: %u. Available: %u\n",
2300 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
2301 bufmgr_gem->exec_count),
2302 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
2303 bufmgr_gem->exec_count),
2304 (unsigned int) bufmgr_gem->gtt_size);
2307 drm_intel_update_buffer_offsets2(bufmgr_gem);
2310 if (bufmgr_gem->bufmgr.debug)
2311 drm_intel_gem_dump_validation_list(bufmgr_gem);
2313 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2314 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
2315 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
2317 /* Disconnect the buffer from the validate list */
2318 bo_gem->validate_index = -1;
2319 bufmgr_gem->exec_bos[i] = NULL;
2321 bufmgr_gem->exec_count = 0;
2322 pthread_mutex_unlock(&bufmgr_gem->lock);
2328 drm_intel_gem_bo_exec2(drm_intel_bo *bo, int used,
2329 drm_clip_rect_t *cliprects, int num_cliprects,
2332 return do_exec2(bo, used, NULL, cliprects, num_cliprects, DR4,
2337 drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used,
2338 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
2341 return do_exec2(bo, used, NULL, cliprects, num_cliprects, DR4,
2346 drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx,
2347 int used, unsigned int flags)
2349 return do_exec2(bo, used, ctx, NULL, 0, 0, flags);
2353 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
2355 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2356 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2357 struct drm_i915_gem_pin pin;
2361 pin.handle = bo_gem->gem_handle;
2362 pin.alignment = alignment;
2364 ret = drmIoctl(bufmgr_gem->fd,
2365 DRM_IOCTL_I915_GEM_PIN,
2370 bo->offset = pin.offset;
2375 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
2377 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2378 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2379 struct drm_i915_gem_unpin unpin;
2383 unpin.handle = bo_gem->gem_handle;
2385 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
2393 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
2394 uint32_t tiling_mode,
2397 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2398 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2399 struct drm_i915_gem_set_tiling set_tiling;
2402 if (bo_gem->global_name == 0 &&
2403 tiling_mode == bo_gem->tiling_mode &&
2404 stride == bo_gem->stride)
2407 memset(&set_tiling, 0, sizeof(set_tiling));
2409 /* set_tiling is slightly broken and overwrites the
2410 * input on the error path, so we have to open code
2413 set_tiling.handle = bo_gem->gem_handle;
2414 set_tiling.tiling_mode = tiling_mode;
2415 set_tiling.stride = stride;
2417 ret = ioctl(bufmgr_gem->fd,
2418 DRM_IOCTL_I915_GEM_SET_TILING,
2420 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
2424 bo_gem->tiling_mode = set_tiling.tiling_mode;
2425 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
2426 bo_gem->stride = set_tiling.stride;
2431 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
2434 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2435 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2438 /* Linear buffers have no stride. By ensuring that we only ever use
2439 * stride 0 with linear buffers, we simplify our code.
2441 if (*tiling_mode == I915_TILING_NONE)
2444 ret = drm_intel_gem_bo_set_tiling_internal(bo, *tiling_mode, stride);
2446 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
2448 *tiling_mode = bo_gem->tiling_mode;
2453 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
2454 uint32_t * swizzle_mode)
2456 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2458 *tiling_mode = bo_gem->tiling_mode;
2459 *swizzle_mode = bo_gem->swizzle_mode;
2464 drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr, int prime_fd, int size)
2466 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
2469 drm_intel_bo_gem *bo_gem;
2470 struct drm_i915_gem_get_tiling get_tiling;
2471 drmMMListHead *list;
2473 ret = drmPrimeFDToHandle(bufmgr_gem->fd, prime_fd, &handle);
2476 * See if the kernel has already returned this buffer to us. Just as
2477 * for named buffers, we must not create two bo's pointing at the same
2480 for (list = bufmgr_gem->named.next;
2481 list != &bufmgr_gem->named;
2482 list = list->next) {
2483 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, list, name_list);
2484 if (bo_gem->gem_handle == handle) {
2485 drm_intel_gem_bo_reference(&bo_gem->bo);
2491 fprintf(stderr,"ret is %d %d\n", ret, errno);
2495 bo_gem = calloc(1, sizeof(*bo_gem));
2499 /* Determine size of bo. The fd-to-handle ioctl really should
2500 * return the size, but it doesn't. If we have kernel 3.12 or
2501 * later, we can lseek on the prime fd to get the size. Older
2502 * kernels will just fail, in which case we fall back to the
2503 * provided (estimated or guess size). */
2504 ret = lseek(prime_fd, 0, SEEK_END);
2506 bo_gem->bo.size = ret;
2508 bo_gem->bo.size = size;
2510 bo_gem->bo.handle = handle;
2511 bo_gem->bo.bufmgr = bufmgr;
2513 bo_gem->gem_handle = handle;
2515 atomic_set(&bo_gem->refcount, 1);
2517 bo_gem->name = "prime";
2518 bo_gem->validate_index = -1;
2519 bo_gem->reloc_tree_fences = 0;
2520 bo_gem->used_as_reloc_target = false;
2521 bo_gem->has_error = false;
2522 bo_gem->reusable = false;
2524 DRMINITLISTHEAD(&bo_gem->vma_list);
2525 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
2527 VG_CLEAR(get_tiling);
2528 get_tiling.handle = bo_gem->gem_handle;
2529 ret = drmIoctl(bufmgr_gem->fd,
2530 DRM_IOCTL_I915_GEM_GET_TILING,
2533 drm_intel_gem_bo_unreference(&bo_gem->bo);
2536 bo_gem->tiling_mode = get_tiling.tiling_mode;
2537 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
2538 /* XXX stride is unknown */
2539 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
2545 drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int *prime_fd)
2547 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2548 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2550 if (DRMLISTEMPTY(&bo_gem->name_list))
2551 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
2553 if (drmPrimeHandleToFD(bufmgr_gem->fd, bo_gem->gem_handle,
2554 DRM_CLOEXEC, prime_fd) != 0)
2557 bo_gem->reusable = false;
2563 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name)
2565 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2566 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2569 if (!bo_gem->global_name) {
2570 struct drm_gem_flink flink;
2573 flink.handle = bo_gem->gem_handle;
2575 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink);
2579 bo_gem->global_name = flink.name;
2580 bo_gem->reusable = false;
2582 if (DRMLISTEMPTY(&bo_gem->name_list))
2583 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
2586 *name = bo_gem->global_name;
2591 * Enables unlimited caching of buffer objects for reuse.
2593 * This is potentially very memory expensive, as the cache at each bucket
2594 * size is only bounded by how many buffers of that size we've managed to have
2595 * in flight at once.
2598 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
2600 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
2602 bufmgr_gem->bo_reuse = true;
2606 * Enable use of fenced reloc type.
2608 * New code should enable this to avoid unnecessary fence register
2609 * allocation. If this option is not enabled, all relocs will have fence
2610 * register allocated.
2613 drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr)
2615 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2617 if (bufmgr_gem->bufmgr.bo_exec == drm_intel_gem_bo_exec2)
2618 bufmgr_gem->fenced_relocs = true;
2622 * Return the additional aperture space required by the tree of buffer objects
2626 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
2628 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2632 if (bo == NULL || bo_gem->included_in_check_aperture)
2636 bo_gem->included_in_check_aperture = true;
2638 for (i = 0; i < bo_gem->reloc_count; i++)
2640 drm_intel_gem_bo_get_aperture_space(bo_gem->
2641 reloc_target_info[i].bo);
2647 * Count the number of buffers in this list that need a fence reg
2649 * If the count is greater than the number of available regs, we'll have
2650 * to ask the caller to resubmit a batch with fewer tiled buffers.
2652 * This function over-counts if the same buffer is used multiple times.
2655 drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count)
2658 unsigned int total = 0;
2660 for (i = 0; i < count; i++) {
2661 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
2666 total += bo_gem->reloc_tree_fences;
2672 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
2673 * for the next drm_intel_bufmgr_check_aperture_space() call.
2676 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
2678 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2681 if (bo == NULL || !bo_gem->included_in_check_aperture)
2684 bo_gem->included_in_check_aperture = false;
2686 for (i = 0; i < bo_gem->reloc_count; i++)
2687 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->
2688 reloc_target_info[i].bo);
2692 * Return a conservative estimate for the amount of aperture required
2693 * for a collection of buffers. This may double-count some buffers.
2696 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
2699 unsigned int total = 0;
2701 for (i = 0; i < count; i++) {
2702 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
2704 total += bo_gem->reloc_tree_size;
2710 * Return the amount of aperture needed for a collection of buffers.
2711 * This avoids double counting any buffers, at the cost of looking
2712 * at every buffer in the set.
2715 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
2718 unsigned int total = 0;
2720 for (i = 0; i < count; i++) {
2721 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
2722 /* For the first buffer object in the array, we get an
2723 * accurate count back for its reloc_tree size (since nothing
2724 * had been flagged as being counted yet). We can save that
2725 * value out as a more conservative reloc_tree_size that
2726 * avoids double-counting target buffers. Since the first
2727 * buffer happens to usually be the batch buffer in our
2728 * callers, this can pull us back from doing the tree
2729 * walk on every new batch emit.
2732 drm_intel_bo_gem *bo_gem =
2733 (drm_intel_bo_gem *) bo_array[i];
2734 bo_gem->reloc_tree_size = total;
2738 for (i = 0; i < count; i++)
2739 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
2744 * Return -1 if the batchbuffer should be flushed before attempting to
2745 * emit rendering referencing the buffers pointed to by bo_array.
2747 * This is required because if we try to emit a batchbuffer with relocations
2748 * to a tree of buffers that won't simultaneously fit in the aperture,
2749 * the rendering will return an error at a point where the software is not
2750 * prepared to recover from it.
2752 * However, we also want to emit the batchbuffer significantly before we reach
2753 * the limit, as a series of batchbuffers each of which references buffers
2754 * covering almost all of the aperture means that at each emit we end up
2755 * waiting to evict a buffer from the last rendering, and we get synchronous
2756 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
2757 * get better parallelism.
2760 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
2762 drm_intel_bufmgr_gem *bufmgr_gem =
2763 (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr;
2764 unsigned int total = 0;
2765 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
2768 /* Check for fence reg constraints if necessary */
2769 if (bufmgr_gem->available_fences) {
2770 total_fences = drm_intel_gem_total_fences(bo_array, count);
2771 if (total_fences > bufmgr_gem->available_fences)
2775 total = drm_intel_gem_estimate_batch_space(bo_array, count);
2777 if (total > threshold)
2778 total = drm_intel_gem_compute_batch_space(bo_array, count);
2780 if (total > threshold) {
2781 DBG("check_space: overflowed available aperture, "
2783 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
2786 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024,
2787 (int)bufmgr_gem->gtt_size / 1024);
2793 * Disable buffer reuse for objects which are shared with the kernel
2794 * as scanout buffers
2797 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
2799 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2801 bo_gem->reusable = false;
2806 drm_intel_gem_bo_is_reusable(drm_intel_bo *bo)
2808 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2810 return bo_gem->reusable;
2814 _drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2816 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2819 for (i = 0; i < bo_gem->reloc_count; i++) {
2820 if (bo_gem->reloc_target_info[i].bo == target_bo)
2822 if (bo == bo_gem->reloc_target_info[i].bo)
2824 if (_drm_intel_gem_bo_references(bo_gem->reloc_target_info[i].bo,
2832 /** Return true if target_bo is referenced by bo's relocation tree. */
2834 drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2836 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
2838 if (bo == NULL || target_bo == NULL)
2840 if (target_bo_gem->used_as_reloc_target)
2841 return _drm_intel_gem_bo_references(bo, target_bo);
2846 add_bucket(drm_intel_bufmgr_gem *bufmgr_gem, int size)
2848 unsigned int i = bufmgr_gem->num_buckets;
2850 assert(i < ARRAY_SIZE(bufmgr_gem->cache_bucket));
2852 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
2853 bufmgr_gem->cache_bucket[i].size = size;
2854 bufmgr_gem->num_buckets++;
2858 init_cache_buckets(drm_intel_bufmgr_gem *bufmgr_gem)
2860 unsigned long size, cache_max_size = 64 * 1024 * 1024;
2862 /* OK, so power of two buckets was too wasteful of memory.
2863 * Give 3 other sizes between each power of two, to hopefully
2864 * cover things accurately enough. (The alternative is
2865 * probably to just go for exact matching of sizes, and assume
2866 * that for things like composited window resize the tiled
2867 * width/height alignment and rounding of sizes to pages will
2868 * get us useful cache hit rates anyway)
2870 add_bucket(bufmgr_gem, 4096);
2871 add_bucket(bufmgr_gem, 4096 * 2);
2872 add_bucket(bufmgr_gem, 4096 * 3);
2874 /* Initialize the linked lists for BO reuse cache. */
2875 for (size = 4 * 4096; size <= cache_max_size; size *= 2) {
2876 add_bucket(bufmgr_gem, size);
2878 add_bucket(bufmgr_gem, size + size * 1 / 4);
2879 add_bucket(bufmgr_gem, size + size * 2 / 4);
2880 add_bucket(bufmgr_gem, size + size * 3 / 4);
2885 drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr, int limit)
2887 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2889 bufmgr_gem->vma_max = limit;
2891 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
2895 * Get the PCI ID for the device. This can be overridden by setting the
2896 * INTEL_DEVID_OVERRIDE environment variable to the desired ID.
2899 get_pci_device_id(drm_intel_bufmgr_gem *bufmgr_gem)
2901 char *devid_override;
2904 drm_i915_getparam_t gp;
2906 if (geteuid() == getuid()) {
2907 devid_override = getenv("INTEL_DEVID_OVERRIDE");
2908 if (devid_override) {
2909 bufmgr_gem->no_exec = true;
2910 return strtod(devid_override, NULL);
2916 gp.param = I915_PARAM_CHIPSET_ID;
2918 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2920 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
2921 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
2927 drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr)
2929 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2931 return bufmgr_gem->pci_device;
2935 * Sets the AUB filename.
2937 * This function has to be called before drm_intel_bufmgr_gem_set_aub_dump()
2938 * for it to have any effect.
2941 drm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr,
2942 const char *filename)
2944 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2946 free(bufmgr_gem->aub_filename);
2948 bufmgr_gem->aub_filename = strdup(filename);
2952 * Sets up AUB dumping.
2954 * This is a trace file format that can be used with the simulator.
2955 * Packets are emitted in a format somewhat like GPU command packets.
2956 * You can set up a GTT and upload your objects into the referenced
2957 * space, then send off batchbuffers and get BMPs out the other end.
2960 drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable)
2962 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2963 int entry = 0x200003;
2965 int gtt_size = 0x10000;
2966 const char *filename;
2969 if (bufmgr_gem->aub_file) {
2970 fclose(bufmgr_gem->aub_file);
2971 bufmgr_gem->aub_file = NULL;
2976 if (geteuid() != getuid())
2979 if (bufmgr_gem->aub_filename)
2980 filename = bufmgr_gem->aub_filename;
2982 filename = "intel.aub";
2983 bufmgr_gem->aub_file = fopen(filename, "w+");
2984 if (!bufmgr_gem->aub_file)
2987 /* Start allocating objects from just after the GTT. */
2988 bufmgr_gem->aub_offset = gtt_size;
2990 /* Start with a (required) version packet. */
2991 aub_out(bufmgr_gem, CMD_AUB_HEADER | (13 - 2));
2993 (4 << AUB_HEADER_MAJOR_SHIFT) |
2994 (0 << AUB_HEADER_MINOR_SHIFT));
2995 for (i = 0; i < 8; i++) {
2996 aub_out(bufmgr_gem, 0); /* app name */
2998 aub_out(bufmgr_gem, 0); /* timestamp */
2999 aub_out(bufmgr_gem, 0); /* timestamp */
3000 aub_out(bufmgr_gem, 0); /* comment len */
3002 /* Set up the GTT. The max we can handle is 256M */
3003 aub_out(bufmgr_gem, CMD_AUB_TRACE_HEADER_BLOCK | ((bufmgr_gem->gen >= 8 ? 6 : 5) - 2));
3004 aub_out(bufmgr_gem, AUB_TRACE_MEMTYPE_NONLOCAL | 0 | AUB_TRACE_OP_DATA_WRITE);
3005 aub_out(bufmgr_gem, 0); /* subtype */
3006 aub_out(bufmgr_gem, 0); /* offset */
3007 aub_out(bufmgr_gem, gtt_size); /* size */
3008 if (bufmgr_gem->gen >= 8)
3009 aub_out(bufmgr_gem, 0);
3010 for (i = 0x000; i < gtt_size; i += 4, entry += 0x1000) {
3011 aub_out(bufmgr_gem, entry);
3016 drm_intel_gem_context_create(drm_intel_bufmgr *bufmgr)
3018 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3019 struct drm_i915_gem_context_create create;
3020 drm_intel_context *context = NULL;
3023 context = calloc(1, sizeof(*context));
3028 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE, &create);
3030 DBG("DRM_IOCTL_I915_GEM_CONTEXT_CREATE failed: %s\n",
3036 context->ctx_id = create.ctx_id;
3037 context->bufmgr = bufmgr;
3043 drm_intel_gem_context_destroy(drm_intel_context *ctx)
3045 drm_intel_bufmgr_gem *bufmgr_gem;
3046 struct drm_i915_gem_context_destroy destroy;
3054 bufmgr_gem = (drm_intel_bufmgr_gem *)ctx->bufmgr;
3055 destroy.ctx_id = ctx->ctx_id;
3056 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_CONTEXT_DESTROY,
3059 fprintf(stderr, "DRM_IOCTL_I915_GEM_CONTEXT_DESTROY failed: %s\n",
3066 drm_intel_get_reset_stats(drm_intel_context *ctx,
3067 uint32_t *reset_count,
3071 drm_intel_bufmgr_gem *bufmgr_gem;
3072 struct drm_i915_reset_stats stats;
3078 memset(&stats, 0, sizeof(stats));
3080 bufmgr_gem = (drm_intel_bufmgr_gem *)ctx->bufmgr;
3081 stats.ctx_id = ctx->ctx_id;
3082 ret = drmIoctl(bufmgr_gem->fd,
3083 DRM_IOCTL_I915_GET_RESET_STATS,
3086 if (reset_count != NULL)
3087 *reset_count = stats.reset_count;
3090 *active = stats.batch_active;
3092 if (pending != NULL)
3093 *pending = stats.batch_pending;
3100 drm_intel_reg_read(drm_intel_bufmgr *bufmgr,
3104 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3105 struct drm_i915_reg_read reg_read;
3109 reg_read.offset = offset;
3111 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_REG_READ, ®_read);
3113 *result = reg_read.val;
3119 * Annotate the given bo for use in aub dumping.
3121 * \param annotations is an array of drm_intel_aub_annotation objects
3122 * describing the type of data in various sections of the bo. Each
3123 * element of the array specifies the type and subtype of a section of
3124 * the bo, and the past-the-end offset of that section. The elements
3125 * of \c annotations must be sorted so that ending_offset is
3128 * \param count is the number of elements in the \c annotations array.
3129 * If \c count is zero, then \c annotations will not be dereferenced.
3131 * Annotations are copied into a private data structure, so caller may
3132 * re-use the memory pointed to by \c annotations after the call
3135 * Annotations are stored for the lifetime of the bo; to reset to the
3136 * default state (no annotations), call this function with a \c count
3140 drm_intel_bufmgr_gem_set_aub_annotations(drm_intel_bo *bo,
3141 drm_intel_aub_annotation *annotations,
3144 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
3145 unsigned size = sizeof(*annotations) * count;
3146 drm_intel_aub_annotation *new_annotations =
3147 count > 0 ? realloc(bo_gem->aub_annotations, size) : NULL;
3148 if (new_annotations == NULL) {
3149 free(bo_gem->aub_annotations);
3150 bo_gem->aub_annotations = NULL;
3151 bo_gem->aub_annotation_count = 0;
3154 memcpy(new_annotations, annotations, size);
3155 bo_gem->aub_annotations = new_annotations;
3156 bo_gem->aub_annotation_count = count;
3160 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
3161 * and manage map buffer objections.
3163 * \param fd File descriptor of the opened DRM device.
3166 drm_intel_bufmgr_gem_init(int fd, int batch_size)
3168 drm_intel_bufmgr_gem *bufmgr_gem;
3169 struct drm_i915_gem_get_aperture aperture;
3170 drm_i915_getparam_t gp;
3174 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
3175 if (bufmgr_gem == NULL)
3178 bufmgr_gem->fd = fd;
3180 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
3185 ret = drmIoctl(bufmgr_gem->fd,
3186 DRM_IOCTL_I915_GEM_GET_APERTURE,
3190 bufmgr_gem->gtt_size = aperture.aper_available_size;
3192 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
3194 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
3195 fprintf(stderr, "Assuming %dkB available aperture size.\n"
3196 "May lead to reduced performance or incorrect "
3198 (int)bufmgr_gem->gtt_size / 1024);
3201 bufmgr_gem->pci_device = get_pci_device_id(bufmgr_gem);
3203 if (IS_GEN2(bufmgr_gem->pci_device))
3204 bufmgr_gem->gen = 2;
3205 else if (IS_GEN3(bufmgr_gem->pci_device))
3206 bufmgr_gem->gen = 3;
3207 else if (IS_GEN4(bufmgr_gem->pci_device))
3208 bufmgr_gem->gen = 4;
3209 else if (IS_GEN5(bufmgr_gem->pci_device))
3210 bufmgr_gem->gen = 5;
3211 else if (IS_GEN6(bufmgr_gem->pci_device))
3212 bufmgr_gem->gen = 6;
3213 else if (IS_GEN7(bufmgr_gem->pci_device))
3214 bufmgr_gem->gen = 7;
3215 else if (IS_GEN8(bufmgr_gem->pci_device))
3216 bufmgr_gem->gen = 8;
3222 if (IS_GEN3(bufmgr_gem->pci_device) &&
3223 bufmgr_gem->gtt_size > 256*1024*1024) {
3224 /* The unmappable part of gtt on gen 3 (i.e. above 256MB) can't
3225 * be used for tiled blits. To simplify the accounting, just
3226 * substract the unmappable part (fixed to 256MB on all known
3227 * gen3 devices) if the kernel advertises it. */
3228 bufmgr_gem->gtt_size -= 256*1024*1024;
3234 gp.param = I915_PARAM_HAS_EXECBUF2;
3235 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3239 gp.param = I915_PARAM_HAS_BSD;
3240 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3241 bufmgr_gem->has_bsd = ret == 0;
3243 gp.param = I915_PARAM_HAS_BLT;
3244 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3245 bufmgr_gem->has_blt = ret == 0;
3247 gp.param = I915_PARAM_HAS_RELAXED_FENCING;
3248 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3249 bufmgr_gem->has_relaxed_fencing = ret == 0;
3251 gp.param = I915_PARAM_HAS_WAIT_TIMEOUT;
3252 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3253 bufmgr_gem->has_wait_timeout = ret == 0;
3255 gp.param = I915_PARAM_HAS_LLC;
3256 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3258 /* Kernel does not supports HAS_LLC query, fallback to GPU
3259 * generation detection and assume that we have LLC on GEN6/7
3261 bufmgr_gem->has_llc = (IS_GEN6(bufmgr_gem->pci_device) |
3262 IS_GEN7(bufmgr_gem->pci_device));
3264 bufmgr_gem->has_llc = *gp.value;
3266 gp.param = I915_PARAM_HAS_VEBOX;
3267 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3268 bufmgr_gem->has_vebox = (ret == 0) & (*gp.value > 0);
3270 if (bufmgr_gem->gen < 4) {
3271 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
3272 gp.value = &bufmgr_gem->available_fences;
3273 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3275 fprintf(stderr, "get fences failed: %d [%d]\n", ret,
3277 fprintf(stderr, "param: %d, val: %d\n", gp.param,
3279 bufmgr_gem->available_fences = 0;
3281 /* XXX The kernel reports the total number of fences,
3282 * including any that may be pinned.
3284 * We presume that there will be at least one pinned
3285 * fence for the scanout buffer, but there may be more
3286 * than one scanout and the user may be manually
3287 * pinning buffers. Let's move to execbuffer2 and
3288 * thereby forget the insanity of using fences...
3290 bufmgr_gem->available_fences -= 2;
3291 if (bufmgr_gem->available_fences < 0)
3292 bufmgr_gem->available_fences = 0;
3296 /* Let's go with one relocation per every 2 dwords (but round down a bit
3297 * since a power of two will mean an extra page allocation for the reloc
3300 * Every 4 was too few for the blender benchmark.
3302 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
3304 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
3305 bufmgr_gem->bufmgr.bo_alloc_for_render =
3306 drm_intel_gem_bo_alloc_for_render;
3307 bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled;
3308 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
3309 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
3310 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
3311 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
3312 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
3313 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
3314 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
3315 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
3316 bufmgr_gem->bufmgr.bo_emit_reloc_fence = drm_intel_gem_bo_emit_reloc_fence;
3317 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
3318 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
3319 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
3320 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
3321 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
3322 /* Use the new one if available */
3324 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec2;
3325 bufmgr_gem->bufmgr.bo_mrb_exec = drm_intel_gem_bo_mrb_exec2;
3327 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
3328 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
3329 bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise;
3330 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_destroy;
3331 bufmgr_gem->bufmgr.debug = 0;
3332 bufmgr_gem->bufmgr.check_aperture_space =
3333 drm_intel_gem_check_aperture_space;
3334 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
3335 bufmgr_gem->bufmgr.bo_is_reusable = drm_intel_gem_bo_is_reusable;
3336 bufmgr_gem->bufmgr.get_pipe_from_crtc_id =
3337 drm_intel_gem_get_pipe_from_crtc_id;
3338 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
3340 DRMINITLISTHEAD(&bufmgr_gem->named);
3341 init_cache_buckets(bufmgr_gem);
3343 DRMINITLISTHEAD(&bufmgr_gem->vma_cache);
3344 bufmgr_gem->vma_max = -1; /* unlimited by default */
3346 return &bufmgr_gem->bufmgr;