1 /**************************************************************************
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007-2012 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 **************************************************************************/
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
42 #include <xf86atomic.h>
50 #include <sys/ioctl.h>
53 #include <sys/types.h>
58 #define ETIME ETIMEDOUT
61 #include "libdrm_lists.h"
62 #include "intel_bufmgr.h"
63 #include "intel_bufmgr_priv.h"
64 #include "intel_chipset.h"
65 #include "intel_aub.h"
78 #define VG_CLEAR(s) VG(memset(&s, 0, sizeof(s)))
80 #define DBG(...) do { \
81 if (bufmgr_gem->bufmgr.debug) \
82 fprintf(stderr, __VA_ARGS__); \
85 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
87 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
89 struct drm_intel_gem_bo_bucket {
94 typedef struct _drm_intel_bufmgr_gem {
95 drm_intel_bufmgr bufmgr;
103 pthread_mutex_t lock;
105 struct drm_i915_gem_exec_object *exec_objects;
106 struct drm_i915_gem_exec_object2 *exec2_objects;
107 drm_intel_bo **exec_bos;
111 /** Array of lists of cached gem objects of power-of-two sizes */
112 struct drm_intel_gem_bo_bucket cache_bucket[14 * 4];
116 drmMMListHead managers;
119 drmMMListHead vma_cache;
120 int vma_count, vma_open, vma_max;
123 int available_fences;
126 unsigned int has_bsd : 1;
127 unsigned int has_blt : 1;
128 unsigned int has_relaxed_fencing : 1;
129 unsigned int has_llc : 1;
130 unsigned int has_wait_timeout : 1;
131 unsigned int bo_reuse : 1;
132 unsigned int no_exec : 1;
133 unsigned int has_vebox : 1;
139 } drm_intel_bufmgr_gem;
141 #define DRM_INTEL_RELOC_FENCE (1<<0)
143 typedef struct _drm_intel_reloc_target_info {
146 } drm_intel_reloc_target;
148 struct _drm_intel_bo_gem {
156 * Kenel-assigned global name for this object
158 * List contains both flink named and prime fd'd objects
160 unsigned int global_name;
161 drmMMListHead name_list;
164 * Index of the buffer within the validation list while preparing a
165 * batchbuffer execution.
170 * Current tiling mode
172 uint32_t tiling_mode;
173 uint32_t swizzle_mode;
174 unsigned long stride;
178 /** Array passed to the DRM containing relocation information. */
179 struct drm_i915_gem_relocation_entry *relocs;
181 * Array of info structs corresponding to relocs[i].target_handle etc
183 drm_intel_reloc_target *reloc_target_info;
184 /** Number of entries in relocs */
186 /** Mapped address for the buffer, saved across map/unmap cycles */
188 /** GTT virtual address for the buffer, saved across map/unmap cycles */
191 drmMMListHead vma_list;
197 * Boolean of whether this BO and its children have been included in
198 * the current drm_intel_bufmgr_check_aperture_space() total.
200 bool included_in_check_aperture;
203 * Boolean of whether this buffer has been used as a relocation
204 * target and had its size accounted for, and thus can't have any
205 * further relocations added to it.
207 bool used_as_reloc_target;
210 * Boolean of whether we have encountered an error whilst building the relocation tree.
215 * Boolean of whether this buffer can be re-used
220 * Boolean of whether the GPU is definitely not accessing the buffer.
222 * This is only valid when reusable, since non-reusable
223 * buffers are those that have been shared wth other
224 * processes, so we don't know their state.
229 * Size in bytes of this buffer and its relocation descendents.
231 * Used to avoid costly tree walking in
232 * drm_intel_bufmgr_check_aperture in the common case.
237 * Number of potential fence registers required by this buffer and its
240 int reloc_tree_fences;
242 /** Flags that we may need to do the SW_FINSIH ioctl on unmap. */
243 bool mapped_cpu_write;
247 drm_intel_aub_annotation *aub_annotations;
248 unsigned aub_annotation_count;
252 drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count);
255 drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count);
258 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
259 uint32_t * swizzle_mode);
262 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
263 uint32_t tiling_mode,
266 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
269 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo);
271 static void drm_intel_gem_bo_free(drm_intel_bo *bo);
274 drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
275 uint32_t *tiling_mode)
277 unsigned long min_size, max_size;
280 if (*tiling_mode == I915_TILING_NONE)
283 /* 965+ just need multiples of page size for tiling */
284 if (bufmgr_gem->gen >= 4)
285 return ROUND_UP_TO(size, 4096);
287 /* Older chips need powers of two, of at least 512k or 1M */
288 if (bufmgr_gem->gen == 3) {
289 min_size = 1024*1024;
290 max_size = 128*1024*1024;
293 max_size = 64*1024*1024;
296 if (size > max_size) {
297 *tiling_mode = I915_TILING_NONE;
301 /* Do we need to allocate every page for the fence? */
302 if (bufmgr_gem->has_relaxed_fencing)
303 return ROUND_UP_TO(size, 4096);
305 for (i = min_size; i < size; i <<= 1)
312 * Round a given pitch up to the minimum required for X tiling on a
313 * given chip. We use 512 as the minimum to allow for a later tiling
317 drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
318 unsigned long pitch, uint32_t *tiling_mode)
320 unsigned long tile_width;
323 /* If untiled, then just align it so that we can do rendering
324 * to it with the 3D engine.
326 if (*tiling_mode == I915_TILING_NONE)
327 return ALIGN(pitch, 64);
329 if (*tiling_mode == I915_TILING_X
330 || (IS_915(bufmgr_gem->pci_device)
331 && *tiling_mode == I915_TILING_Y))
336 /* 965 is flexible */
337 if (bufmgr_gem->gen >= 4)
338 return ROUND_UP_TO(pitch, tile_width);
340 /* The older hardware has a maximum pitch of 8192 with tiled
341 * surfaces, so fallback to untiled if it's too large.
344 *tiling_mode = I915_TILING_NONE;
345 return ALIGN(pitch, 64);
348 /* Pre-965 needs power of two tile width */
349 for (i = tile_width; i < pitch; i <<= 1)
355 static struct drm_intel_gem_bo_bucket *
356 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
361 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
362 struct drm_intel_gem_bo_bucket *bucket =
363 &bufmgr_gem->cache_bucket[i];
364 if (bucket->size >= size) {
373 drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
377 for (i = 0; i < bufmgr_gem->exec_count; i++) {
378 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
379 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
381 if (bo_gem->relocs == NULL) {
382 DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle,
387 for (j = 0; j < bo_gem->reloc_count; j++) {
388 drm_intel_bo *target_bo = bo_gem->reloc_target_info[j].bo;
389 drm_intel_bo_gem *target_gem =
390 (drm_intel_bo_gem *) target_bo;
392 DBG("%2d: %d (%s)@0x%08llx -> "
393 "%d (%s)@0x%08lx + 0x%08x\n",
395 bo_gem->gem_handle, bo_gem->name,
396 (unsigned long long)bo_gem->relocs[j].offset,
397 target_gem->gem_handle,
400 bo_gem->relocs[j].delta);
406 drm_intel_gem_bo_reference(drm_intel_bo *bo)
408 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
410 atomic_inc(&bo_gem->refcount);
414 * Adds the given buffer to the list of buffers to be validated (moved into the
415 * appropriate memory type) with the next batch submission.
417 * If a buffer is validated multiple times in a batch submission, it ends up
418 * with the intersection of the memory type flags and the union of the
422 drm_intel_add_validate_buffer(drm_intel_bo *bo)
424 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
425 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
428 if (bo_gem->validate_index != -1)
431 /* Extend the array of validation entries as necessary. */
432 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
433 int new_size = bufmgr_gem->exec_size * 2;
438 bufmgr_gem->exec_objects =
439 realloc(bufmgr_gem->exec_objects,
440 sizeof(*bufmgr_gem->exec_objects) * new_size);
441 bufmgr_gem->exec_bos =
442 realloc(bufmgr_gem->exec_bos,
443 sizeof(*bufmgr_gem->exec_bos) * new_size);
444 bufmgr_gem->exec_size = new_size;
447 index = bufmgr_gem->exec_count;
448 bo_gem->validate_index = index;
449 /* Fill in array entry */
450 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
451 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
452 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs;
453 bufmgr_gem->exec_objects[index].alignment = 0;
454 bufmgr_gem->exec_objects[index].offset = 0;
455 bufmgr_gem->exec_bos[index] = bo;
456 bufmgr_gem->exec_count++;
460 drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence)
462 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
463 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
466 if (bo_gem->validate_index != -1) {
468 bufmgr_gem->exec2_objects[bo_gem->validate_index].flags |=
469 EXEC_OBJECT_NEEDS_FENCE;
473 /* Extend the array of validation entries as necessary. */
474 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
475 int new_size = bufmgr_gem->exec_size * 2;
480 bufmgr_gem->exec2_objects =
481 realloc(bufmgr_gem->exec2_objects,
482 sizeof(*bufmgr_gem->exec2_objects) * new_size);
483 bufmgr_gem->exec_bos =
484 realloc(bufmgr_gem->exec_bos,
485 sizeof(*bufmgr_gem->exec_bos) * new_size);
486 bufmgr_gem->exec_size = new_size;
489 index = bufmgr_gem->exec_count;
490 bo_gem->validate_index = index;
491 /* Fill in array entry */
492 bufmgr_gem->exec2_objects[index].handle = bo_gem->gem_handle;
493 bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count;
494 bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
495 bufmgr_gem->exec2_objects[index].alignment = 0;
496 bufmgr_gem->exec2_objects[index].offset = 0;
497 bufmgr_gem->exec_bos[index] = bo;
498 bufmgr_gem->exec2_objects[index].flags = 0;
499 bufmgr_gem->exec2_objects[index].rsvd1 = 0;
500 bufmgr_gem->exec2_objects[index].rsvd2 = 0;
502 bufmgr_gem->exec2_objects[index].flags |=
503 EXEC_OBJECT_NEEDS_FENCE;
505 bufmgr_gem->exec_count++;
508 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
512 drm_intel_bo_gem_set_in_aperture_size(drm_intel_bufmgr_gem *bufmgr_gem,
513 drm_intel_bo_gem *bo_gem)
517 assert(!bo_gem->used_as_reloc_target);
519 /* The older chipsets are far-less flexible in terms of tiling,
520 * and require tiled buffer to be size aligned in the aperture.
521 * This means that in the worst possible case we will need a hole
522 * twice as large as the object in order for it to fit into the
523 * aperture. Optimal packing is for wimps.
525 size = bo_gem->bo.size;
526 if (bufmgr_gem->gen < 4 && bo_gem->tiling_mode != I915_TILING_NONE) {
529 if (bufmgr_gem->has_relaxed_fencing) {
530 if (bufmgr_gem->gen == 3)
531 min_size = 1024*1024;
535 while (min_size < size)
540 /* Account for worst-case alignment. */
544 bo_gem->reloc_tree_size = size;
548 drm_intel_setup_reloc_list(drm_intel_bo *bo)
550 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
551 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
552 unsigned int max_relocs = bufmgr_gem->max_relocs;
554 if (bo->size / 4 < max_relocs)
555 max_relocs = bo->size / 4;
557 bo_gem->relocs = malloc(max_relocs *
558 sizeof(struct drm_i915_gem_relocation_entry));
559 bo_gem->reloc_target_info = malloc(max_relocs *
560 sizeof(drm_intel_reloc_target));
561 if (bo_gem->relocs == NULL || bo_gem->reloc_target_info == NULL) {
562 bo_gem->has_error = true;
564 free (bo_gem->relocs);
565 bo_gem->relocs = NULL;
567 free (bo_gem->reloc_target_info);
568 bo_gem->reloc_target_info = NULL;
577 drm_intel_gem_bo_busy(drm_intel_bo *bo)
579 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
580 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
581 struct drm_i915_gem_busy busy;
584 if (bo_gem->reusable && bo_gem->idle)
588 busy.handle = bo_gem->gem_handle;
590 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
592 bo_gem->idle = !busy.busy;
597 return (ret == 0 && busy.busy);
601 drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem,
602 drm_intel_bo_gem *bo_gem, int state)
604 struct drm_i915_gem_madvise madv;
607 madv.handle = bo_gem->gem_handle;
610 drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
612 return madv.retained;
616 drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
618 return drm_intel_gem_bo_madvise_internal
619 ((drm_intel_bufmgr_gem *) bo->bufmgr,
620 (drm_intel_bo_gem *) bo,
624 /* drop the oldest entries that have been purged by the kernel */
626 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
627 struct drm_intel_gem_bo_bucket *bucket)
629 while (!DRMLISTEMPTY(&bucket->head)) {
630 drm_intel_bo_gem *bo_gem;
632 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
633 bucket->head.next, head);
634 if (drm_intel_gem_bo_madvise_internal
635 (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
638 DRMLISTDEL(&bo_gem->head);
639 drm_intel_gem_bo_free(&bo_gem->bo);
643 static drm_intel_bo *
644 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr,
648 uint32_t tiling_mode,
649 unsigned long stride)
651 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
652 drm_intel_bo_gem *bo_gem;
653 unsigned int page_size = getpagesize();
655 struct drm_intel_gem_bo_bucket *bucket;
656 bool alloc_from_cache;
657 unsigned long bo_size;
658 bool for_render = false;
660 if (flags & BO_ALLOC_FOR_RENDER)
663 /* Round the allocated size up to a power of two number of pages. */
664 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
666 /* If we don't have caching at this size, don't actually round the
669 if (bucket == NULL) {
671 if (bo_size < page_size)
674 bo_size = bucket->size;
677 pthread_mutex_lock(&bufmgr_gem->lock);
678 /* Get a buffer out of the cache if available */
680 alloc_from_cache = false;
681 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) {
683 /* Allocate new render-target BOs from the tail (MRU)
684 * of the list, as it will likely be hot in the GPU
685 * cache and in the aperture for us.
687 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
688 bucket->head.prev, head);
689 DRMLISTDEL(&bo_gem->head);
690 alloc_from_cache = true;
692 /* For non-render-target BOs (where we're probably
693 * going to map it first thing in order to fill it
694 * with data), check if the last BO in the cache is
695 * unbusy, and only reuse in that case. Otherwise,
696 * allocating a new buffer is probably faster than
697 * waiting for the GPU to finish.
699 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
700 bucket->head.next, head);
701 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
702 alloc_from_cache = true;
703 DRMLISTDEL(&bo_gem->head);
707 if (alloc_from_cache) {
708 if (!drm_intel_gem_bo_madvise_internal
709 (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) {
710 drm_intel_gem_bo_free(&bo_gem->bo);
711 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem,
716 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
719 drm_intel_gem_bo_free(&bo_gem->bo);
724 pthread_mutex_unlock(&bufmgr_gem->lock);
726 if (!alloc_from_cache) {
727 struct drm_i915_gem_create create;
729 bo_gem = calloc(1, sizeof(*bo_gem));
733 bo_gem->bo.size = bo_size;
736 create.size = bo_size;
738 ret = drmIoctl(bufmgr_gem->fd,
739 DRM_IOCTL_I915_GEM_CREATE,
741 bo_gem->gem_handle = create.handle;
742 bo_gem->bo.handle = bo_gem->gem_handle;
747 bo_gem->bo.bufmgr = bufmgr;
749 bo_gem->tiling_mode = I915_TILING_NONE;
750 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
753 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
756 drm_intel_gem_bo_free(&bo_gem->bo);
760 DRMINITLISTHEAD(&bo_gem->name_list);
761 DRMINITLISTHEAD(&bo_gem->vma_list);
765 atomic_set(&bo_gem->refcount, 1);
766 bo_gem->validate_index = -1;
767 bo_gem->reloc_tree_fences = 0;
768 bo_gem->used_as_reloc_target = false;
769 bo_gem->has_error = false;
770 bo_gem->reusable = true;
771 bo_gem->aub_annotations = NULL;
772 bo_gem->aub_annotation_count = 0;
774 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
776 DBG("bo_create: buf %d (%s) %ldb\n",
777 bo_gem->gem_handle, bo_gem->name, size);
782 static drm_intel_bo *
783 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
786 unsigned int alignment)
788 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
790 I915_TILING_NONE, 0);
793 static drm_intel_bo *
794 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr,
797 unsigned int alignment)
799 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0,
800 I915_TILING_NONE, 0);
803 static drm_intel_bo *
804 drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
805 int x, int y, int cpp, uint32_t *tiling_mode,
806 unsigned long *pitch, unsigned long flags)
808 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
809 unsigned long size, stride;
813 unsigned long aligned_y, height_alignment;
815 tiling = *tiling_mode;
817 /* If we're tiled, our allocations are in 8 or 32-row blocks,
818 * so failure to align our height means that we won't allocate
821 * If we're untiled, we still have to align to 2 rows high
822 * because the data port accesses 2x2 blocks even if the
823 * bottom row isn't to be rendered, so failure to align means
824 * we could walk off the end of the GTT and fault. This is
825 * documented on 965, and may be the case on older chipsets
826 * too so we try to be careful.
829 height_alignment = 2;
831 if ((bufmgr_gem->gen == 2) && tiling != I915_TILING_NONE)
832 height_alignment = 16;
833 else if (tiling == I915_TILING_X
834 || (IS_915(bufmgr_gem->pci_device)
835 && tiling == I915_TILING_Y))
836 height_alignment = 8;
837 else if (tiling == I915_TILING_Y)
838 height_alignment = 32;
839 aligned_y = ALIGN(y, height_alignment);
842 stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, tiling_mode);
843 size = stride * aligned_y;
844 size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
845 } while (*tiling_mode != tiling);
848 if (tiling == I915_TILING_NONE)
851 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags,
856 * Returns a drm_intel_bo wrapping the given buffer object handle.
858 * This can be used when one application needs to pass a buffer object
861 drm_public drm_intel_bo *
862 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
866 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
867 drm_intel_bo_gem *bo_gem;
869 struct drm_gem_open open_arg;
870 struct drm_i915_gem_get_tiling get_tiling;
873 /* At the moment most applications only have a few named bo.
874 * For instance, in a DRI client only the render buffers passed
875 * between X and the client are named. And since X returns the
876 * alternating names for the front/back buffer a linear search
877 * provides a sufficiently fast match.
879 for (list = bufmgr_gem->named.next;
880 list != &bufmgr_gem->named;
882 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, list, name_list);
883 if (bo_gem->global_name == handle) {
884 drm_intel_gem_bo_reference(&bo_gem->bo);
890 open_arg.name = handle;
891 ret = drmIoctl(bufmgr_gem->fd,
895 DBG("Couldn't reference %s handle 0x%08x: %s\n",
896 name, handle, strerror(errno));
899 /* Now see if someone has used a prime handle to get this
900 * object from the kernel before by looking through the list
901 * again for a matching gem_handle
903 for (list = bufmgr_gem->named.next;
904 list != &bufmgr_gem->named;
906 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, list, name_list);
907 if (bo_gem->gem_handle == open_arg.handle) {
908 drm_intel_gem_bo_reference(&bo_gem->bo);
913 bo_gem = calloc(1, sizeof(*bo_gem));
917 bo_gem->bo.size = open_arg.size;
918 bo_gem->bo.offset = 0;
919 bo_gem->bo.offset64 = 0;
920 bo_gem->bo.virtual = NULL;
921 bo_gem->bo.bufmgr = bufmgr;
923 atomic_set(&bo_gem->refcount, 1);
924 bo_gem->validate_index = -1;
925 bo_gem->gem_handle = open_arg.handle;
926 bo_gem->bo.handle = open_arg.handle;
927 bo_gem->global_name = handle;
928 bo_gem->reusable = false;
930 VG_CLEAR(get_tiling);
931 get_tiling.handle = bo_gem->gem_handle;
932 ret = drmIoctl(bufmgr_gem->fd,
933 DRM_IOCTL_I915_GEM_GET_TILING,
936 drm_intel_gem_bo_unreference(&bo_gem->bo);
939 bo_gem->tiling_mode = get_tiling.tiling_mode;
940 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
941 /* XXX stride is unknown */
942 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
944 DRMINITLISTHEAD(&bo_gem->vma_list);
945 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
946 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
952 drm_intel_gem_bo_free(drm_intel_bo *bo)
954 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
955 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
956 struct drm_gem_close close;
959 DRMLISTDEL(&bo_gem->vma_list);
960 if (bo_gem->mem_virtual) {
961 VG(VALGRIND_FREELIKE_BLOCK(bo_gem->mem_virtual, 0));
962 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
963 bufmgr_gem->vma_count--;
965 if (bo_gem->gtt_virtual) {
966 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
967 bufmgr_gem->vma_count--;
970 /* Close this object */
972 close.handle = bo_gem->gem_handle;
973 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
975 DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
976 bo_gem->gem_handle, bo_gem->name, strerror(errno));
978 free(bo_gem->aub_annotations);
983 drm_intel_gem_bo_mark_mmaps_incoherent(drm_intel_bo *bo)
986 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
988 if (bo_gem->mem_virtual)
989 VALGRIND_MAKE_MEM_NOACCESS(bo_gem->mem_virtual, bo->size);
991 if (bo_gem->gtt_virtual)
992 VALGRIND_MAKE_MEM_NOACCESS(bo_gem->gtt_virtual, bo->size);
996 /** Frees all cached buffers significantly older than @time. */
998 drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time)
1002 if (bufmgr_gem->time == time)
1005 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
1006 struct drm_intel_gem_bo_bucket *bucket =
1007 &bufmgr_gem->cache_bucket[i];
1009 while (!DRMLISTEMPTY(&bucket->head)) {
1010 drm_intel_bo_gem *bo_gem;
1012 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1013 bucket->head.next, head);
1014 if (time - bo_gem->free_time <= 1)
1017 DRMLISTDEL(&bo_gem->head);
1019 drm_intel_gem_bo_free(&bo_gem->bo);
1023 bufmgr_gem->time = time;
1026 static void drm_intel_gem_bo_purge_vma_cache(drm_intel_bufmgr_gem *bufmgr_gem)
1030 DBG("%s: cached=%d, open=%d, limit=%d\n", __FUNCTION__,
1031 bufmgr_gem->vma_count, bufmgr_gem->vma_open, bufmgr_gem->vma_max);
1033 if (bufmgr_gem->vma_max < 0)
1036 /* We may need to evict a few entries in order to create new mmaps */
1037 limit = bufmgr_gem->vma_max - 2*bufmgr_gem->vma_open;
1041 while (bufmgr_gem->vma_count > limit) {
1042 drm_intel_bo_gem *bo_gem;
1044 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1045 bufmgr_gem->vma_cache.next,
1047 assert(bo_gem->map_count == 0);
1048 DRMLISTDELINIT(&bo_gem->vma_list);
1050 if (bo_gem->mem_virtual) {
1051 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
1052 bo_gem->mem_virtual = NULL;
1053 bufmgr_gem->vma_count--;
1055 if (bo_gem->gtt_virtual) {
1056 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
1057 bo_gem->gtt_virtual = NULL;
1058 bufmgr_gem->vma_count--;
1063 static void drm_intel_gem_bo_close_vma(drm_intel_bufmgr_gem *bufmgr_gem,
1064 drm_intel_bo_gem *bo_gem)
1066 bufmgr_gem->vma_open--;
1067 DRMLISTADDTAIL(&bo_gem->vma_list, &bufmgr_gem->vma_cache);
1068 if (bo_gem->mem_virtual)
1069 bufmgr_gem->vma_count++;
1070 if (bo_gem->gtt_virtual)
1071 bufmgr_gem->vma_count++;
1072 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
1075 static void drm_intel_gem_bo_open_vma(drm_intel_bufmgr_gem *bufmgr_gem,
1076 drm_intel_bo_gem *bo_gem)
1078 bufmgr_gem->vma_open++;
1079 DRMLISTDEL(&bo_gem->vma_list);
1080 if (bo_gem->mem_virtual)
1081 bufmgr_gem->vma_count--;
1082 if (bo_gem->gtt_virtual)
1083 bufmgr_gem->vma_count--;
1084 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
1088 drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
1090 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1091 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1092 struct drm_intel_gem_bo_bucket *bucket;
1095 /* Unreference all the target buffers */
1096 for (i = 0; i < bo_gem->reloc_count; i++) {
1097 if (bo_gem->reloc_target_info[i].bo != bo) {
1098 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
1099 reloc_target_info[i].bo,
1103 bo_gem->reloc_count = 0;
1104 bo_gem->used_as_reloc_target = false;
1106 DBG("bo_unreference final: %d (%s)\n",
1107 bo_gem->gem_handle, bo_gem->name);
1109 /* release memory associated with this object */
1110 if (bo_gem->reloc_target_info) {
1111 free(bo_gem->reloc_target_info);
1112 bo_gem->reloc_target_info = NULL;
1114 if (bo_gem->relocs) {
1115 free(bo_gem->relocs);
1116 bo_gem->relocs = NULL;
1119 /* Clear any left-over mappings */
1120 if (bo_gem->map_count) {
1121 DBG("bo freed with non-zero map-count %d\n", bo_gem->map_count);
1122 bo_gem->map_count = 0;
1123 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1124 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1127 DRMLISTDEL(&bo_gem->name_list);
1129 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
1130 /* Put the buffer into our internal cache for reuse if we can. */
1131 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
1132 drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem,
1133 I915_MADV_DONTNEED)) {
1134 bo_gem->free_time = time;
1136 bo_gem->name = NULL;
1137 bo_gem->validate_index = -1;
1139 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
1141 drm_intel_gem_bo_free(bo);
1145 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
1148 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1150 assert(atomic_read(&bo_gem->refcount) > 0);
1151 if (atomic_dec_and_test(&bo_gem->refcount))
1152 drm_intel_gem_bo_unreference_final(bo, time);
1155 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
1157 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1159 assert(atomic_read(&bo_gem->refcount) > 0);
1161 if (atomic_add_unless(&bo_gem->refcount, -1, 1)) {
1162 drm_intel_bufmgr_gem *bufmgr_gem =
1163 (drm_intel_bufmgr_gem *) bo->bufmgr;
1164 struct timespec time;
1166 clock_gettime(CLOCK_MONOTONIC, &time);
1168 pthread_mutex_lock(&bufmgr_gem->lock);
1170 if (atomic_dec_and_test(&bo_gem->refcount)) {
1171 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
1172 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time.tv_sec);
1175 pthread_mutex_unlock(&bufmgr_gem->lock);
1179 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
1181 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1182 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1183 struct drm_i915_gem_set_domain set_domain;
1186 pthread_mutex_lock(&bufmgr_gem->lock);
1188 if (bo_gem->map_count++ == 0)
1189 drm_intel_gem_bo_open_vma(bufmgr_gem, bo_gem);
1191 if (!bo_gem->mem_virtual) {
1192 struct drm_i915_gem_mmap mmap_arg;
1194 DBG("bo_map: %d (%s), map_count=%d\n",
1195 bo_gem->gem_handle, bo_gem->name, bo_gem->map_count);
1198 mmap_arg.handle = bo_gem->gem_handle;
1199 mmap_arg.offset = 0;
1200 mmap_arg.size = bo->size;
1201 ret = drmIoctl(bufmgr_gem->fd,
1202 DRM_IOCTL_I915_GEM_MMAP,
1206 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1207 __FILE__, __LINE__, bo_gem->gem_handle,
1208 bo_gem->name, strerror(errno));
1209 if (--bo_gem->map_count == 0)
1210 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1211 pthread_mutex_unlock(&bufmgr_gem->lock);
1214 VG(VALGRIND_MALLOCLIKE_BLOCK(mmap_arg.addr_ptr, mmap_arg.size, 0, 1));
1215 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
1217 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1218 bo_gem->mem_virtual);
1219 bo->virtual = bo_gem->mem_virtual;
1221 VG_CLEAR(set_domain);
1222 set_domain.handle = bo_gem->gem_handle;
1223 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
1225 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
1227 set_domain.write_domain = 0;
1228 ret = drmIoctl(bufmgr_gem->fd,
1229 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1232 DBG("%s:%d: Error setting to CPU domain %d: %s\n",
1233 __FILE__, __LINE__, bo_gem->gem_handle,
1238 bo_gem->mapped_cpu_write = true;
1240 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1241 VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->mem_virtual, bo->size));
1242 pthread_mutex_unlock(&bufmgr_gem->lock);
1248 map_gtt(drm_intel_bo *bo)
1250 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1251 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1254 if (bo_gem->map_count++ == 0)
1255 drm_intel_gem_bo_open_vma(bufmgr_gem, bo_gem);
1257 /* Get a mapping of the buffer if we haven't before. */
1258 if (bo_gem->gtt_virtual == NULL) {
1259 struct drm_i915_gem_mmap_gtt mmap_arg;
1261 DBG("bo_map_gtt: mmap %d (%s), map_count=%d\n",
1262 bo_gem->gem_handle, bo_gem->name, bo_gem->map_count);
1265 mmap_arg.handle = bo_gem->gem_handle;
1267 /* Get the fake offset back... */
1268 ret = drmIoctl(bufmgr_gem->fd,
1269 DRM_IOCTL_I915_GEM_MMAP_GTT,
1273 DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n",
1275 bo_gem->gem_handle, bo_gem->name,
1277 if (--bo_gem->map_count == 0)
1278 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1283 bo_gem->gtt_virtual = mmap(0, bo->size, PROT_READ | PROT_WRITE,
1284 MAP_SHARED, bufmgr_gem->fd,
1286 if (bo_gem->gtt_virtual == MAP_FAILED) {
1287 bo_gem->gtt_virtual = NULL;
1289 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1291 bo_gem->gem_handle, bo_gem->name,
1293 if (--bo_gem->map_count == 0)
1294 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1299 bo->virtual = bo_gem->gtt_virtual;
1301 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1302 bo_gem->gtt_virtual);
1308 drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
1310 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1311 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1312 struct drm_i915_gem_set_domain set_domain;
1315 pthread_mutex_lock(&bufmgr_gem->lock);
1319 pthread_mutex_unlock(&bufmgr_gem->lock);
1323 /* Now move it to the GTT domain so that the GPU and CPU
1324 * caches are flushed and the GPU isn't actively using the
1327 * The pagefault handler does this domain change for us when
1328 * it has unbound the BO from the GTT, but it's up to us to
1329 * tell it when we're about to use things if we had done
1330 * rendering and it still happens to be bound to the GTT.
1332 VG_CLEAR(set_domain);
1333 set_domain.handle = bo_gem->gem_handle;
1334 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1335 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
1336 ret = drmIoctl(bufmgr_gem->fd,
1337 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1340 DBG("%s:%d: Error setting domain %d: %s\n",
1341 __FILE__, __LINE__, bo_gem->gem_handle,
1345 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1346 VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->gtt_virtual, bo->size));
1347 pthread_mutex_unlock(&bufmgr_gem->lock);
1353 * Performs a mapping of the buffer object like the normal GTT
1354 * mapping, but avoids waiting for the GPU to be done reading from or
1355 * rendering to the buffer.
1357 * This is used in the implementation of GL_ARB_map_buffer_range: The
1358 * user asks to create a buffer, then does a mapping, fills some
1359 * space, runs a drawing command, then asks to map it again without
1360 * synchronizing because it guarantees that it won't write over the
1361 * data that the GPU is busy using (or, more specifically, that if it
1362 * does write over the data, it acknowledges that rendering is
1367 drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo)
1369 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1370 #ifdef HAVE_VALGRIND
1371 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1375 /* If the CPU cache isn't coherent with the GTT, then use a
1376 * regular synchronized mapping. The problem is that we don't
1377 * track where the buffer was last used on the CPU side in
1378 * terms of drm_intel_bo_map vs drm_intel_gem_bo_map_gtt, so
1379 * we would potentially corrupt the buffer even when the user
1380 * does reasonable things.
1382 if (!bufmgr_gem->has_llc)
1383 return drm_intel_gem_bo_map_gtt(bo);
1385 pthread_mutex_lock(&bufmgr_gem->lock);
1389 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1390 VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->gtt_virtual, bo->size));
1393 pthread_mutex_unlock(&bufmgr_gem->lock);
1398 static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
1400 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1401 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1407 pthread_mutex_lock(&bufmgr_gem->lock);
1409 if (bo_gem->map_count <= 0) {
1410 DBG("attempted to unmap an unmapped bo\n");
1411 pthread_mutex_unlock(&bufmgr_gem->lock);
1412 /* Preserve the old behaviour of just treating this as a
1413 * no-op rather than reporting the error.
1418 if (bo_gem->mapped_cpu_write) {
1419 struct drm_i915_gem_sw_finish sw_finish;
1421 /* Cause a flush to happen if the buffer's pinned for
1422 * scanout, so the results show up in a timely manner.
1423 * Unlike GTT set domains, this only does work if the
1424 * buffer should be scanout-related.
1426 VG_CLEAR(sw_finish);
1427 sw_finish.handle = bo_gem->gem_handle;
1428 ret = drmIoctl(bufmgr_gem->fd,
1429 DRM_IOCTL_I915_GEM_SW_FINISH,
1431 ret = ret == -1 ? -errno : 0;
1433 bo_gem->mapped_cpu_write = false;
1436 /* We need to unmap after every innovation as we cannot track
1437 * an open vma for every bo as that will exhaasut the system
1438 * limits and cause later failures.
1440 if (--bo_gem->map_count == 0) {
1441 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1442 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1445 pthread_mutex_unlock(&bufmgr_gem->lock);
1451 drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
1453 return drm_intel_gem_bo_unmap(bo);
1457 drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset,
1458 unsigned long size, const void *data)
1460 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1461 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1462 struct drm_i915_gem_pwrite pwrite;
1466 pwrite.handle = bo_gem->gem_handle;
1467 pwrite.offset = offset;
1469 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
1470 ret = drmIoctl(bufmgr_gem->fd,
1471 DRM_IOCTL_I915_GEM_PWRITE,
1475 DBG("%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
1476 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1477 (int)size, strerror(errno));
1484 drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
1486 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1487 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
1490 VG_CLEAR(get_pipe_from_crtc_id);
1491 get_pipe_from_crtc_id.crtc_id = crtc_id;
1492 ret = drmIoctl(bufmgr_gem->fd,
1493 DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
1494 &get_pipe_from_crtc_id);
1496 /* We return -1 here to signal that we don't
1497 * know which pipe is associated with this crtc.
1498 * This lets the caller know that this information
1499 * isn't available; using the wrong pipe for
1500 * vblank waiting can cause the chipset to lock up
1505 return get_pipe_from_crtc_id.pipe;
1509 drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
1510 unsigned long size, void *data)
1512 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1513 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1514 struct drm_i915_gem_pread pread;
1518 pread.handle = bo_gem->gem_handle;
1519 pread.offset = offset;
1521 pread.data_ptr = (uint64_t) (uintptr_t) data;
1522 ret = drmIoctl(bufmgr_gem->fd,
1523 DRM_IOCTL_I915_GEM_PREAD,
1527 DBG("%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
1528 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1529 (int)size, strerror(errno));
1535 /** Waits for all GPU rendering with the object to have completed. */
1537 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
1539 drm_intel_gem_bo_start_gtt_access(bo, 1);
1543 * Waits on a BO for the given amount of time.
1545 * @bo: buffer object to wait for
1546 * @timeout_ns: amount of time to wait in nanoseconds.
1547 * If value is less than 0, an infinite wait will occur.
1549 * Returns 0 if the wait was successful ie. the last batch referencing the
1550 * object has completed within the allotted time. Otherwise some negative return
1551 * value describes the error. Of particular interest is -ETIME when the wait has
1552 * failed to yield the desired result.
1554 * Similar to drm_intel_gem_bo_wait_rendering except a timeout parameter allows
1555 * the operation to give up after a certain amount of time. Another subtle
1556 * difference is the internal locking semantics are different (this variant does
1557 * not hold the lock for the duration of the wait). This makes the wait subject
1558 * to a larger userspace race window.
1560 * The implementation shall wait until the object is no longer actively
1561 * referenced within a batch buffer at the time of the call. The wait will
1562 * not guarantee that the buffer is re-issued via another thread, or an flinked
1563 * handle. Userspace must make sure this race does not occur if such precision
1567 drm_intel_gem_bo_wait(drm_intel_bo *bo, int64_t timeout_ns)
1569 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1570 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1571 struct drm_i915_gem_wait wait;
1574 if (!bufmgr_gem->has_wait_timeout) {
1575 DBG("%s:%d: Timed wait is not supported. Falling back to "
1576 "infinite wait\n", __FILE__, __LINE__);
1578 drm_intel_gem_bo_wait_rendering(bo);
1581 return drm_intel_gem_bo_busy(bo) ? -ETIME : 0;
1585 wait.bo_handle = bo_gem->gem_handle;
1586 wait.timeout_ns = timeout_ns;
1588 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_WAIT, &wait);
1596 * Sets the object to the GTT read and possibly write domain, used by the X
1597 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
1599 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
1600 * can do tiled pixmaps this way.
1603 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
1605 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1606 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1607 struct drm_i915_gem_set_domain set_domain;
1610 VG_CLEAR(set_domain);
1611 set_domain.handle = bo_gem->gem_handle;
1612 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1613 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
1614 ret = drmIoctl(bufmgr_gem->fd,
1615 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1618 DBG("%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
1619 __FILE__, __LINE__, bo_gem->gem_handle,
1620 set_domain.read_domains, set_domain.write_domain,
1626 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
1628 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1631 free(bufmgr_gem->exec2_objects);
1632 free(bufmgr_gem->exec_objects);
1633 free(bufmgr_gem->exec_bos);
1634 free(bufmgr_gem->aub_filename);
1636 pthread_mutex_destroy(&bufmgr_gem->lock);
1638 /* Free any cached buffer objects we were going to reuse */
1639 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
1640 struct drm_intel_gem_bo_bucket *bucket =
1641 &bufmgr_gem->cache_bucket[i];
1642 drm_intel_bo_gem *bo_gem;
1644 while (!DRMLISTEMPTY(&bucket->head)) {
1645 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1646 bucket->head.next, head);
1647 DRMLISTDEL(&bo_gem->head);
1649 drm_intel_gem_bo_free(&bo_gem->bo);
1657 * Adds the target buffer to the validation list and adds the relocation
1658 * to the reloc_buffer's relocation list.
1660 * The relocation entry at the given offset must already contain the
1661 * precomputed relocation value, because the kernel will optimize out
1662 * the relocation entry write when the buffer hasn't moved from the
1663 * last known offset in target_bo.
1666 do_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1667 drm_intel_bo *target_bo, uint32_t target_offset,
1668 uint32_t read_domains, uint32_t write_domain,
1671 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1672 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1673 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1674 bool fenced_command;
1676 if (bo_gem->has_error)
1679 if (target_bo_gem->has_error) {
1680 bo_gem->has_error = true;
1684 /* We never use HW fences for rendering on 965+ */
1685 if (bufmgr_gem->gen >= 4)
1688 fenced_command = need_fence;
1689 if (target_bo_gem->tiling_mode == I915_TILING_NONE)
1692 /* Create a new relocation list if needed */
1693 if (bo_gem->relocs == NULL && drm_intel_setup_reloc_list(bo))
1696 /* Check overflow */
1697 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
1700 assert(offset <= bo->size - 4);
1701 assert((write_domain & (write_domain - 1)) == 0);
1703 /* Make sure that we're not adding a reloc to something whose size has
1704 * already been accounted for.
1706 assert(!bo_gem->used_as_reloc_target);
1707 if (target_bo_gem != bo_gem) {
1708 target_bo_gem->used_as_reloc_target = true;
1709 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
1711 /* An object needing a fence is a tiled buffer, so it won't have
1712 * relocs to other buffers.
1715 target_bo_gem->reloc_tree_fences = 1;
1716 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
1718 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
1719 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
1720 bo_gem->relocs[bo_gem->reloc_count].target_handle =
1721 target_bo_gem->gem_handle;
1722 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
1723 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
1724 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset64;
1726 bo_gem->reloc_target_info[bo_gem->reloc_count].bo = target_bo;
1727 if (target_bo != bo)
1728 drm_intel_gem_bo_reference(target_bo);
1730 bo_gem->reloc_target_info[bo_gem->reloc_count].flags =
1731 DRM_INTEL_RELOC_FENCE;
1733 bo_gem->reloc_target_info[bo_gem->reloc_count].flags = 0;
1735 bo_gem->reloc_count++;
1741 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1742 drm_intel_bo *target_bo, uint32_t target_offset,
1743 uint32_t read_domains, uint32_t write_domain)
1745 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1747 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1748 read_domains, write_domain,
1749 !bufmgr_gem->fenced_relocs);
1753 drm_intel_gem_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
1754 drm_intel_bo *target_bo,
1755 uint32_t target_offset,
1756 uint32_t read_domains, uint32_t write_domain)
1758 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1759 read_domains, write_domain, true);
1763 drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo)
1765 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1767 return bo_gem->reloc_count;
1771 * Removes existing relocation entries in the BO after "start".
1773 * This allows a user to avoid a two-step process for state setup with
1774 * counting up all the buffer objects and doing a
1775 * drm_intel_bufmgr_check_aperture_space() before emitting any of the
1776 * relocations for the state setup. Instead, save the state of the
1777 * batchbuffer including drm_intel_gem_get_reloc_count(), emit all the
1778 * state, and then check if it still fits in the aperture.
1780 * Any further drm_intel_bufmgr_check_aperture_space() queries
1781 * involving this buffer in the tree are undefined after this call.
1784 drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start)
1786 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1787 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1789 struct timespec time;
1791 clock_gettime(CLOCK_MONOTONIC, &time);
1793 assert(bo_gem->reloc_count >= start);
1795 /* Unreference the cleared target buffers */
1796 pthread_mutex_lock(&bufmgr_gem->lock);
1798 for (i = start; i < bo_gem->reloc_count; i++) {
1799 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) bo_gem->reloc_target_info[i].bo;
1800 if (&target_bo_gem->bo != bo) {
1801 bo_gem->reloc_tree_fences -= target_bo_gem->reloc_tree_fences;
1802 drm_intel_gem_bo_unreference_locked_timed(&target_bo_gem->bo,
1806 bo_gem->reloc_count = start;
1808 pthread_mutex_unlock(&bufmgr_gem->lock);
1813 * Walk the tree of relocations rooted at BO and accumulate the list of
1814 * validations to be performed and update the relocation buffers with
1815 * index values into the validation list.
1818 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
1820 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1823 if (bo_gem->relocs == NULL)
1826 for (i = 0; i < bo_gem->reloc_count; i++) {
1827 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1829 if (target_bo == bo)
1832 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1834 /* Continue walking the tree depth-first. */
1835 drm_intel_gem_bo_process_reloc(target_bo);
1837 /* Add the target to the validate list */
1838 drm_intel_add_validate_buffer(target_bo);
1843 drm_intel_gem_bo_process_reloc2(drm_intel_bo *bo)
1845 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1848 if (bo_gem->relocs == NULL)
1851 for (i = 0; i < bo_gem->reloc_count; i++) {
1852 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1855 if (target_bo == bo)
1858 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1860 /* Continue walking the tree depth-first. */
1861 drm_intel_gem_bo_process_reloc2(target_bo);
1863 need_fence = (bo_gem->reloc_target_info[i].flags &
1864 DRM_INTEL_RELOC_FENCE);
1866 /* Add the target to the validate list */
1867 drm_intel_add_validate_buffer2(target_bo, need_fence);
1873 drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem)
1877 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1878 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1879 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1881 /* Update the buffer offset */
1882 if (bufmgr_gem->exec_objects[i].offset != bo->offset64) {
1883 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1884 bo_gem->gem_handle, bo_gem->name, bo->offset64,
1885 (unsigned long long)bufmgr_gem->exec_objects[i].
1887 bo->offset64 = bufmgr_gem->exec_objects[i].offset;
1888 bo->offset = bufmgr_gem->exec_objects[i].offset;
1894 drm_intel_update_buffer_offsets2 (drm_intel_bufmgr_gem *bufmgr_gem)
1898 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1899 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1900 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1902 /* Update the buffer offset */
1903 if (bufmgr_gem->exec2_objects[i].offset != bo->offset64) {
1904 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1905 bo_gem->gem_handle, bo_gem->name, bo->offset64,
1906 (unsigned long long)bufmgr_gem->exec2_objects[i].offset);
1907 bo->offset64 = bufmgr_gem->exec2_objects[i].offset;
1908 bo->offset = bufmgr_gem->exec2_objects[i].offset;
1914 aub_out(drm_intel_bufmgr_gem *bufmgr_gem, uint32_t data)
1916 fwrite(&data, 1, 4, bufmgr_gem->aub_file);
1920 aub_out_data(drm_intel_bufmgr_gem *bufmgr_gem, void *data, size_t size)
1922 fwrite(data, 1, size, bufmgr_gem->aub_file);
1926 aub_write_bo_data(drm_intel_bo *bo, uint32_t offset, uint32_t size)
1928 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1929 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1933 data = malloc(bo->size);
1934 drm_intel_bo_get_subdata(bo, offset, size, data);
1936 /* Easy mode: write out bo with no relocations */
1937 if (!bo_gem->reloc_count) {
1938 aub_out_data(bufmgr_gem, data, size);
1943 /* Otherwise, handle the relocations while writing. */
1944 for (i = 0; i < size / 4; i++) {
1946 for (r = 0; r < bo_gem->reloc_count; r++) {
1947 struct drm_i915_gem_relocation_entry *reloc;
1948 drm_intel_reloc_target *info;
1950 reloc = &bo_gem->relocs[r];
1951 info = &bo_gem->reloc_target_info[r];
1953 if (reloc->offset == offset + i * 4) {
1954 drm_intel_bo_gem *target_gem;
1957 target_gem = (drm_intel_bo_gem *)info->bo;
1960 val += target_gem->aub_offset;
1962 aub_out(bufmgr_gem, val);
1967 if (r == bo_gem->reloc_count) {
1968 /* no relocation, just the data */
1969 aub_out(bufmgr_gem, data[i]);
1977 aub_bo_get_address(drm_intel_bo *bo)
1979 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1980 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1982 /* Give the object a graphics address in the AUB file. We
1983 * don't just use the GEM object address because we do AUB
1984 * dumping before execution -- we want to successfully log
1985 * when the hardware might hang, and we might even want to aub
1986 * capture for a driver trying to execute on a different
1987 * generation of hardware by disabling the actual kernel exec
1990 bo_gem->aub_offset = bufmgr_gem->aub_offset;
1991 bufmgr_gem->aub_offset += bo->size;
1992 /* XXX: Handle aperture overflow. */
1993 assert(bufmgr_gem->aub_offset < 256 * 1024 * 1024);
1997 aub_write_trace_block(drm_intel_bo *bo, uint32_t type, uint32_t subtype,
1998 uint32_t offset, uint32_t size)
2000 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2001 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2004 CMD_AUB_TRACE_HEADER_BLOCK |
2005 ((bufmgr_gem->gen >= 8 ? 6 : 5) - 2));
2007 AUB_TRACE_MEMTYPE_GTT | type | AUB_TRACE_OP_DATA_WRITE);
2008 aub_out(bufmgr_gem, subtype);
2009 aub_out(bufmgr_gem, bo_gem->aub_offset + offset);
2010 aub_out(bufmgr_gem, size);
2011 if (bufmgr_gem->gen >= 8)
2012 aub_out(bufmgr_gem, 0);
2013 aub_write_bo_data(bo, offset, size);
2017 * Break up large objects into multiple writes. Otherwise a 128kb VBO
2018 * would overflow the 16 bits of size field in the packet header and
2019 * everything goes badly after that.
2022 aub_write_large_trace_block(drm_intel_bo *bo, uint32_t type, uint32_t subtype,
2023 uint32_t offset, uint32_t size)
2025 uint32_t block_size;
2026 uint32_t sub_offset;
2028 for (sub_offset = 0; sub_offset < size; sub_offset += block_size) {
2029 block_size = size - sub_offset;
2031 if (block_size > 8 * 4096)
2032 block_size = 8 * 4096;
2034 aub_write_trace_block(bo, type, subtype, offset + sub_offset,
2040 aub_write_bo(drm_intel_bo *bo)
2042 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2043 uint32_t offset = 0;
2046 aub_bo_get_address(bo);
2048 /* Write out each annotated section separately. */
2049 for (i = 0; i < bo_gem->aub_annotation_count; ++i) {
2050 drm_intel_aub_annotation *annotation =
2051 &bo_gem->aub_annotations[i];
2052 uint32_t ending_offset = annotation->ending_offset;
2053 if (ending_offset > bo->size)
2054 ending_offset = bo->size;
2055 if (ending_offset > offset) {
2056 aub_write_large_trace_block(bo, annotation->type,
2057 annotation->subtype,
2059 ending_offset - offset);
2060 offset = ending_offset;
2064 /* Write out any remaining unannotated data */
2065 if (offset < bo->size) {
2066 aub_write_large_trace_block(bo, AUB_TRACE_TYPE_NOTYPE, 0,
2067 offset, bo->size - offset);
2072 * Make a ringbuffer on fly and dump it
2075 aub_build_dump_ringbuffer(drm_intel_bufmgr_gem *bufmgr_gem,
2076 uint32_t batch_buffer, int ring_flag)
2078 uint32_t ringbuffer[4096];
2079 int ring = AUB_TRACE_TYPE_RING_PRB0; /* The default ring */
2082 if (ring_flag == I915_EXEC_BSD)
2083 ring = AUB_TRACE_TYPE_RING_PRB1;
2084 else if (ring_flag == I915_EXEC_BLT)
2085 ring = AUB_TRACE_TYPE_RING_PRB2;
2087 /* Make a ring buffer to execute our batchbuffer. */
2088 memset(ringbuffer, 0, sizeof(ringbuffer));
2089 if (bufmgr_gem->gen >= 8) {
2090 ringbuffer[ring_count++] = AUB_MI_BATCH_BUFFER_START | (3 - 2);
2091 ringbuffer[ring_count++] = batch_buffer;
2092 ringbuffer[ring_count++] = 0;
2094 ringbuffer[ring_count++] = AUB_MI_BATCH_BUFFER_START;
2095 ringbuffer[ring_count++] = batch_buffer;
2098 /* Write out the ring. This appears to trigger execution of
2099 * the ring in the simulator.
2102 CMD_AUB_TRACE_HEADER_BLOCK |
2103 ((bufmgr_gem->gen >= 8 ? 6 : 5) - 2));
2105 AUB_TRACE_MEMTYPE_GTT | ring | AUB_TRACE_OP_COMMAND_WRITE);
2106 aub_out(bufmgr_gem, 0); /* general/surface subtype */
2107 aub_out(bufmgr_gem, bufmgr_gem->aub_offset);
2108 aub_out(bufmgr_gem, ring_count * 4);
2109 if (bufmgr_gem->gen >= 8)
2110 aub_out(bufmgr_gem, 0);
2112 /* FIXME: Need some flush operations here? */
2113 aub_out_data(bufmgr_gem, ringbuffer, ring_count * 4);
2115 /* Update offset pointer */
2116 bufmgr_gem->aub_offset += 4096;
2120 drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo,
2121 int x1, int y1, int width, int height,
2122 enum aub_dump_bmp_format format,
2123 int pitch, int offset)
2125 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2126 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
2130 case AUB_DUMP_BMP_FORMAT_8BIT:
2133 case AUB_DUMP_BMP_FORMAT_ARGB_4444:
2136 case AUB_DUMP_BMP_FORMAT_ARGB_0888:
2137 case AUB_DUMP_BMP_FORMAT_ARGB_8888:
2141 printf("Unknown AUB dump format %d\n", format);
2145 if (!bufmgr_gem->aub_file)
2148 aub_out(bufmgr_gem, CMD_AUB_DUMP_BMP | 4);
2149 aub_out(bufmgr_gem, (y1 << 16) | x1);
2154 aub_out(bufmgr_gem, (height << 16) | width);
2155 aub_out(bufmgr_gem, bo_gem->aub_offset + offset);
2157 ((bo_gem->tiling_mode != I915_TILING_NONE) ? (1 << 2) : 0) |
2158 ((bo_gem->tiling_mode == I915_TILING_Y) ? (1 << 3) : 0));
2162 aub_exec(drm_intel_bo *bo, int ring_flag, int used)
2164 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2165 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2167 bool batch_buffer_needs_annotations;
2169 if (!bufmgr_gem->aub_file)
2172 /* If batch buffer is not annotated, annotate it the best we
2175 batch_buffer_needs_annotations = bo_gem->aub_annotation_count == 0;
2176 if (batch_buffer_needs_annotations) {
2177 drm_intel_aub_annotation annotations[2] = {
2178 { AUB_TRACE_TYPE_BATCH, 0, used },
2179 { AUB_TRACE_TYPE_NOTYPE, 0, bo->size }
2181 drm_intel_bufmgr_gem_set_aub_annotations(bo, annotations, 2);
2184 /* Write out all buffers to AUB memory */
2185 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2186 aub_write_bo(bufmgr_gem->exec_bos[i]);
2189 /* Remove any annotations we added */
2190 if (batch_buffer_needs_annotations)
2191 drm_intel_bufmgr_gem_set_aub_annotations(bo, NULL, 0);
2193 /* Dump ring buffer */
2194 aub_build_dump_ringbuffer(bufmgr_gem, bo_gem->aub_offset, ring_flag);
2196 fflush(bufmgr_gem->aub_file);
2199 * One frame has been dumped. So reset the aub_offset for the next frame.
2201 * FIXME: Can we do this?
2203 bufmgr_gem->aub_offset = 0x10000;
2207 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
2208 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
2210 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2211 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2212 struct drm_i915_gem_execbuffer execbuf;
2215 if (bo_gem->has_error)
2218 pthread_mutex_lock(&bufmgr_gem->lock);
2219 /* Update indices and set up the validate list. */
2220 drm_intel_gem_bo_process_reloc(bo);
2222 /* Add the batch buffer to the validation list. There are no
2223 * relocations pointing to it.
2225 drm_intel_add_validate_buffer(bo);
2228 execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects;
2229 execbuf.buffer_count = bufmgr_gem->exec_count;
2230 execbuf.batch_start_offset = 0;
2231 execbuf.batch_len = used;
2232 execbuf.cliprects_ptr = (uintptr_t) cliprects;
2233 execbuf.num_cliprects = num_cliprects;
2237 ret = drmIoctl(bufmgr_gem->fd,
2238 DRM_IOCTL_I915_GEM_EXECBUFFER,
2242 if (errno == ENOSPC) {
2243 DBG("Execbuffer fails to pin. "
2244 "Estimate: %u. Actual: %u. Available: %u\n",
2245 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
2248 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
2251 (unsigned int)bufmgr_gem->gtt_size);
2254 drm_intel_update_buffer_offsets(bufmgr_gem);
2256 if (bufmgr_gem->bufmgr.debug)
2257 drm_intel_gem_dump_validation_list(bufmgr_gem);
2259 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2260 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
2261 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2263 bo_gem->idle = false;
2265 /* Disconnect the buffer from the validate list */
2266 bo_gem->validate_index = -1;
2267 bufmgr_gem->exec_bos[i] = NULL;
2269 bufmgr_gem->exec_count = 0;
2270 pthread_mutex_unlock(&bufmgr_gem->lock);
2276 do_exec2(drm_intel_bo *bo, int used, drm_intel_context *ctx,
2277 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
2280 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
2281 struct drm_i915_gem_execbuffer2 execbuf;
2285 switch (flags & 0x7) {
2289 if (!bufmgr_gem->has_blt)
2293 if (!bufmgr_gem->has_bsd)
2296 case I915_EXEC_VEBOX:
2297 if (!bufmgr_gem->has_vebox)
2300 case I915_EXEC_RENDER:
2301 case I915_EXEC_DEFAULT:
2305 pthread_mutex_lock(&bufmgr_gem->lock);
2306 /* Update indices and set up the validate list. */
2307 drm_intel_gem_bo_process_reloc2(bo);
2309 /* Add the batch buffer to the validation list. There are no relocations
2312 drm_intel_add_validate_buffer2(bo, 0);
2315 execbuf.buffers_ptr = (uintptr_t)bufmgr_gem->exec2_objects;
2316 execbuf.buffer_count = bufmgr_gem->exec_count;
2317 execbuf.batch_start_offset = 0;
2318 execbuf.batch_len = used;
2319 execbuf.cliprects_ptr = (uintptr_t)cliprects;
2320 execbuf.num_cliprects = num_cliprects;
2323 execbuf.flags = flags;
2325 i915_execbuffer2_set_context_id(execbuf, 0);
2327 i915_execbuffer2_set_context_id(execbuf, ctx->ctx_id);
2330 aub_exec(bo, flags, used);
2332 if (bufmgr_gem->no_exec)
2333 goto skip_execution;
2335 ret = drmIoctl(bufmgr_gem->fd,
2336 DRM_IOCTL_I915_GEM_EXECBUFFER2,
2340 if (ret == -ENOSPC) {
2341 DBG("Execbuffer fails to pin. "
2342 "Estimate: %u. Actual: %u. Available: %u\n",
2343 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
2344 bufmgr_gem->exec_count),
2345 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
2346 bufmgr_gem->exec_count),
2347 (unsigned int) bufmgr_gem->gtt_size);
2350 drm_intel_update_buffer_offsets2(bufmgr_gem);
2353 if (bufmgr_gem->bufmgr.debug)
2354 drm_intel_gem_dump_validation_list(bufmgr_gem);
2356 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2357 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
2358 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
2360 bo_gem->idle = false;
2362 /* Disconnect the buffer from the validate list */
2363 bo_gem->validate_index = -1;
2364 bufmgr_gem->exec_bos[i] = NULL;
2366 bufmgr_gem->exec_count = 0;
2367 pthread_mutex_unlock(&bufmgr_gem->lock);
2373 drm_intel_gem_bo_exec2(drm_intel_bo *bo, int used,
2374 drm_clip_rect_t *cliprects, int num_cliprects,
2377 return do_exec2(bo, used, NULL, cliprects, num_cliprects, DR4,
2382 drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used,
2383 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
2386 return do_exec2(bo, used, NULL, cliprects, num_cliprects, DR4,
2391 drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx,
2392 int used, unsigned int flags)
2394 return do_exec2(bo, used, ctx, NULL, 0, 0, flags);
2398 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
2400 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2401 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2402 struct drm_i915_gem_pin pin;
2406 pin.handle = bo_gem->gem_handle;
2407 pin.alignment = alignment;
2409 ret = drmIoctl(bufmgr_gem->fd,
2410 DRM_IOCTL_I915_GEM_PIN,
2415 bo->offset64 = pin.offset;
2416 bo->offset = pin.offset;
2421 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
2423 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2424 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2425 struct drm_i915_gem_unpin unpin;
2429 unpin.handle = bo_gem->gem_handle;
2431 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
2439 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
2440 uint32_t tiling_mode,
2443 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2444 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2445 struct drm_i915_gem_set_tiling set_tiling;
2448 if (bo_gem->global_name == 0 &&
2449 tiling_mode == bo_gem->tiling_mode &&
2450 stride == bo_gem->stride)
2453 memset(&set_tiling, 0, sizeof(set_tiling));
2455 /* set_tiling is slightly broken and overwrites the
2456 * input on the error path, so we have to open code
2459 set_tiling.handle = bo_gem->gem_handle;
2460 set_tiling.tiling_mode = tiling_mode;
2461 set_tiling.stride = stride;
2463 ret = ioctl(bufmgr_gem->fd,
2464 DRM_IOCTL_I915_GEM_SET_TILING,
2466 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
2470 bo_gem->tiling_mode = set_tiling.tiling_mode;
2471 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
2472 bo_gem->stride = set_tiling.stride;
2477 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
2480 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2481 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2484 /* Linear buffers have no stride. By ensuring that we only ever use
2485 * stride 0 with linear buffers, we simplify our code.
2487 if (*tiling_mode == I915_TILING_NONE)
2490 ret = drm_intel_gem_bo_set_tiling_internal(bo, *tiling_mode, stride);
2492 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
2494 *tiling_mode = bo_gem->tiling_mode;
2499 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
2500 uint32_t * swizzle_mode)
2502 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2504 *tiling_mode = bo_gem->tiling_mode;
2505 *swizzle_mode = bo_gem->swizzle_mode;
2509 drm_public drm_intel_bo *
2510 drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr, int prime_fd, int size)
2512 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
2515 drm_intel_bo_gem *bo_gem;
2516 struct drm_i915_gem_get_tiling get_tiling;
2517 drmMMListHead *list;
2519 ret = drmPrimeFDToHandle(bufmgr_gem->fd, prime_fd, &handle);
2522 * See if the kernel has already returned this buffer to us. Just as
2523 * for named buffers, we must not create two bo's pointing at the same
2526 for (list = bufmgr_gem->named.next;
2527 list != &bufmgr_gem->named;
2528 list = list->next) {
2529 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, list, name_list);
2530 if (bo_gem->gem_handle == handle) {
2531 drm_intel_gem_bo_reference(&bo_gem->bo);
2537 fprintf(stderr,"ret is %d %d\n", ret, errno);
2541 bo_gem = calloc(1, sizeof(*bo_gem));
2545 /* Determine size of bo. The fd-to-handle ioctl really should
2546 * return the size, but it doesn't. If we have kernel 3.12 or
2547 * later, we can lseek on the prime fd to get the size. Older
2548 * kernels will just fail, in which case we fall back to the
2549 * provided (estimated or guess size). */
2550 ret = lseek(prime_fd, 0, SEEK_END);
2552 bo_gem->bo.size = ret;
2554 bo_gem->bo.size = size;
2556 bo_gem->bo.handle = handle;
2557 bo_gem->bo.bufmgr = bufmgr;
2559 bo_gem->gem_handle = handle;
2561 atomic_set(&bo_gem->refcount, 1);
2563 bo_gem->name = "prime";
2564 bo_gem->validate_index = -1;
2565 bo_gem->reloc_tree_fences = 0;
2566 bo_gem->used_as_reloc_target = false;
2567 bo_gem->has_error = false;
2568 bo_gem->reusable = false;
2570 DRMINITLISTHEAD(&bo_gem->vma_list);
2571 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
2573 VG_CLEAR(get_tiling);
2574 get_tiling.handle = bo_gem->gem_handle;
2575 ret = drmIoctl(bufmgr_gem->fd,
2576 DRM_IOCTL_I915_GEM_GET_TILING,
2579 drm_intel_gem_bo_unreference(&bo_gem->bo);
2582 bo_gem->tiling_mode = get_tiling.tiling_mode;
2583 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
2584 /* XXX stride is unknown */
2585 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
2591 drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int *prime_fd)
2593 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2594 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2596 if (DRMLISTEMPTY(&bo_gem->name_list))
2597 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
2599 if (drmPrimeHandleToFD(bufmgr_gem->fd, bo_gem->gem_handle,
2600 DRM_CLOEXEC, prime_fd) != 0)
2603 bo_gem->reusable = false;
2609 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name)
2611 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2612 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2615 if (!bo_gem->global_name) {
2616 struct drm_gem_flink flink;
2619 flink.handle = bo_gem->gem_handle;
2621 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink);
2625 bo_gem->global_name = flink.name;
2626 bo_gem->reusable = false;
2628 if (DRMLISTEMPTY(&bo_gem->name_list))
2629 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
2632 *name = bo_gem->global_name;
2637 * Enables unlimited caching of buffer objects for reuse.
2639 * This is potentially very memory expensive, as the cache at each bucket
2640 * size is only bounded by how many buffers of that size we've managed to have
2641 * in flight at once.
2644 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
2646 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
2648 bufmgr_gem->bo_reuse = true;
2652 * Enable use of fenced reloc type.
2654 * New code should enable this to avoid unnecessary fence register
2655 * allocation. If this option is not enabled, all relocs will have fence
2656 * register allocated.
2659 drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr)
2661 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2663 if (bufmgr_gem->bufmgr.bo_exec == drm_intel_gem_bo_exec2)
2664 bufmgr_gem->fenced_relocs = true;
2668 * Return the additional aperture space required by the tree of buffer objects
2672 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
2674 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2678 if (bo == NULL || bo_gem->included_in_check_aperture)
2682 bo_gem->included_in_check_aperture = true;
2684 for (i = 0; i < bo_gem->reloc_count; i++)
2686 drm_intel_gem_bo_get_aperture_space(bo_gem->
2687 reloc_target_info[i].bo);
2693 * Count the number of buffers in this list that need a fence reg
2695 * If the count is greater than the number of available regs, we'll have
2696 * to ask the caller to resubmit a batch with fewer tiled buffers.
2698 * This function over-counts if the same buffer is used multiple times.
2701 drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count)
2704 unsigned int total = 0;
2706 for (i = 0; i < count; i++) {
2707 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
2712 total += bo_gem->reloc_tree_fences;
2718 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
2719 * for the next drm_intel_bufmgr_check_aperture_space() call.
2722 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
2724 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2727 if (bo == NULL || !bo_gem->included_in_check_aperture)
2730 bo_gem->included_in_check_aperture = false;
2732 for (i = 0; i < bo_gem->reloc_count; i++)
2733 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->
2734 reloc_target_info[i].bo);
2738 * Return a conservative estimate for the amount of aperture required
2739 * for a collection of buffers. This may double-count some buffers.
2742 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
2745 unsigned int total = 0;
2747 for (i = 0; i < count; i++) {
2748 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
2750 total += bo_gem->reloc_tree_size;
2756 * Return the amount of aperture needed for a collection of buffers.
2757 * This avoids double counting any buffers, at the cost of looking
2758 * at every buffer in the set.
2761 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
2764 unsigned int total = 0;
2766 for (i = 0; i < count; i++) {
2767 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
2768 /* For the first buffer object in the array, we get an
2769 * accurate count back for its reloc_tree size (since nothing
2770 * had been flagged as being counted yet). We can save that
2771 * value out as a more conservative reloc_tree_size that
2772 * avoids double-counting target buffers. Since the first
2773 * buffer happens to usually be the batch buffer in our
2774 * callers, this can pull us back from doing the tree
2775 * walk on every new batch emit.
2778 drm_intel_bo_gem *bo_gem =
2779 (drm_intel_bo_gem *) bo_array[i];
2780 bo_gem->reloc_tree_size = total;
2784 for (i = 0; i < count; i++)
2785 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
2790 * Return -1 if the batchbuffer should be flushed before attempting to
2791 * emit rendering referencing the buffers pointed to by bo_array.
2793 * This is required because if we try to emit a batchbuffer with relocations
2794 * to a tree of buffers that won't simultaneously fit in the aperture,
2795 * the rendering will return an error at a point where the software is not
2796 * prepared to recover from it.
2798 * However, we also want to emit the batchbuffer significantly before we reach
2799 * the limit, as a series of batchbuffers each of which references buffers
2800 * covering almost all of the aperture means that at each emit we end up
2801 * waiting to evict a buffer from the last rendering, and we get synchronous
2802 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
2803 * get better parallelism.
2806 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
2808 drm_intel_bufmgr_gem *bufmgr_gem =
2809 (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr;
2810 unsigned int total = 0;
2811 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
2814 /* Check for fence reg constraints if necessary */
2815 if (bufmgr_gem->available_fences) {
2816 total_fences = drm_intel_gem_total_fences(bo_array, count);
2817 if (total_fences > bufmgr_gem->available_fences)
2821 total = drm_intel_gem_estimate_batch_space(bo_array, count);
2823 if (total > threshold)
2824 total = drm_intel_gem_compute_batch_space(bo_array, count);
2826 if (total > threshold) {
2827 DBG("check_space: overflowed available aperture, "
2829 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
2832 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024,
2833 (int)bufmgr_gem->gtt_size / 1024);
2839 * Disable buffer reuse for objects which are shared with the kernel
2840 * as scanout buffers
2843 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
2845 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2847 bo_gem->reusable = false;
2852 drm_intel_gem_bo_is_reusable(drm_intel_bo *bo)
2854 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2856 return bo_gem->reusable;
2860 _drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2862 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2865 for (i = 0; i < bo_gem->reloc_count; i++) {
2866 if (bo_gem->reloc_target_info[i].bo == target_bo)
2868 if (bo == bo_gem->reloc_target_info[i].bo)
2870 if (_drm_intel_gem_bo_references(bo_gem->reloc_target_info[i].bo,
2878 /** Return true if target_bo is referenced by bo's relocation tree. */
2880 drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2882 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
2884 if (bo == NULL || target_bo == NULL)
2886 if (target_bo_gem->used_as_reloc_target)
2887 return _drm_intel_gem_bo_references(bo, target_bo);
2892 add_bucket(drm_intel_bufmgr_gem *bufmgr_gem, int size)
2894 unsigned int i = bufmgr_gem->num_buckets;
2896 assert(i < ARRAY_SIZE(bufmgr_gem->cache_bucket));
2898 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
2899 bufmgr_gem->cache_bucket[i].size = size;
2900 bufmgr_gem->num_buckets++;
2904 init_cache_buckets(drm_intel_bufmgr_gem *bufmgr_gem)
2906 unsigned long size, cache_max_size = 64 * 1024 * 1024;
2908 /* OK, so power of two buckets was too wasteful of memory.
2909 * Give 3 other sizes between each power of two, to hopefully
2910 * cover things accurately enough. (The alternative is
2911 * probably to just go for exact matching of sizes, and assume
2912 * that for things like composited window resize the tiled
2913 * width/height alignment and rounding of sizes to pages will
2914 * get us useful cache hit rates anyway)
2916 add_bucket(bufmgr_gem, 4096);
2917 add_bucket(bufmgr_gem, 4096 * 2);
2918 add_bucket(bufmgr_gem, 4096 * 3);
2920 /* Initialize the linked lists for BO reuse cache. */
2921 for (size = 4 * 4096; size <= cache_max_size; size *= 2) {
2922 add_bucket(bufmgr_gem, size);
2924 add_bucket(bufmgr_gem, size + size * 1 / 4);
2925 add_bucket(bufmgr_gem, size + size * 2 / 4);
2926 add_bucket(bufmgr_gem, size + size * 3 / 4);
2931 drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr, int limit)
2933 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2935 bufmgr_gem->vma_max = limit;
2937 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
2941 * Get the PCI ID for the device. This can be overridden by setting the
2942 * INTEL_DEVID_OVERRIDE environment variable to the desired ID.
2945 get_pci_device_id(drm_intel_bufmgr_gem *bufmgr_gem)
2947 char *devid_override;
2950 drm_i915_getparam_t gp;
2952 if (geteuid() == getuid()) {
2953 devid_override = getenv("INTEL_DEVID_OVERRIDE");
2954 if (devid_override) {
2955 bufmgr_gem->no_exec = true;
2956 return strtod(devid_override, NULL);
2962 gp.param = I915_PARAM_CHIPSET_ID;
2964 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2966 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
2967 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
2973 drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr)
2975 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2977 return bufmgr_gem->pci_device;
2981 * Sets the AUB filename.
2983 * This function has to be called before drm_intel_bufmgr_gem_set_aub_dump()
2984 * for it to have any effect.
2987 drm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr,
2988 const char *filename)
2990 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2992 free(bufmgr_gem->aub_filename);
2994 bufmgr_gem->aub_filename = strdup(filename);
2998 * Sets up AUB dumping.
3000 * This is a trace file format that can be used with the simulator.
3001 * Packets are emitted in a format somewhat like GPU command packets.
3002 * You can set up a GTT and upload your objects into the referenced
3003 * space, then send off batchbuffers and get BMPs out the other end.
3006 drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable)
3008 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3009 int entry = 0x200003;
3011 int gtt_size = 0x10000;
3012 const char *filename;
3015 if (bufmgr_gem->aub_file) {
3016 fclose(bufmgr_gem->aub_file);
3017 bufmgr_gem->aub_file = NULL;
3022 if (geteuid() != getuid())
3025 if (bufmgr_gem->aub_filename)
3026 filename = bufmgr_gem->aub_filename;
3028 filename = "intel.aub";
3029 bufmgr_gem->aub_file = fopen(filename, "w+");
3030 if (!bufmgr_gem->aub_file)
3033 /* Start allocating objects from just after the GTT. */
3034 bufmgr_gem->aub_offset = gtt_size;
3036 /* Start with a (required) version packet. */
3037 aub_out(bufmgr_gem, CMD_AUB_HEADER | (13 - 2));
3039 (4 << AUB_HEADER_MAJOR_SHIFT) |
3040 (0 << AUB_HEADER_MINOR_SHIFT));
3041 for (i = 0; i < 8; i++) {
3042 aub_out(bufmgr_gem, 0); /* app name */
3044 aub_out(bufmgr_gem, 0); /* timestamp */
3045 aub_out(bufmgr_gem, 0); /* timestamp */
3046 aub_out(bufmgr_gem, 0); /* comment len */
3048 /* Set up the GTT. The max we can handle is 256M */
3049 aub_out(bufmgr_gem, CMD_AUB_TRACE_HEADER_BLOCK | ((bufmgr_gem->gen >= 8 ? 6 : 5) - 2));
3050 aub_out(bufmgr_gem, AUB_TRACE_MEMTYPE_NONLOCAL | 0 | AUB_TRACE_OP_DATA_WRITE);
3051 aub_out(bufmgr_gem, 0); /* subtype */
3052 aub_out(bufmgr_gem, 0); /* offset */
3053 aub_out(bufmgr_gem, gtt_size); /* size */
3054 if (bufmgr_gem->gen >= 8)
3055 aub_out(bufmgr_gem, 0);
3056 for (i = 0x000; i < gtt_size; i += 4, entry += 0x1000) {
3057 aub_out(bufmgr_gem, entry);
3061 drm_public drm_intel_context *
3062 drm_intel_gem_context_create(drm_intel_bufmgr *bufmgr)
3064 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3065 struct drm_i915_gem_context_create create;
3066 drm_intel_context *context = NULL;
3069 context = calloc(1, sizeof(*context));
3074 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE, &create);
3076 DBG("DRM_IOCTL_I915_GEM_CONTEXT_CREATE failed: %s\n",
3082 context->ctx_id = create.ctx_id;
3083 context->bufmgr = bufmgr;
3089 drm_intel_gem_context_destroy(drm_intel_context *ctx)
3091 drm_intel_bufmgr_gem *bufmgr_gem;
3092 struct drm_i915_gem_context_destroy destroy;
3100 bufmgr_gem = (drm_intel_bufmgr_gem *)ctx->bufmgr;
3101 destroy.ctx_id = ctx->ctx_id;
3102 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_CONTEXT_DESTROY,
3105 fprintf(stderr, "DRM_IOCTL_I915_GEM_CONTEXT_DESTROY failed: %s\n",
3112 drm_intel_get_reset_stats(drm_intel_context *ctx,
3113 uint32_t *reset_count,
3117 drm_intel_bufmgr_gem *bufmgr_gem;
3118 struct drm_i915_reset_stats stats;
3124 memset(&stats, 0, sizeof(stats));
3126 bufmgr_gem = (drm_intel_bufmgr_gem *)ctx->bufmgr;
3127 stats.ctx_id = ctx->ctx_id;
3128 ret = drmIoctl(bufmgr_gem->fd,
3129 DRM_IOCTL_I915_GET_RESET_STATS,
3132 if (reset_count != NULL)
3133 *reset_count = stats.reset_count;
3136 *active = stats.batch_active;
3138 if (pending != NULL)
3139 *pending = stats.batch_pending;
3146 drm_intel_reg_read(drm_intel_bufmgr *bufmgr,
3150 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3151 struct drm_i915_reg_read reg_read;
3155 reg_read.offset = offset;
3157 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_REG_READ, ®_read);
3159 *result = reg_read.val;
3165 * Annotate the given bo for use in aub dumping.
3167 * \param annotations is an array of drm_intel_aub_annotation objects
3168 * describing the type of data in various sections of the bo. Each
3169 * element of the array specifies the type and subtype of a section of
3170 * the bo, and the past-the-end offset of that section. The elements
3171 * of \c annotations must be sorted so that ending_offset is
3174 * \param count is the number of elements in the \c annotations array.
3175 * If \c count is zero, then \c annotations will not be dereferenced.
3177 * Annotations are copied into a private data structure, so caller may
3178 * re-use the memory pointed to by \c annotations after the call
3181 * Annotations are stored for the lifetime of the bo; to reset to the
3182 * default state (no annotations), call this function with a \c count
3186 drm_intel_bufmgr_gem_set_aub_annotations(drm_intel_bo *bo,
3187 drm_intel_aub_annotation *annotations,
3190 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
3191 unsigned size = sizeof(*annotations) * count;
3192 drm_intel_aub_annotation *new_annotations =
3193 count > 0 ? realloc(bo_gem->aub_annotations, size) : NULL;
3194 if (new_annotations == NULL) {
3195 free(bo_gem->aub_annotations);
3196 bo_gem->aub_annotations = NULL;
3197 bo_gem->aub_annotation_count = 0;
3200 memcpy(new_annotations, annotations, size);
3201 bo_gem->aub_annotations = new_annotations;
3202 bo_gem->aub_annotation_count = count;
3205 static pthread_mutex_t bufmgr_list_mutex = PTHREAD_MUTEX_INITIALIZER;
3206 static drmMMListHead bufmgr_list = { &bufmgr_list, &bufmgr_list };
3208 static drm_intel_bufmgr_gem *
3209 drm_intel_bufmgr_gem_find(int fd)
3211 drm_intel_bufmgr_gem *bufmgr_gem;
3213 DRMLISTFOREACHENTRY(bufmgr_gem, &bufmgr_list, managers) {
3214 if (bufmgr_gem->fd == fd) {
3215 atomic_inc(&bufmgr_gem->refcount);
3224 drm_intel_bufmgr_gem_unref(drm_intel_bufmgr *bufmgr)
3226 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3228 if (atomic_add_unless(&bufmgr_gem->refcount, -1, 1)) {
3229 pthread_mutex_lock(&bufmgr_list_mutex);
3231 if (atomic_dec_and_test(&bufmgr_gem->refcount)) {
3232 DRMLISTDEL(&bufmgr_gem->managers);
3233 drm_intel_bufmgr_gem_destroy(bufmgr);
3236 pthread_mutex_unlock(&bufmgr_list_mutex);
3241 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
3242 * and manage map buffer objections.
3244 * \param fd File descriptor of the opened DRM device.
3246 drm_public drm_intel_bufmgr *
3247 drm_intel_bufmgr_gem_init(int fd, int batch_size)
3249 drm_intel_bufmgr_gem *bufmgr_gem;
3250 struct drm_i915_gem_get_aperture aperture;
3251 drm_i915_getparam_t gp;
3255 pthread_mutex_lock(&bufmgr_list_mutex);
3257 bufmgr_gem = drm_intel_bufmgr_gem_find(fd);
3261 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
3262 if (bufmgr_gem == NULL)
3265 bufmgr_gem->fd = fd;
3266 atomic_set(&bufmgr_gem->refcount, 1);
3268 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
3274 ret = drmIoctl(bufmgr_gem->fd,
3275 DRM_IOCTL_I915_GEM_GET_APERTURE,
3279 bufmgr_gem->gtt_size = aperture.aper_available_size;
3281 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
3283 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
3284 fprintf(stderr, "Assuming %dkB available aperture size.\n"
3285 "May lead to reduced performance or incorrect "
3287 (int)bufmgr_gem->gtt_size / 1024);
3290 bufmgr_gem->pci_device = get_pci_device_id(bufmgr_gem);
3292 if (IS_GEN2(bufmgr_gem->pci_device))
3293 bufmgr_gem->gen = 2;
3294 else if (IS_GEN3(bufmgr_gem->pci_device))
3295 bufmgr_gem->gen = 3;
3296 else if (IS_GEN4(bufmgr_gem->pci_device))
3297 bufmgr_gem->gen = 4;
3298 else if (IS_GEN5(bufmgr_gem->pci_device))
3299 bufmgr_gem->gen = 5;
3300 else if (IS_GEN6(bufmgr_gem->pci_device))
3301 bufmgr_gem->gen = 6;
3302 else if (IS_GEN7(bufmgr_gem->pci_device))
3303 bufmgr_gem->gen = 7;
3304 else if (IS_GEN8(bufmgr_gem->pci_device))
3305 bufmgr_gem->gen = 8;
3312 if (IS_GEN3(bufmgr_gem->pci_device) &&
3313 bufmgr_gem->gtt_size > 256*1024*1024) {
3314 /* The unmappable part of gtt on gen 3 (i.e. above 256MB) can't
3315 * be used for tiled blits. To simplify the accounting, just
3316 * substract the unmappable part (fixed to 256MB on all known
3317 * gen3 devices) if the kernel advertises it. */
3318 bufmgr_gem->gtt_size -= 256*1024*1024;
3324 gp.param = I915_PARAM_HAS_EXECBUF2;
3325 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3329 gp.param = I915_PARAM_HAS_BSD;
3330 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3331 bufmgr_gem->has_bsd = ret == 0;
3333 gp.param = I915_PARAM_HAS_BLT;
3334 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3335 bufmgr_gem->has_blt = ret == 0;
3337 gp.param = I915_PARAM_HAS_RELAXED_FENCING;
3338 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3339 bufmgr_gem->has_relaxed_fencing = ret == 0;
3341 gp.param = I915_PARAM_HAS_WAIT_TIMEOUT;
3342 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3343 bufmgr_gem->has_wait_timeout = ret == 0;
3345 gp.param = I915_PARAM_HAS_LLC;
3346 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3348 /* Kernel does not supports HAS_LLC query, fallback to GPU
3349 * generation detection and assume that we have LLC on GEN6/7
3351 bufmgr_gem->has_llc = (IS_GEN6(bufmgr_gem->pci_device) |
3352 IS_GEN7(bufmgr_gem->pci_device));
3354 bufmgr_gem->has_llc = *gp.value;
3356 gp.param = I915_PARAM_HAS_VEBOX;
3357 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3358 bufmgr_gem->has_vebox = (ret == 0) & (*gp.value > 0);
3360 if (bufmgr_gem->gen < 4) {
3361 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
3362 gp.value = &bufmgr_gem->available_fences;
3363 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3365 fprintf(stderr, "get fences failed: %d [%d]\n", ret,
3367 fprintf(stderr, "param: %d, val: %d\n", gp.param,
3369 bufmgr_gem->available_fences = 0;
3371 /* XXX The kernel reports the total number of fences,
3372 * including any that may be pinned.
3374 * We presume that there will be at least one pinned
3375 * fence for the scanout buffer, but there may be more
3376 * than one scanout and the user may be manually
3377 * pinning buffers. Let's move to execbuffer2 and
3378 * thereby forget the insanity of using fences...
3380 bufmgr_gem->available_fences -= 2;
3381 if (bufmgr_gem->available_fences < 0)
3382 bufmgr_gem->available_fences = 0;
3386 /* Let's go with one relocation per every 2 dwords (but round down a bit
3387 * since a power of two will mean an extra page allocation for the reloc
3390 * Every 4 was too few for the blender benchmark.
3392 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
3394 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
3395 bufmgr_gem->bufmgr.bo_alloc_for_render =
3396 drm_intel_gem_bo_alloc_for_render;
3397 bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled;
3398 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
3399 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
3400 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
3401 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
3402 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
3403 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
3404 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
3405 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
3406 bufmgr_gem->bufmgr.bo_emit_reloc_fence = drm_intel_gem_bo_emit_reloc_fence;
3407 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
3408 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
3409 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
3410 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
3411 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
3412 /* Use the new one if available */
3414 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec2;
3415 bufmgr_gem->bufmgr.bo_mrb_exec = drm_intel_gem_bo_mrb_exec2;
3417 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
3418 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
3419 bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise;
3420 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_unref;
3421 bufmgr_gem->bufmgr.debug = 0;
3422 bufmgr_gem->bufmgr.check_aperture_space =
3423 drm_intel_gem_check_aperture_space;
3424 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
3425 bufmgr_gem->bufmgr.bo_is_reusable = drm_intel_gem_bo_is_reusable;
3426 bufmgr_gem->bufmgr.get_pipe_from_crtc_id =
3427 drm_intel_gem_get_pipe_from_crtc_id;
3428 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
3430 DRMINITLISTHEAD(&bufmgr_gem->named);
3431 init_cache_buckets(bufmgr_gem);
3433 DRMINITLISTHEAD(&bufmgr_gem->vma_cache);
3434 bufmgr_gem->vma_max = -1; /* unlimited by default */
3436 DRMLISTADD(&bufmgr_gem->managers, &bufmgr_list);
3439 pthread_mutex_unlock(&bufmgr_list_mutex);
3441 return bufmgr_gem != NULL ? &bufmgr_gem->bufmgr : NULL;