3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #ifndef _INTEL_CHIPSET_H
29 #define _INTEL_CHIPSET_H
31 #define PCI_CHIP_I810 0x7121
32 #define PCI_CHIP_I810_DC100 0x7123
33 #define PCI_CHIP_I810_E 0x7125
34 #define PCI_CHIP_I815 0x1132
36 #define PCI_CHIP_I830_M 0x3577
37 #define PCI_CHIP_845_G 0x2562
38 #define PCI_CHIP_I855_GM 0x3582
39 #define PCI_CHIP_I865_G 0x2572
41 #define PCI_CHIP_I915_G 0x2582
42 #define PCI_CHIP_E7221_G 0x258A
43 #define PCI_CHIP_I915_GM 0x2592
44 #define PCI_CHIP_I945_G 0x2772
45 #define PCI_CHIP_I945_GM 0x27A2
46 #define PCI_CHIP_I945_GME 0x27AE
48 #define PCI_CHIP_Q35_G 0x29B2
49 #define PCI_CHIP_G33_G 0x29C2
50 #define PCI_CHIP_Q33_G 0x29D2
52 #define PCI_CHIP_IGD_GM 0xA011
53 #define PCI_CHIP_IGD_G 0xA001
55 #define IS_IGDGM(devid) ((devid) == PCI_CHIP_IGD_GM)
56 #define IS_IGDG(devid) ((devid) == PCI_CHIP_IGD_G)
57 #define IS_IGD(devid) (IS_IGDG(devid) || IS_IGDGM(devid))
59 #define PCI_CHIP_I965_G 0x29A2
60 #define PCI_CHIP_I965_Q 0x2992
61 #define PCI_CHIP_I965_G_1 0x2982
62 #define PCI_CHIP_I946_GZ 0x2972
63 #define PCI_CHIP_I965_GM 0x2A02
64 #define PCI_CHIP_I965_GME 0x2A12
66 #define PCI_CHIP_GM45_GM 0x2A42
68 #define PCI_CHIP_IGD_E_G 0x2E02
69 #define PCI_CHIP_Q45_G 0x2E12
70 #define PCI_CHIP_G45_G 0x2E22
71 #define PCI_CHIP_G41_G 0x2E32
73 #define PCI_CHIP_ILD_G 0x0042
74 #define PCI_CHIP_ILM_G 0x0046
76 #define PCI_CHIP_SANDYBRIDGE_GT1 0x0102 /* desktop */
77 #define PCI_CHIP_SANDYBRIDGE_GT2 0x0112
78 #define PCI_CHIP_SANDYBRIDGE_GT2_PLUS 0x0122
79 #define PCI_CHIP_SANDYBRIDGE_M_GT1 0x0106 /* mobile */
80 #define PCI_CHIP_SANDYBRIDGE_M_GT2 0x0116
81 #define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126
82 #define PCI_CHIP_SANDYBRIDGE_S 0x010A /* server */
84 #define PCI_CHIP_IVYBRIDGE_GT1 0x0152 /* desktop */
85 #define PCI_CHIP_IVYBRIDGE_GT2 0x0162
86 #define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 /* mobile */
87 #define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166
88 #define PCI_CHIP_IVYBRIDGE_S 0x015a /* server */
89 #define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a /* server */
91 #define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */
92 #define PCI_CHIP_HASWELL_GT2 0x0412
93 #define PCI_CHIP_HASWELL_GT3 0x0422
94 #define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */
95 #define PCI_CHIP_HASWELL_M_GT2 0x0416
96 #define PCI_CHIP_HASWELL_M_GT3 0x0426
97 #define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */
98 #define PCI_CHIP_HASWELL_S_GT2 0x041A
99 #define PCI_CHIP_HASWELL_S_GT3 0x042A
100 #define PCI_CHIP_HASWELL_B_GT1 0x040B /* Reserved */
101 #define PCI_CHIP_HASWELL_B_GT2 0x041B
102 #define PCI_CHIP_HASWELL_B_GT3 0x042B
103 #define PCI_CHIP_HASWELL_E_GT1 0x040E /* Reserved */
104 #define PCI_CHIP_HASWELL_E_GT2 0x041E
105 #define PCI_CHIP_HASWELL_E_GT3 0x042E
106 #define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */
107 #define PCI_CHIP_HASWELL_SDV_GT2 0x0C12
108 #define PCI_CHIP_HASWELL_SDV_GT3 0x0C22
109 #define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */
110 #define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16
111 #define PCI_CHIP_HASWELL_SDV_M_GT3 0x0C26
112 #define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */
113 #define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A
114 #define PCI_CHIP_HASWELL_SDV_S_GT3 0x0C2A
115 #define PCI_CHIP_HASWELL_SDV_B_GT1 0x0C0B /* Reserved */
116 #define PCI_CHIP_HASWELL_SDV_B_GT2 0x0C1B
117 #define PCI_CHIP_HASWELL_SDV_B_GT3 0x0C2B
118 #define PCI_CHIP_HASWELL_SDV_E_GT1 0x0C0E /* Reserved */
119 #define PCI_CHIP_HASWELL_SDV_E_GT2 0x0C1E
120 #define PCI_CHIP_HASWELL_SDV_E_GT3 0x0C2E
121 #define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */
122 #define PCI_CHIP_HASWELL_ULT_GT2 0x0A12
123 #define PCI_CHIP_HASWELL_ULT_GT3 0x0A22
124 #define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */
125 #define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16
126 #define PCI_CHIP_HASWELL_ULT_M_GT3 0x0A26
127 #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */
128 #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
129 #define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A
130 #define PCI_CHIP_HASWELL_ULT_B_GT1 0x0A0B /* Reserved */
131 #define PCI_CHIP_HASWELL_ULT_B_GT2 0x0A1B
132 #define PCI_CHIP_HASWELL_ULT_B_GT3 0x0A2B
133 #define PCI_CHIP_HASWELL_ULT_E_GT1 0x0A0E /* Reserved */
134 #define PCI_CHIP_HASWELL_ULT_E_GT2 0x0A1E
135 #define PCI_CHIP_HASWELL_ULT_E_GT3 0x0A2E
136 #define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */
137 #define PCI_CHIP_HASWELL_CRW_GT2 0x0D12
138 #define PCI_CHIP_HASWELL_CRW_GT3 0x0D22
139 #define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 /* Mobile */
140 #define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16
141 #define PCI_CHIP_HASWELL_CRW_M_GT3 0x0D26
142 #define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */
143 #define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A
144 #define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A
145 #define PCI_CHIP_HASWELL_CRW_B_GT1 0x0D0B /* Reserved */
146 #define PCI_CHIP_HASWELL_CRW_B_GT2 0x0D1B
147 #define PCI_CHIP_HASWELL_CRW_B_GT3 0x0D2B
148 #define PCI_CHIP_HASWELL_CRW_E_GT1 0x0D0E /* Reserved */
149 #define PCI_CHIP_HASWELL_CRW_E_GT2 0x0D1E
150 #define PCI_CHIP_HASWELL_CRW_E_GT3 0x0D2E
151 #define BDW_SPARE 0x2
153 #define BDW_SERVER 0xa
155 #define BDW_WORKSTATION 0xd
158 #define PCI_CHIP_VALLEYVIEW_PO 0x0f30 /* VLV PO board */
159 #define PCI_CHIP_VALLEYVIEW_1 0x0f31
160 #define PCI_CHIP_VALLEYVIEW_2 0x0f32
161 #define PCI_CHIP_VALLEYVIEW_3 0x0f33
163 #define PCI_CHIP_CHERRYVIEW_0 0x22b0
164 #define PCI_CHIP_CHERRYVIEW_1 0x22b1
165 #define PCI_CHIP_CHERRYVIEW_2 0x22b2
166 #define PCI_CHIP_CHERRYVIEW_3 0x22b3
168 #define PCI_CHIP_SKYLAKE_DT_GT1 0x1902
169 #define PCI_CHIP_SKYLAKE_ULT_GT1 0x1906
170 #define PCI_CHIP_SKYLAKE_SRV_GT1 0x190A /* Reserved */
171 #define PCI_CHIP_SKYLAKE_H_GT1 0x190B
172 #define PCI_CHIP_SKYLAKE_ULX_GT1 0x190E /* Reserved */
173 #define PCI_CHIP_SKYLAKE_DT_GT2 0x1912
174 #define PCI_CHIP_SKYLAKE_FUSED0_GT2 0x1913 /* Reserved */
175 #define PCI_CHIP_SKYLAKE_FUSED1_GT2 0x1915 /* Reserved */
176 #define PCI_CHIP_SKYLAKE_ULT_GT2 0x1916
177 #define PCI_CHIP_SKYLAKE_FUSED2_GT2 0x1917 /* Reserved */
178 #define PCI_CHIP_SKYLAKE_SRV_GT2 0x191A /* Reserved */
179 #define PCI_CHIP_SKYLAKE_HALO_GT2 0x191B
180 #define PCI_CHIP_SKYLAKE_WKS_GT2 0x191D
181 #define PCI_CHIP_SKYLAKE_ULX_GT2 0x191E
182 #define PCI_CHIP_SKYLAKE_MOBILE_GT2 0x1921 /* Reserved */
183 #define PCI_CHIP_SKYLAKE_ULT_GT3_0 0x1923
184 #define PCI_CHIP_SKYLAKE_ULT_GT3_1 0x1926
185 #define PCI_CHIP_SKYLAKE_ULT_GT3_2 0x1927
186 #define PCI_CHIP_SKYLAKE_SRV_GT4 0x192A
187 #define PCI_CHIP_SKYLAKE_HALO_GT3 0x192B /* Reserved */
188 #define PCI_CHIP_SKYLAKE_SRV_GT3 0x192D
189 #define PCI_CHIP_SKYLAKE_DT_GT4 0x1932
190 #define PCI_CHIP_SKYLAKE_SRV_GT4X 0x193A
191 #define PCI_CHIP_SKYLAKE_H_GT4 0x193B
192 #define PCI_CHIP_SKYLAKE_WKS_GT4 0x193D
194 #define PCI_CHIP_KABYLAKE_ULT_GT2 0x5916
195 #define PCI_CHIP_KABYLAKE_ULT_GT1_5 0x5913
196 #define PCI_CHIP_KABYLAKE_ULT_GT1 0x5906
197 #define PCI_CHIP_KABYLAKE_ULT_GT3_0 0x5923
198 #define PCI_CHIP_KABYLAKE_ULT_GT3_1 0x5926
199 #define PCI_CHIP_KABYLAKE_ULT_GT3_2 0x5927
200 #define PCI_CHIP_KABYLAKE_ULT_GT2F 0x5921
201 #define PCI_CHIP_KABYLAKE_ULX_GT1_5 0x5915
202 #define PCI_CHIP_KABYLAKE_ULX_GT1 0x590E
203 #define PCI_CHIP_KABYLAKE_ULX_GT2 0x591E
204 #define PCI_CHIP_KABYLAKE_DT_GT2 0x5912
205 #define PCI_CHIP_KABYLAKE_DT_GT1_5 0x5917
206 #define PCI_CHIP_KABYLAKE_DT_GT1 0x5902
207 #define PCI_CHIP_KABYLAKE_HALO_GT2 0x591B
208 #define PCI_CHIP_KABYLAKE_HALO_GT4 0x593B
209 #define PCI_CHIP_KABYLAKE_HALO_GT1_0 0x5908
210 #define PCI_CHIP_KABYLAKE_HALO_GT1_1 0x590B
211 #define PCI_CHIP_KABYLAKE_SRV_GT2 0x591A
212 #define PCI_CHIP_KABYLAKE_SRV_GT1 0x590A
213 #define PCI_CHIP_KABYLAKE_WKS_GT2 0x591D
215 #define PCI_CHIP_BROXTON_0 0x0A84
216 #define PCI_CHIP_BROXTON_1 0x1A84
217 #define PCI_CHIP_BROXTON_2 0x5A84
218 #define PCI_CHIP_BROXTON_3 0x1A85
219 #define PCI_CHIP_BROXTON_4 0x5A85
221 #define PCI_CHIP_GLK 0x3184
222 #define PCI_CHIP_GLK_2X6 0x3185
224 #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
225 (devid) == PCI_CHIP_I915_GM || \
226 (devid) == PCI_CHIP_I945_GM || \
227 (devid) == PCI_CHIP_I945_GME || \
228 (devid) == PCI_CHIP_I965_GM || \
229 (devid) == PCI_CHIP_I965_GME || \
230 (devid) == PCI_CHIP_GM45_GM || IS_IGD(devid) || \
231 (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
232 (devid) == PCI_CHIP_IVYBRIDGE_M_GT2)
234 #define IS_G45(devid) ((devid) == PCI_CHIP_IGD_E_G || \
235 (devid) == PCI_CHIP_Q45_G || \
236 (devid) == PCI_CHIP_G45_G || \
237 (devid) == PCI_CHIP_G41_G)
238 #define IS_GM45(devid) ((devid) == PCI_CHIP_GM45_GM)
239 #define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid))
241 #define IS_ILD(devid) ((devid) == PCI_CHIP_ILD_G)
242 #define IS_ILM(devid) ((devid) == PCI_CHIP_ILM_G)
244 #define IS_915(devid) ((devid) == PCI_CHIP_I915_G || \
245 (devid) == PCI_CHIP_E7221_G || \
246 (devid) == PCI_CHIP_I915_GM)
248 #define IS_945GM(devid) ((devid) == PCI_CHIP_I945_GM || \
249 (devid) == PCI_CHIP_I945_GME)
251 #define IS_945(devid) ((devid) == PCI_CHIP_I945_G || \
252 (devid) == PCI_CHIP_I945_GM || \
253 (devid) == PCI_CHIP_I945_GME || \
256 #define IS_G33(devid) ((devid) == PCI_CHIP_G33_G || \
257 (devid) == PCI_CHIP_Q33_G || \
258 (devid) == PCI_CHIP_Q35_G || IS_IGD(devid))
260 #define IS_GEN2(devid) ((devid) == PCI_CHIP_I830_M || \
261 (devid) == PCI_CHIP_845_G || \
262 (devid) == PCI_CHIP_I855_GM || \
263 (devid) == PCI_CHIP_I865_G)
265 #define IS_GEN3(devid) (IS_945(devid) || IS_915(devid))
267 #define IS_GEN4(devid) ((devid) == PCI_CHIP_I965_G || \
268 (devid) == PCI_CHIP_I965_Q || \
269 (devid) == PCI_CHIP_I965_G_1 || \
270 (devid) == PCI_CHIP_I965_GM || \
271 (devid) == PCI_CHIP_I965_GME || \
272 (devid) == PCI_CHIP_I946_GZ || \
275 #define IS_GEN5(devid) (IS_ILD(devid) || IS_ILM(devid))
277 #define IS_GEN6(devid) ((devid) == PCI_CHIP_SANDYBRIDGE_GT1 || \
278 (devid) == PCI_CHIP_SANDYBRIDGE_GT2 || \
279 (devid) == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
280 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
281 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
282 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
283 (devid) == PCI_CHIP_SANDYBRIDGE_S)
285 #define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \
286 IS_HASWELL(devid) || \
287 IS_VALLEYVIEW(devid))
289 #define IS_IVYBRIDGE(devid) ((devid) == PCI_CHIP_IVYBRIDGE_GT1 || \
290 (devid) == PCI_CHIP_IVYBRIDGE_GT2 || \
291 (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
292 (devid) == PCI_CHIP_IVYBRIDGE_M_GT2 || \
293 (devid) == PCI_CHIP_IVYBRIDGE_S || \
294 (devid) == PCI_CHIP_IVYBRIDGE_S_GT2)
296 #define IS_VALLEYVIEW(devid) ((devid) == PCI_CHIP_VALLEYVIEW_PO || \
297 (devid) == PCI_CHIP_VALLEYVIEW_1 || \
298 (devid) == PCI_CHIP_VALLEYVIEW_2 || \
299 (devid) == PCI_CHIP_VALLEYVIEW_3)
301 #define IS_HSW_GT1(devid) ((devid) == PCI_CHIP_HASWELL_GT1 || \
302 (devid) == PCI_CHIP_HASWELL_M_GT1 || \
303 (devid) == PCI_CHIP_HASWELL_S_GT1 || \
304 (devid) == PCI_CHIP_HASWELL_B_GT1 || \
305 (devid) == PCI_CHIP_HASWELL_E_GT1 || \
306 (devid) == PCI_CHIP_HASWELL_SDV_GT1 || \
307 (devid) == PCI_CHIP_HASWELL_SDV_M_GT1 || \
308 (devid) == PCI_CHIP_HASWELL_SDV_S_GT1 || \
309 (devid) == PCI_CHIP_HASWELL_SDV_B_GT1 || \
310 (devid) == PCI_CHIP_HASWELL_SDV_E_GT1 || \
311 (devid) == PCI_CHIP_HASWELL_ULT_GT1 || \
312 (devid) == PCI_CHIP_HASWELL_ULT_M_GT1 || \
313 (devid) == PCI_CHIP_HASWELL_ULT_S_GT1 || \
314 (devid) == PCI_CHIP_HASWELL_ULT_B_GT1 || \
315 (devid) == PCI_CHIP_HASWELL_ULT_E_GT1 || \
316 (devid) == PCI_CHIP_HASWELL_CRW_GT1 || \
317 (devid) == PCI_CHIP_HASWELL_CRW_M_GT1 || \
318 (devid) == PCI_CHIP_HASWELL_CRW_S_GT1 || \
319 (devid) == PCI_CHIP_HASWELL_CRW_B_GT1 || \
320 (devid) == PCI_CHIP_HASWELL_CRW_E_GT1)
321 #define IS_HSW_GT2(devid) ((devid) == PCI_CHIP_HASWELL_GT2 || \
322 (devid) == PCI_CHIP_HASWELL_M_GT2 || \
323 (devid) == PCI_CHIP_HASWELL_S_GT2 || \
324 (devid) == PCI_CHIP_HASWELL_B_GT2 || \
325 (devid) == PCI_CHIP_HASWELL_E_GT2 || \
326 (devid) == PCI_CHIP_HASWELL_SDV_GT2 || \
327 (devid) == PCI_CHIP_HASWELL_SDV_M_GT2 || \
328 (devid) == PCI_CHIP_HASWELL_SDV_S_GT2 || \
329 (devid) == PCI_CHIP_HASWELL_SDV_B_GT2 || \
330 (devid) == PCI_CHIP_HASWELL_SDV_E_GT2 || \
331 (devid) == PCI_CHIP_HASWELL_ULT_GT2 || \
332 (devid) == PCI_CHIP_HASWELL_ULT_M_GT2 || \
333 (devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \
334 (devid) == PCI_CHIP_HASWELL_ULT_B_GT2 || \
335 (devid) == PCI_CHIP_HASWELL_ULT_E_GT2 || \
336 (devid) == PCI_CHIP_HASWELL_CRW_GT2 || \
337 (devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \
338 (devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \
339 (devid) == PCI_CHIP_HASWELL_CRW_B_GT2 || \
340 (devid) == PCI_CHIP_HASWELL_CRW_E_GT2)
341 #define IS_HSW_GT3(devid) ((devid) == PCI_CHIP_HASWELL_GT3 || \
342 (devid) == PCI_CHIP_HASWELL_M_GT3 || \
343 (devid) == PCI_CHIP_HASWELL_S_GT3 || \
344 (devid) == PCI_CHIP_HASWELL_B_GT3 || \
345 (devid) == PCI_CHIP_HASWELL_E_GT3 || \
346 (devid) == PCI_CHIP_HASWELL_SDV_GT3 || \
347 (devid) == PCI_CHIP_HASWELL_SDV_M_GT3 || \
348 (devid) == PCI_CHIP_HASWELL_SDV_S_GT3 || \
349 (devid) == PCI_CHIP_HASWELL_SDV_B_GT3 || \
350 (devid) == PCI_CHIP_HASWELL_SDV_E_GT3 || \
351 (devid) == PCI_CHIP_HASWELL_ULT_GT3 || \
352 (devid) == PCI_CHIP_HASWELL_ULT_M_GT3 || \
353 (devid) == PCI_CHIP_HASWELL_ULT_S_GT3 || \
354 (devid) == PCI_CHIP_HASWELL_ULT_B_GT3 || \
355 (devid) == PCI_CHIP_HASWELL_ULT_E_GT3 || \
356 (devid) == PCI_CHIP_HASWELL_CRW_GT3 || \
357 (devid) == PCI_CHIP_HASWELL_CRW_M_GT3 || \
358 (devid) == PCI_CHIP_HASWELL_CRW_S_GT3 || \
359 (devid) == PCI_CHIP_HASWELL_CRW_B_GT3 || \
360 (devid) == PCI_CHIP_HASWELL_CRW_E_GT3)
362 #define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \
363 IS_HSW_GT2(devid) || \
366 #define IS_BROADWELL(devid) (((devid & 0xff00) != 0x1600) ? 0 : \
367 (((devid & 0x00f0) >> 4) > 3) ? 0 : \
368 ((devid & 0x000f) == BDW_SPARE) ? 1 : \
369 ((devid & 0x000f) == BDW_ULT) ? 1 : \
370 ((devid & 0x000f) == BDW_IRIS) ? 1 : \
371 ((devid & 0x000f) == BDW_SERVER) ? 1 : \
372 ((devid & 0x000f) == BDW_WORKSTATION) ? 1 : \
373 ((devid & 0x000f) == BDW_ULX) ? 1 : 0)
375 #define IS_CHERRYVIEW(devid) ((devid) == PCI_CHIP_CHERRYVIEW_0 || \
376 (devid) == PCI_CHIP_CHERRYVIEW_1 || \
377 (devid) == PCI_CHIP_CHERRYVIEW_2 || \
378 (devid) == PCI_CHIP_CHERRYVIEW_3)
380 #define IS_GEN8(devid) (IS_BROADWELL(devid) || \
381 IS_CHERRYVIEW(devid))
383 #define IS_SKL_GT1(devid) ((devid) == PCI_CHIP_SKYLAKE_DT_GT1 || \
384 (devid) == PCI_CHIP_SKYLAKE_ULT_GT1 || \
385 (devid) == PCI_CHIP_SKYLAKE_SRV_GT1 || \
386 (devid) == PCI_CHIP_SKYLAKE_H_GT1 || \
387 (devid) == PCI_CHIP_SKYLAKE_ULX_GT1)
389 #define IS_SKL_GT2(devid) ((devid) == PCI_CHIP_SKYLAKE_DT_GT2 || \
390 (devid) == PCI_CHIP_SKYLAKE_FUSED0_GT2 || \
391 (devid) == PCI_CHIP_SKYLAKE_FUSED1_GT2 || \
392 (devid) == PCI_CHIP_SKYLAKE_ULT_GT2 || \
393 (devid) == PCI_CHIP_SKYLAKE_FUSED2_GT2 || \
394 (devid) == PCI_CHIP_SKYLAKE_SRV_GT2 || \
395 (devid) == PCI_CHIP_SKYLAKE_HALO_GT2 || \
396 (devid) == PCI_CHIP_SKYLAKE_WKS_GT2 || \
397 (devid) == PCI_CHIP_SKYLAKE_ULX_GT2 || \
398 (devid) == PCI_CHIP_SKYLAKE_MOBILE_GT2)
400 #define IS_SKL_GT3(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT3_0 || \
401 (devid) == PCI_CHIP_SKYLAKE_ULT_GT3_1 || \
402 (devid) == PCI_CHIP_SKYLAKE_ULT_GT3_2 || \
403 (devid) == PCI_CHIP_SKYLAKE_HALO_GT3 || \
404 (devid) == PCI_CHIP_SKYLAKE_SRV_GT3)
406 #define IS_SKL_GT4(devid) ((devid) == PCI_CHIP_SKYLAKE_SRV_GT4 || \
407 (devid) == PCI_CHIP_SKYLAKE_DT_GT4 || \
408 (devid) == PCI_CHIP_SKYLAKE_SRV_GT4X || \
409 (devid) == PCI_CHIP_SKYLAKE_H_GT4 || \
410 (devid) == PCI_CHIP_SKYLAKE_WKS_GT4)
412 #define IS_KBL_GT1(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT1_5 || \
413 (devid) == PCI_CHIP_KABYLAKE_ULX_GT1_5 || \
414 (devid) == PCI_CHIP_KABYLAKE_DT_GT1_5 || \
415 (devid) == PCI_CHIP_KABYLAKE_ULT_GT1 || \
416 (devid) == PCI_CHIP_KABYLAKE_ULX_GT1 || \
417 (devid) == PCI_CHIP_KABYLAKE_DT_GT1 || \
418 (devid) == PCI_CHIP_KABYLAKE_HALO_GT1_0 || \
419 (devid) == PCI_CHIP_KABYLAKE_HALO_GT1_1 || \
420 (devid) == PCI_CHIP_KABYLAKE_SRV_GT1)
422 #define IS_KBL_GT2(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT2 || \
423 (devid) == PCI_CHIP_KABYLAKE_ULT_GT2F || \
424 (devid) == PCI_CHIP_KABYLAKE_ULX_GT2 || \
425 (devid) == PCI_CHIP_KABYLAKE_DT_GT2 || \
426 (devid) == PCI_CHIP_KABYLAKE_HALO_GT2 || \
427 (devid) == PCI_CHIP_KABYLAKE_SRV_GT2 || \
428 (devid) == PCI_CHIP_KABYLAKE_WKS_GT2)
430 #define IS_KBL_GT3(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT3_0 || \
431 (devid) == PCI_CHIP_KABYLAKE_ULT_GT3_1 || \
432 (devid) == PCI_CHIP_KABYLAKE_ULT_GT3_2)
434 #define IS_KBL_GT4(devid) ((devid) == PCI_CHIP_KABYLAKE_HALO_GT4)
436 #define IS_KABYLAKE(devid) (IS_KBL_GT1(devid) || \
437 IS_KBL_GT2(devid) || \
438 IS_KBL_GT3(devid) || \
441 #define IS_SKYLAKE(devid) (IS_SKL_GT1(devid) || \
442 IS_SKL_GT2(devid) || \
443 IS_SKL_GT3(devid) || \
446 #define IS_BROXTON(devid) ((devid) == PCI_CHIP_BROXTON_0 || \
447 (devid) == PCI_CHIP_BROXTON_1 || \
448 (devid) == PCI_CHIP_BROXTON_2 || \
449 (devid) == PCI_CHIP_BROXTON_3 || \
450 (devid) == PCI_CHIP_BROXTON_4)
452 #define IS_GEMINILAKE(devid) ((devid) == PCI_CHIP_GLK || \
453 (devid) == PCI_CHIP_GLK_2X6)
455 #define IS_GEN9(devid) (IS_SKYLAKE(devid) || \
456 IS_BROXTON(devid) || \
457 IS_KABYLAKE(devid) || \
458 IS_GEMINILAKE(devid))
460 #define IS_9XX(dev) (IS_GEN3(dev) || \
469 #endif /* _INTEL_CHIPSET_H */