tests/amdgpu/syncobj_tests.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22 */
  23
  24 #include "CUnit/Basic.h"
  25
  26 #include "amdgpu_test.h"
  27 #include "amdgpu_drm.h"
  28 #include "amdgpu_internal.h"
  29 #include <pthread.h>
  30
  31 static  amdgpu_device_handle device_handle;
  32 static  uint32_t  major_version;
  33 static  uint32_t  minor_version;
  34
  35 static void amdgpu_syncobj_timeline_test(void);
  36
  37 CU_BOOL suite_syncobj_timeline_tests_enable(void)
  38 {
  39         return CU_TRUE;
  40 }
  41
  42 int suite_syncobj_timeline_tests_init(void)
  43 {
  44         int r;
  45
  46         r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
  47                                    &minor_version, &device_handle);
  48
  49         if (r) {
  50                 if ((r == -EACCES) && (errno == EACCES))
  51                         printf("\n\nError:%s. "
  52                                 "Hint:Try to run this test program as root.",
  53                                 strerror(errno));
  54                 return CUE_SINIT_FAILED;
  55         }
  56
  57         return CUE_SUCCESS;
  58 }
  59
  60 int suite_syncobj_timeline_tests_clean(void)
  61 {
  62         int r = amdgpu_device_deinitialize(device_handle);
  63
  64         if (r == 0)
  65                 return CUE_SUCCESS;
  66         else
  67                 return CUE_SCLEAN_FAILED;
  68 }
  69
  70
  71 CU_TestInfo syncobj_timeline_tests[] = {
  72         { "syncobj timeline test",  amdgpu_syncobj_timeline_test },
  73         CU_TEST_INFO_NULL,
  74 };
  75
  76 #define GFX_COMPUTE_NOP  0xffff1000
  77 #define SDMA_NOP  0x0
  78 static int syncobj_command_submission_helper(uint32_t syncobj_handle, bool
  79                                              wait_or_signal, uint64_t point)
  80 {
  81         amdgpu_context_handle context_handle;
  82         amdgpu_bo_handle ib_result_handle;
  83         void *ib_result_cpu;
  84         uint64_t ib_result_mc_address;
  85         struct drm_amdgpu_cs_chunk chunks[2];
  86         struct drm_amdgpu_cs_chunk_data chunk_data;
  87         struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
  88         struct amdgpu_cs_fence fence_status;
  89         amdgpu_bo_list_handle bo_list;
  90         amdgpu_va_handle va_handle;
  91         uint32_t expired, flags;
  92         int i, r;
  93         uint64_t seq_no;
  94         static uint32_t *ptr;
  95
  96         r = amdgpu_cs_ctx_create(device_handle, &context_handle);
  97         CU_ASSERT_EQUAL(r, 0);
  98
  99         r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
 100                                     AMDGPU_GEM_DOMAIN_GTT, 0,
 101                                     &ib_result_handle, &ib_result_cpu,
 102                                     &ib_result_mc_address, &va_handle);
 103         CU_ASSERT_EQUAL(r, 0);
 104
 105         r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL,
 106                                &bo_list);
 107         CU_ASSERT_EQUAL(r, 0);
 108
 109         ptr = ib_result_cpu;
 110
 111         for (i = 0; i < 16; ++i)
 112                 ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP: SDMA_NOP;
 113
 114         chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
 115         chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
 116         chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
 117         chunk_data.ib_data._pad = 0;
 118         chunk_data.ib_data.va_start = ib_result_mc_address;
 119         chunk_data.ib_data.ib_bytes = 16 * 4;
 120         chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX :
 121                 AMDGPU_HW_IP_DMA;
 122         chunk_data.ib_data.ip_instance = 0;
 123         chunk_data.ib_data.ring = 0;
 124         chunk_data.ib_data.flags = 0;
 125
 126         chunks[1].chunk_id = wait_or_signal ?
 127                 AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
 128                 AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
 129         chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
 130         chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
 131         syncobj_data.handle = syncobj_handle;
 132         syncobj_data.point = point;
 133         syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
 134
 135         r = amdgpu_cs_submit_raw(device_handle,
 136                                  context_handle,
 137                                  bo_list,
 138                                  2,
 139                                  chunks,
 140                                  &seq_no);
 141         CU_ASSERT_EQUAL(r, 0);
 142
 143
 144         memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
 145         fence_status.context = context_handle;
 146         fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX:
 147                 AMDGPU_HW_IP_DMA;
 148         fence_status.ip_instance = 0;
 149         fence_status.ring = 0;
 150         fence_status.fence = seq_no;
 151
 152         r = amdgpu_cs_query_fence_status(&fence_status,
 153                         AMDGPU_TIMEOUT_INFINITE,0, &expired);
 154         CU_ASSERT_EQUAL(r, 0);
 155
 156         r = amdgpu_bo_list_destroy(bo_list);
 157         CU_ASSERT_EQUAL(r, 0);
 158
 159         r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
 160                                      ib_result_mc_address, 4096);
 161         CU_ASSERT_EQUAL(r, 0);
 162
 163         r = amdgpu_cs_ctx_free(context_handle);
 164         CU_ASSERT_EQUAL(r, 0);
 165
 166         return r;
 167 }
 168
 169 struct syncobj_point {
 170         uint32_t syncobj_handle;
 171         uint64_t point;
 172 };
 173
 174 static void *syncobj_wait(void *data)
 175 {
 176         struct syncobj_point *sp = (struct syncobj_point *)data;
 177         int r;
 178
 179         r = syncobj_command_submission_helper(sp->syncobj_handle, true,
 180                                               sp->point);
 181         CU_ASSERT_EQUAL(r, 0);
 182
 183         return (void *)(long)r;
 184 }
 185
 186 static void *syncobj_signal(void *data)
 187 {
 188         struct syncobj_point *sp = (struct syncobj_point *)data;
 189         int r;
 190
 191         r = syncobj_command_submission_helper(sp->syncobj_handle, false,
 192                                               sp->point);
 193         CU_ASSERT_EQUAL(r, 0);
 194
 195         return (void *)(long)r;
 196 }
 197
 198 static void amdgpu_syncobj_timeline_test(void)
 199 {
 200         static pthread_t wait_thread;
 201         static pthread_t signal_thread;
 202         static pthread_t c_thread;
 203         struct syncobj_point sp1, sp2, sp3;
 204         uint32_t syncobj_handle;
 205         uint64_t payload;
 206         uint64_t wait_point, signal_point;
 207         uint64_t timeout;
 208         struct timespec tp;
 209         int r, sync_fd;
 210         void *tmp;
 211
 212         r =  amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
 213         CU_ASSERT_EQUAL(r, 0);
 214
 215         // wait on point 5
 216         sp1.syncobj_handle = syncobj_handle;
 217         sp1.point = 5;
 218         r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
 219         CU_ASSERT_EQUAL(r, 0);
 220
 221         // signal on point 10
 222         sp2.syncobj_handle = syncobj_handle;
 223         sp2.point = 10;
 224         r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
 225         CU_ASSERT_EQUAL(r, 0);
 226
 227         r = pthread_join(wait_thread, &tmp);
 228         CU_ASSERT_EQUAL(r, 0);
 229         CU_ASSERT_EQUAL(tmp, 0);
 230
 231         r = pthread_join(signal_thread, &tmp);
 232         CU_ASSERT_EQUAL(r, 0);
 233         CU_ASSERT_EQUAL(tmp, 0);
 234
 235         //query timeline payload
 236         r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
 237                                     &payload, 1);
 238         CU_ASSERT_EQUAL(r, 0);
 239         CU_ASSERT_EQUAL(payload, 10);
 240
 241         //signal on point 16
 242         sp3.syncobj_handle = syncobj_handle;
 243         sp3.point = 16;
 244         r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
 245         CU_ASSERT_EQUAL(r, 0);
 246         //CPU wait on point 16
 247         wait_point = 16;
 248         timeout = 0;
 249         clock_gettime(CLOCK_MONOTONIC, &tp);
 250         timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
 251         timeout += 0x10000000000; //10s
 252         r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
 253                                             &wait_point, 1, timeout,
 254                                             DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
 255                                             DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
 256                                             NULL);
 257
 258         CU_ASSERT_EQUAL(r, 0);
 259         r = pthread_join(c_thread, &tmp);
 260         CU_ASSERT_EQUAL(r, 0);
 261         CU_ASSERT_EQUAL(tmp, 0);
 262
 263         // export point 16 and import to point 18
 264         r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
 265                                                 16,
 266                                                 DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
 267                                                 &sync_fd);
 268         CU_ASSERT_EQUAL(r, 0);
 269         r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
 270                                                 18, sync_fd);
 271         CU_ASSERT_EQUAL(r, 0);
 272         r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
 273                                     &payload, 1);
 274         CU_ASSERT_EQUAL(r, 0);
 275         CU_ASSERT_EQUAL(payload, 18);
 276
 277         // CPU signal on point 20
 278         signal_point = 20;
 279         r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
 280                                               &signal_point, 1);
 281         CU_ASSERT_EQUAL(r, 0);
 282         r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
 283                                     &payload, 1);
 284         CU_ASSERT_EQUAL(r, 0);
 285         CU_ASSERT_EQUAL(payload, 20);
 286
 287         r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
 288         CU_ASSERT_EQUAL(r, 0);
 289
 290 }