intel: Update i915_drm.h

Copy from drm-intel-nightly a307a3a81c2bf2883457e03abcf5c9520cf452c1.

Signed-off-by: Kristian Høgsberg Kristensen <kristian.h.kristensen@intel.com>

diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index ded43b1..0e51d42 100644 (file)
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -27,7 +27,7 @@
 #ifndef _I915_DRM_H_
 #define _I915_DRM_H_
 
-#include <drm.h>
+#include "drm.h"
 
 /* Please note that modifications to all structs defined here are
  * subject to backwards-compatibility constraints.
@@ -171,8 +171,12 @@ typedef struct _drm_i915_sarea {
 #define I915_BOX_TEXTURE_LOAD  0x8
 #define I915_BOX_LOST_CONTEXT  0x10
 
-/* I915 specific ioctls
- * The device specific ioctl range is 0x40 to 0x79.
+/*
+ * i915 specific ioctls.
+ *
+ * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie
+ * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset
+ * against DRM_COMMAND_BASE and should be between [0x0, 0x60).
  */
 #define DRM_I915_INIT          0x00
 #define DRM_I915_FLUSH         0x01
@@ -270,7 +274,7 @@ typedef struct _drm_i915_sarea {
 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE       DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
 #define DRM_IOCTL_I915_OVERLAY_ATTRS   DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
 #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
-#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
+#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
 #define DRM_IOCTL_I915_GEM_WAIT                DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE      DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY     DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
@@ -350,9 +354,16 @@ typedef struct drm_i915_irq_wait {
 #define I915_PARAM_REVISION              32
 #define I915_PARAM_SUBSLICE_TOTAL       33
 #define I915_PARAM_EU_TOTAL             34
+#define I915_PARAM_HAS_GPU_RESET        35
+#define I915_PARAM_HAS_RESOURCE_STREAMER 36
+#define I915_PARAM_HAS_EXEC_SOFTPIN     37
 
 typedef struct drm_i915_getparam {
-       int param;
+       __s32 param;
+       /*
+        * WARNING: Using pointers instead of fixed-size u64 means we need to write
+        * compat32 code. Don't repeat this mistake.
+        */
        int *value;
 } drm_i915_getparam_t;
 
@@ -672,15 +683,21 @@ struct drm_i915_gem_exec_object2 {
        __u64 alignment;
 
        /**
-        * Returned value of the updated offset of the object, for future
-        * presumed_offset writes.
+        * When the EXEC_OBJECT_PINNED flag is specified this is populated by
+        * the user with the GTT offset at which this object will be pinned.
+        * When the I915_EXEC_NO_RELOC flag is specified this must contain the
+        * presumed_offset of the object.
+        * During execbuffer2 the kernel populates it with the value of the
+        * current GTT offset of the object, for future presumed_offset writes.
         */
        __u64 offset;
 
 #define EXEC_OBJECT_NEEDS_FENCE (1<<0)
 #define EXEC_OBJECT_NEEDS_GTT  (1<<1)
 #define EXEC_OBJECT_WRITE      (1<<2)
-#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_WRITE<<1)
+#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
+#define EXEC_OBJECT_PINNED     (1<<4)
+#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_PINNED<<1)
        __u64 flags;
 
        __u64 rsvd1;
@@ -760,7 +777,12 @@ struct drm_i915_gem_execbuffer2 {
 #define I915_EXEC_BSD_RING1            (1<<13)
 #define I915_EXEC_BSD_RING2            (2<<13)
 
-#define __I915_EXEC_UNKNOWN_FLAGS -(1<<15)
+/** Tell the kernel that the batchbuffer is processed by
+ *  the resource streamer.
+ */
+#define I915_EXEC_RESOURCE_STREAMER     (1<<15)
+
+#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_RESOURCE_STREAMER<<1)
 
 #define I915_EXEC_CONTEXT_ID_MASK      (0xffffffff)
 #define i915_execbuffer2_set_context_id(eb2, context) \
@@ -996,6 +1018,7 @@ struct drm_intel_overlay_put_image {
 /* flags */
 #define I915_OVERLAY_UPDATE_ATTRS      (1<<0)
 #define I915_OVERLAY_UPDATE_GAMMA      (1<<1)
+#define I915_OVERLAY_DISABLE_DEST_COLORKEY     (1<<2)
 struct drm_intel_overlay_attrs {
        __u32 flags;
        __u32 color_key;
@@ -1062,9 +1085,23 @@ struct drm_i915_gem_context_destroy {
 };
 
 struct drm_i915_reg_read {
+       /*
+        * Register offset.
+        * For 64bit wide registers where the upper 32bits don't immediately
+        * follow the lower 32bits, the offset of the lower 32bits must
+        * be specified
+        */
        __u64 offset;
        __u64 val; /* Return value */
 };
+/* Known registers:
+ *
+ * Render engine timestamp - 0x2358 + 64bit - gen7+
+ * - Note this register returns an invalid value if using the default
+ *   single instruction 8byte read, in order to workaround that use
+ *   offset (0x2538 | 1) instead.
+ *
+ */
 
 struct drm_i915_reset_stats {
        __u32 ctx_id;
@@ -1100,7 +1137,9 @@ struct drm_i915_gem_context_param {
        __u32 ctx_id;
        __u32 size;
        __u64 param;
-#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
+#define I915_CONTEXT_PARAM_BAN_PERIOD  0x1
+#define I915_CONTEXT_PARAM_NO_ZEROMAP  0x2
+#define I915_CONTEXT_PARAM_GTT_SIZE    0x3
        __u64 value;
 };