intel: Fixup for the fix for relaxed tiling on gen2

This is Fail.

First patch to libdrm, and I've borked it up.

Noticed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 9b324d9..f5ab0a6 100644 (file)
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -767,7 +767,7 @@ drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
                else if (tiling == I915_TILING_Y)
                        height_alignment = 32;
                /* i8xx has a interleaved 2-row tile layout */
-               if (IS_GEN2(bufmgr_gem))
+               if (IS_GEN2(bufmgr_gem) && tiling != I915_TILING_NONE)
                        height_alignment *= 2;
                aligned_y = ALIGN(y, height_alignment);