2 * (C) Copyright IBM Corporation 2006
3 * Copyright 2009 Red Hat, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * IBM AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
26 * Copyright (c) 2007 Paulo R. Zanoni, Tiago Vignatti
28 * Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or sell
33 * copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
54 * \author Ian Romanick <idr@us.ibm.com>
63 #define __deprecated __attribute__((deprecated))
68 typedef uint64_t pciaddr_t;
71 struct pci_device_iterator;
73 struct pci_slot_match;
79 int pci_device_has_kernel_driver(struct pci_device *dev);
81 int pci_device_is_boot_vga(struct pci_device *dev);
83 int pci_device_read_rom(struct pci_device *dev, void *buffer);
85 int __deprecated pci_device_map_region(struct pci_device *dev,
86 unsigned region, int write_enable);
88 int __deprecated pci_device_unmap_region(struct pci_device *dev,
91 int pci_device_map_range(struct pci_device *dev, pciaddr_t base,
92 pciaddr_t size, unsigned map_flags, void **addr);
94 int pci_device_unmap_range(struct pci_device *dev, void *memory,
97 int __deprecated pci_device_map_memory_range(struct pci_device *dev,
98 pciaddr_t base, pciaddr_t size, int write_enable, void **addr);
100 int __deprecated pci_device_unmap_memory_range(struct pci_device *dev,
101 void *memory, pciaddr_t size);
103 int pci_device_probe(struct pci_device *dev);
105 const struct pci_agp_info *pci_device_get_agp_info(struct pci_device *dev);
107 const struct pci_bridge_info *pci_device_get_bridge_info(
108 struct pci_device *dev);
110 const struct pci_pcmcia_bridge_info *pci_device_get_pcmcia_bridge_info(
111 struct pci_device *dev);
113 int pci_device_get_bridge_buses(struct pci_device *dev, int *primary_bus,
114 int *secondary_bus, int *subordinate_bus);
116 int pci_system_init(void);
118 void pci_system_init_dev_mem(int fd);
120 void pci_system_cleanup(void);
122 struct pci_device_iterator *pci_slot_match_iterator_create(
123 const struct pci_slot_match *match);
125 struct pci_device_iterator *pci_id_match_iterator_create(
126 const struct pci_id_match *match);
128 void pci_iterator_destroy(struct pci_device_iterator *iter);
130 struct pci_device *pci_device_next(struct pci_device_iterator *iter);
132 struct pci_device *pci_device_find_by_slot(uint32_t domain, uint32_t bus,
133 uint32_t dev, uint32_t func);
135 struct pci_device *pci_device_get_parent_bridge(struct pci_device *dev);
137 void pci_get_strings(const struct pci_id_match *m,
138 const char **device_name, const char **vendor_name,
139 const char **subdevice_name, const char **subvendor_name);
140 const char *pci_device_get_device_name(const struct pci_device *dev);
141 const char *pci_device_get_subdevice_name(const struct pci_device *dev);
142 const char *pci_device_get_vendor_name(const struct pci_device *dev);
143 const char *pci_device_get_subvendor_name(const struct pci_device *dev);
145 void pci_device_enable(struct pci_device *dev);
147 int pci_device_cfg_read (struct pci_device *dev, void *data,
148 pciaddr_t offset, pciaddr_t size, pciaddr_t *bytes_read);
149 int pci_device_cfg_read_u8 (struct pci_device *dev, uint8_t *data,
151 int pci_device_cfg_read_u16(struct pci_device *dev, uint16_t *data,
153 int pci_device_cfg_read_u32(struct pci_device *dev, uint32_t *data,
156 int pci_device_cfg_write (struct pci_device *dev, const void *data,
157 pciaddr_t offset, pciaddr_t size, pciaddr_t *bytes_written);
158 int pci_device_cfg_write_u8 (struct pci_device *dev, uint8_t data,
160 int pci_device_cfg_write_u16(struct pci_device *dev, uint16_t data,
162 int pci_device_cfg_write_u32(struct pci_device *dev, uint32_t data,
164 int pci_device_cfg_write_bits(struct pci_device *dev, uint32_t mask,
165 uint32_t data, pciaddr_t offset);
172 * \name Mapping flags passed to \c pci_device_map_range
175 #define PCI_DEV_MAP_FLAG_WRITABLE (1U<<0)
176 #define PCI_DEV_MAP_FLAG_WRITE_COMBINE (1U<<1)
177 #define PCI_DEV_MAP_FLAG_CACHABLE (1U<<2)
181 #define PCI_MATCH_ANY (~0)
184 * Compare two PCI ID values (either vendor or device). This is used
185 * internally to compare the fields of \c pci_id_match to the fields of
188 #define PCI_ID_COMPARE(a, b) \
189 (((a) == PCI_MATCH_ANY) || ((a) == (b)))
193 struct pci_id_match {
195 * \name Device / vendor matching controls
197 * Control the search based on the device, vendor, subdevice, or subvendor
198 * IDs. Setting any of these fields to \c PCI_MATCH_ANY will cause the
199 * field to not be used in the comparison.
204 uint32_t subvendor_id;
205 uint32_t subdevice_id;
210 * \name Device class matching controls
214 uint32_t device_class;
215 uint32_t device_class_mask;
224 struct pci_slot_match {
226 * \name Device slot matching controls
228 * Control the search based on the domain, bus, slot, and function of
229 * the device. Setting any of these fields to \c PCI_MATCH_ANY will cause
230 * the field to not be used in the comparison.
243 * BAR descriptor for a PCI device.
245 struct pci_mem_region {
247 * When the region is mapped, this is the pointer to the memory.
249 * This field is \b only set when the deprecated \c pci_device_map_region
250 * interface is used. Use \c pci_device_map_range instead.
258 * Base physical address of the region within its bus / domain.
261 * This address is really only useful to other devices in the same
262 * domain. It's probably \b not the address applications will ever
266 * Most (all?) platform back-ends leave this field unset.
272 * Base physical address of the region from the CPU's point of view.
274 * This address is typically passed to \c pci_device_map_range to create
275 * a mapping of the region to the CPU's virtual address space.
281 * Size, in bytes, of the region.
287 * Is the region I/O ports or memory?
292 * Is the memory region prefetchable?
295 * This can only be set if \c is_IO is not set.
297 unsigned is_prefetchable:1;
301 * Is the memory at a 64-bit address?
304 * This can only be set if \c is_IO is not set.
313 * Contains all of the information about a particular PCI device.
317 * \name Device bus identification.
319 * Complete bus identification, including domain, of the device. On
320 * platforms that do not support PCI domains (e.g., 32-bit x86 hardware),
321 * the domain will always be zero.
332 * \name Vendor / device ID
334 * The vendor ID, device ID, and sub-IDs for the device.
339 uint16_t subvendor_id;
340 uint16_t subdevice_id;
344 * Device's class, subclass, and programming interface packed into a
345 * single 32-bit value. The class is at bits [23:16], subclass is at
346 * bits [15:8], and programming interface is at [7:0].
348 uint32_t device_class;
352 * Device revision number, as read from the configuration header.
358 * BAR descriptors for the device.
360 struct pci_mem_region regions[6];
364 * Size, in bytes, of the device's expansion ROM.
370 * IRQ associated with the device. If there is no IRQ, this value will
377 * Storage for user data. Users of the library can store arbitrary
378 * data in this pointer. The library will not use it for any purpose.
379 * It is the user's responsability to free this memory before destroying
380 * the \c pci_device structure.
385 * Used by the VGA arbiter. Type of resource decoded by the device and
386 * the file descriptor (/dev/vga_arbiter). */
392 * Description of the AGP capability of the device.
394 * \sa pci_device_get_agp_info
396 struct pci_agp_info {
398 * Offset of the AGP registers in the devices configuration register
399 * space. This is generally used so that the offset of the AGP command
400 * register can be determined.
402 unsigned config_offset;
406 * \name AGP major / minor version.
409 uint8_t major_version;
410 uint8_t minor_version;
414 * Logical OR of the supported AGP rates. For example, a value of 0x07
415 * means that the device can support 1x, 2x, and 4x. A value of 0x0c
416 * means that the device can support 8x and 4x.
420 unsigned int fast_writes:1; /**< Are fast-writes supported? */
421 unsigned int addr64:1;
422 unsigned int htrans:1;
423 unsigned int gart64:1;
424 unsigned int coherent:1;
425 unsigned int sideband:1; /**< Is side-band addressing supported? */
426 unsigned int isochronus:1;
428 uint8_t async_req_size;
429 uint8_t calibration_cycle_timing;
430 uint8_t max_requests;
434 * Description of a PCI-to-PCI bridge device.
436 * \sa pci_device_get_bridge_info
438 struct pci_bridge_info {
440 uint8_t secondary_bus;
441 uint8_t subordinate_bus;
442 uint8_t secondary_latency_timer;
446 uint8_t prefetch_mem_type;
448 uint16_t secondary_status;
449 uint16_t bridge_control;
457 uint64_t prefetch_mem_base;
458 uint64_t prefetch_mem_limit;
462 * Description of a PCI-to-PCMCIA bridge device.
464 * \sa pci_device_get_pcmcia_bridge_info
466 struct pci_pcmcia_bridge_info {
469 uint8_t subordinate_bus;
470 uint8_t cardbus_latency_timer;
472 uint16_t secondary_status;
473 uint16_t bridge_control;
489 * VGA Arbiter definitions, functions and related.
492 /* Legacy VGA regions */
493 #define VGA_ARB_RSRC_NONE 0x00
494 #define VGA_ARB_RSRC_LEGACY_IO 0x01
495 #define VGA_ARB_RSRC_LEGACY_MEM 0x02
496 /* Non-legacy access */
497 #define VGA_ARB_RSRC_NORMAL_IO 0x04
498 #define VGA_ARB_RSRC_NORMAL_MEM 0x08
500 int pci_device_vgaarb_init (void);
501 void pci_device_vgaarb_fini (void);
502 int pci_device_vgaarb_set_target (struct pci_device *dev);
503 /* use the targetted device */
504 int pci_device_vgaarb_decodes (int new_vga_rsrc);
505 int pci_device_vgaarb_lock (void);
506 int pci_device_vgaarb_trylock (void);
507 int pci_device_vgaarb_unlock (void);
508 /* return the current device count + resource decodes for the device */
509 int pci_device_vgaarb_get_info (struct pci_device *dev, int *vga_count, int *rsrc_decodes);
515 struct pci_io_handle;
517 struct pci_io_handle *pci_device_open_io(struct pci_device *dev, pciaddr_t base,
519 struct pci_io_handle *pci_legacy_open_io(struct pci_device *dev, pciaddr_t base,
521 void pci_device_close_io(struct pci_device *dev, struct pci_io_handle *handle);
522 uint32_t pci_io_read32(struct pci_io_handle *handle, uint32_t reg);
523 uint16_t pci_io_read16(struct pci_io_handle *handle, uint32_t reg);
524 uint8_t pci_io_read8(struct pci_io_handle *handle, uint32_t reg);
525 void pci_io_write32(struct pci_io_handle *handle, uint32_t reg, uint32_t data);
526 void pci_io_write16(struct pci_io_handle *handle, uint32_t reg, uint16_t data);
527 void pci_io_write8(struct pci_io_handle *handle, uint32_t reg, uint8_t data);
529 #endif /* PCIACCESS_H */