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26 * \file common_bridge.c
27 * Support routines used to process PCI header information for bridges.
29 * \author Ian Romanick <idr@us.ibm.com>
41 #if defined(HAVE_STRING_H)
43 #elif defined(HAVE_STRINGS_H)
47 #if defined(HAVE_INTTYPES_H)
48 # include <inttypes.h>
49 #elif defined(HAVE_STDINT_H)
53 #include "pciaccess.h"
54 #include "pciaccess_private.h"
57 read_bridge_info( struct pci_device_private * priv )
64 /* Make sure the device has been probed. If not, header_type won't be
65 * set and the rest of this function will fail.
67 err = pci_device_probe(& priv->base);
72 switch ( priv->header_type & 0x7f ) {
77 struct pci_bridge_info *info;
79 info = malloc(sizeof(*info));
81 pci_device_cfg_read( (struct pci_device *) priv, buf + 0x18, 0x18,
82 0x40 - 0x18, & bytes );
84 info->primary_bus = buf[0x18];
85 info->secondary_bus = buf[0x19];
86 info->subordinate_bus = buf[0x1a];
87 info->secondary_latency_timer = buf[0x1b];
89 info->io_type = buf[0x1c] & 0x0f;
90 info->io_base = (((uint32_t) (buf[0x1c] & 0x0f0)) << 8)
91 + (((uint32_t) buf[0x30]) << 16)
92 + (((uint32_t) buf[0x31]) << 24);
94 info->io_limit = 0x00000fff
95 + (((uint32_t) (buf[0x1d] & 0x0f0)) << 8)
96 + (((uint32_t) buf[0x32]) << 16)
97 + (((uint32_t) buf[0x33]) << 24);
99 info->mem_type = buf[0x20] & 0x0f;
100 info->mem_base = (((uint32_t) (buf[0x20] & 0x0f0)) << 16)
101 + (((uint32_t) buf[0x21]) << 24);
103 info->mem_limit = 0x0000ffff
104 + (((uint32_t) (buf[0x22] & 0x0f0)) << 16)
105 + (((uint32_t) buf[0x23]) << 24);
107 info->prefetch_mem_type = buf[0x24] & 0x0f;
108 info->prefetch_mem_base = (((uint64_t) (buf[0x24] & 0x0f0)) << 16)
109 + (((uint64_t) buf[0x25]) << 24)
110 + (((uint64_t) buf[0x28]) << 32)
111 + (((uint64_t) buf[0x29]) << 40)
112 + (((uint64_t) buf[0x2a]) << 48)
113 + (((uint64_t) buf[0x2b]) << 56);
115 info->prefetch_mem_limit = 0x0000ffff
116 + (((uint64_t) (buf[0x26] & 0x0f0)) << 16)
117 + (((uint64_t) buf[0x27]) << 24)
118 + (((uint64_t) buf[0x2c]) << 32)
119 + (((uint64_t) buf[0x2d]) << 40)
120 + (((uint64_t) buf[0x2e]) << 48)
121 + (((uint64_t) buf[0x2f]) << 56);
123 info->bridge_control = ((uint16_t) buf[0x3e])
124 + (((uint16_t) buf[0x3f]) << 8);
126 info->secondary_status = ((uint16_t) buf[0x1e])
127 + (((uint16_t) buf[0x1f]) << 8);
130 priv->bridge.pci = info;
135 struct pci_pcmcia_bridge_info *info;
137 info = malloc(sizeof(*info));
139 pci_device_cfg_read( (struct pci_device *) priv, buf + 0x16, 0x16,
140 0x40 - 0x16, & bytes );
142 info->primary_bus = buf[0x18];
143 info->card_bus = buf[0x19];
144 info->subordinate_bus = buf[0x1a];
145 info->cardbus_latency_timer = buf[0x1b];
147 info->mem[0].base = (((uint32_t) buf[0x1c]))
148 + (((uint32_t) buf[0x1d]) << 8)
149 + (((uint32_t) buf[0x1e]) << 16)
150 + (((uint32_t) buf[0x1f]) << 24);
152 info->mem[0].limit = (((uint32_t) buf[0x20]))
153 + (((uint32_t) buf[0x21]) << 8)
154 + (((uint32_t) buf[0x22]) << 16)
155 + (((uint32_t) buf[0x23]) << 24);
157 info->mem[1].base = (((uint32_t) buf[0x24]))
158 + (((uint32_t) buf[0x25]) << 8)
159 + (((uint32_t) buf[0x26]) << 16)
160 + (((uint32_t) buf[0x27]) << 24);
162 info->mem[1].limit = (((uint32_t) buf[0x28]))
163 + (((uint32_t) buf[0x29]) << 8)
164 + (((uint32_t) buf[0x2a]) << 16)
165 + (((uint32_t) buf[0x2b]) << 24);
167 info->io[0].base = (((uint32_t) buf[0x2c]))
168 + (((uint32_t) buf[0x2d]) << 8)
169 + (((uint32_t) buf[0x2e]) << 16)
170 + (((uint32_t) buf[0x2f]) << 24);
172 info->io[0].limit = (((uint32_t) buf[0x30]))
173 + (((uint32_t) buf[0x31]) << 8)
174 + (((uint32_t) buf[0x32]) << 16)
175 + (((uint32_t) buf[0x33]) << 24);
177 info->io[1].base = (((uint32_t) buf[0x34]))
178 + (((uint32_t) buf[0x35]) << 8)
179 + (((uint32_t) buf[0x36]) << 16)
180 + (((uint32_t) buf[0x37]) << 24);
182 info->io[1].limit = (((uint32_t) buf[0x38]))
183 + (((uint32_t) buf[0x39]) << 8)
184 + (((uint32_t) buf[0x3a]) << 16)
185 + (((uint32_t) buf[0x3b]) << 24);
187 info->secondary_status = ((uint16_t) buf[0x16])
188 + (((uint16_t) buf[0x17]) << 8);
190 info->bridge_control = ((uint16_t) buf[0x3e])
191 + (((uint16_t) buf[0x3f]) << 8);
194 priv->bridge.pcmcia = info;
204 * Get the PCI bridge information for a device
207 * If \c dev is a PCI-to-PCI bridge, a pointer to a \c pci_bridge_info
208 * structure. Otherwise, \c NULL is returned.
210 const struct pci_bridge_info *
211 pci_device_get_bridge_info( struct pci_device * dev )
213 struct pci_device_private * priv = (struct pci_device_private *) dev;
215 if (priv->bridge.pci == NULL) {
216 read_bridge_info(priv);
219 return (priv->header_type == 1) ? priv->bridge.pci : NULL;
224 * Get the PCMCIA bridge information for a device
227 * If \c dev is a PCI-to-PCMCIA bridge, a pointer to a
228 * \c pci_pcmcia_bridge_info structure. Otherwise, \c NULL is returned.
230 const struct pci_pcmcia_bridge_info *
231 pci_device_get_pcmcia_bridge_info( struct pci_device * dev )
233 struct pci_device_private * priv = (struct pci_device_private *) dev;
235 if (priv->bridge.pcmcia == NULL) {
236 read_bridge_info(priv);
239 return (priv->header_type == 2) ? priv->bridge.pcmcia : NULL;
244 * Determine the primary, secondary, and subordinate buses for a bridge
246 * Determines the IDs of the primary, secondary, and subordinate buses for
247 * a specified bridge. Not all bridges directly store this information
248 * (e.g., PCI-to-ISA bridges). For those bridges, no error is returned, but
249 * -1 is stored in the bus IDs that don't make sense.
251 * For example, for a PCI-to-ISA bridge, \c primary_bus will be set to the ID
252 * of the bus containing the device and both \c secondary_bus and
253 * \c subordinate_bus will be set to -1.
256 * On success, zero is returned. If \c dev is not a bridge, \c ENODEV is
260 * Host bridges are handled the same way as PCI-to-ISA bridges. This is
261 * almost certainly not correct.
264 pci_device_get_bridge_buses(struct pci_device * dev, int *primary_bus,
265 int *secondary_bus, int *subordinate_bus)
267 struct pci_device_private * priv = (struct pci_device_private *) dev;
269 /* If the device isn't a bridge, return an error.
272 if (((dev->device_class >> 16) & 0x0ff) != 0x06) {
276 switch ((dev->device_class >> 8) & 0x0ff) {
278 /* What to do for host bridges? I'm pretty sure this isn't right.
280 *primary_bus = dev->bus;
282 *subordinate_bus = -1;
288 *primary_bus = dev->bus;
290 *subordinate_bus = -1;
294 if (priv->bridge.pci == NULL)
295 read_bridge_info(priv);
296 if ((priv->header_type & 0x7f) == 0x01) {
297 *primary_bus = priv->bridge.pci->primary_bus;
298 *secondary_bus = priv->bridge.pci->secondary_bus;
299 *subordinate_bus = priv->bridge.pci->subordinate_bus;
301 *primary_bus = dev->bus;
303 *subordinate_bus = -1;
308 if (priv->bridge.pcmcia == NULL)
309 read_bridge_info(priv);
310 if ((priv->header_type & 0x7f) == 0x02) {
311 *primary_bus = priv->bridge.pcmcia->primary_bus;
312 *secondary_bus = priv->bridge.pcmcia->card_bus;
313 *subordinate_bus = priv->bridge.pcmcia->subordinate_bus;
315 *primary_bus = dev->bus;
317 *subordinate_bus = -1;
325 #define PCI_CLASS_BRIDGE 0x06
326 #define PCI_SUBCLASS_BRIDGE_PCI 0x04
327 #define PCI_CLASS_MASK 0xFF
328 #define PCI_SUBCLASS_MASK 0xFF
331 pci_device_get_parent_bridge(struct pci_device *dev)
333 struct pci_id_match bridge_match = {
334 PCI_MATCH_ANY, PCI_MATCH_ANY, PCI_MATCH_ANY, PCI_MATCH_ANY,
335 (PCI_CLASS_BRIDGE << 16) | (PCI_SUBCLASS_BRIDGE_PCI << 8),
336 (PCI_CLASS_MASK << 16) | (PCI_SUBCLASS_MASK << 8), 0
339 struct pci_device *bridge;
340 struct pci_device_iterator *iter;
345 iter = pci_id_match_iterator_create(& bridge_match);
349 while ((bridge = pci_device_next(iter)) != NULL) {
350 if (bridge->domain == dev->domain) {
351 const struct pci_bridge_info *info =
352 pci_device_get_bridge_info(bridge);
355 if (info->secondary_bus == dev->bus) {
362 pci_iterator_destroy(iter);