1 This file is a partial list of people who have contributed to the LLVM
2 project. If you have contributed a patch or made some other contribution to
3 LLVM, please submit a patch to this file to add yourself, and it will be
6 The list is sorted by surname and formatted to allow easy grepping and
7 beautification by scripts. The fields are: name (N), email (E), web-address
8 (W), PGP key ID and fingerprint (P), description (D), snail-mail address
9 (S), and (I) IRC handle.
13 W: http://www.cs.uiuc.edu/~vadve/
14 D: The Sparc64 backend, provider of much wisdom, and motivator for LLVM
18 D: LCSSA pass and related LoopUnswitch work
19 D: GVNPRE pass, DataLayout refactoring, random improvements
22 D: MingW Win32 API portability layer
25 E: aaron@aaronballman.com
26 D: __declspec attributes, Windows support, general bug fixing
29 E: natebegeman@mac.com
30 D: PowerPC backend developer
31 D: Target-independent code generator and analysis improvements
34 E: dberlin@dberlin.org
35 D: ET-Forest implementation.
40 D: General bug fixing/fit & finish, mostly in Clang
43 E: neil@daikokuya.co.uk
44 D: APFloat implementation.
51 E: brukman+llvm@uiuc.edu
52 W: http://misha.brukman.net
53 D: Portions of X86 and Sparc JIT compilers, PowerPC backend
54 D: Incremental bitcode loader
58 D: The `mem2reg' pass - promotes values stored in memory to registers
61 E: bcahoon@codeaurora.org
62 D: Loop unrolling with run-time trip counts.
65 E: chandlerc@gmail.com
66 E: chandlerc@google.com
67 D: Hashing algorithms and interfaces
68 D: Inline cost analysis
69 D: Machine block placement pass
74 D: Fixes to the Reassociation pass, various improvement patches
77 E: evan.cheng@apple.com
78 D: ARM and X86 backends
79 D: Instruction scheduler improvements
80 D: Register allocator improvements
81 D: Loop optimizer improvements
82 D: Target-independent code generator improvements
84 N: Dan Villiom Podlaski Christiansen
88 D: LLVM Makefile improvements
89 D: Clang diagnostic & driver tweaks
93 E: jeffc@jolt-lang.org
94 W: http://jolt-lang.org
95 D: Native Win32 API portability layer
99 D: Original Autoconf support, documentation improvements, bug fixes
102 E: adasgupt@codeaurora.org
103 D: Deterministic finite automaton based infrastructure for VLIW packetization
106 E: stefanus.du.toit@intel.com
107 D: Bug fixes and minor improvements
109 N: Rafael Avila de Espindola
114 E: cestes@codeaurora.org
115 D: AArch64 machine description for Cortex-A53
118 E: alkis@evlogimenos.com
119 D: Linear scan register allocator, many codegen improvements, Java frontend
123 D: Basic-block autovectorization, PowerPC backend improvements
127 D: LIT patches and documentation.
130 E: pizza@parseerror.com
131 D: Miscellaneous bug fixes
135 W: http://www.students.uiuc.edu/~gaeke/
136 D: Portions of X86 static and JIT compilers; initial SparcV8 backend
137 D: Dynamic trace optimizer
138 D: FreeBSD/X86 compatibility fixes, the llvm-nm tool
141 E: nicolas.geoffray@lip6.fr
142 W: http://www-src.lip6.fr/homepages/Nicolas.Geoffray/
143 D: PPC backend fixes for Linux
147 D: Portions of the PowerPC backend
150 E: saemghani@gmail.com
151 D: Callgraph class cleanups
153 N: Mikhail Glushenkov
154 E: foldr@codedgers.com
158 E: sunfish@mozilla.com
159 D: Miscellaneous bug fixes
160 D: WebAssembly Backend
163 E: david@goodwinz.net
164 D: Thumb-2 code generator
167 E: greened@obbligato.org
168 D: Miscellaneous bug fixes
169 D: Register allocation refactoring
173 D: Improvements for space efficiency
176 E: grosbach@apple.com
178 D: SjLj exception handling support
179 D: General fixes and improvements for the ARM back-end
181 D: ARM integrated assembler and assembly parser
182 D: Led effort for the backend formerly known as ARM64
186 D: PBQP-based register allocator
189 E: gordonhenriksen@mac.com
190 D: Pluggable GC support
194 N: Raul Fernandes Herbster
195 E: raul@dsc.ufcg.edu.br
196 D: JIT support for ARM
199 E: arathorn@fastwebnet.it
200 D: Visual C++ compatibility fixes
203 E: patjenk@wam.umd.edu
206 N: Tony(Yanjun) Jiang
208 D: PowerPC Backend Developer
209 D: Improvements to the PPC backend and miscellaneous bug fixes
213 D: ARM constant islands improvements
214 D: Tail merging improvements
215 D: Rewrite X87 back end
216 D: Use APFloat for floating point constants widely throughout compiler
217 D: Implement X87 long double
220 E: kungfoomaster@nondot.org
221 D: Support for packed types
225 D: Author of LLVM Ada bindings
228 E: erich.keane@intel.com
229 D: A variety of Clang contributions including function multiversioning, regcall/vectorcall.
233 W: http://randomhacks.net/
234 D: llvm-config script
236 N: Anton Korobeynikov
237 E: anton at korobeynikov dot info
238 D: Mingw32 fixes, cross-compiling support, stdcall/fastcall calling conv.
239 D: x86/linux PIC codegen, aliases, regparm/visibility attributes
240 D: Switch lowering refactoring
244 D: Author of the original C backend
247 E: benny.kra@gmail.com
248 D: Miscellaneous bug fixes
251 E: sundeepk@codeaurora.org
252 D: Implemented DFA-based target independent VLIW packetizer
255 E: christopher.lamb@gmail.com
256 D: aligned load/store support, parts of noalias and restrict support
257 D: vreg subreg infrastructure, X86 codegen improvements based on subregs
262 D: Improvements to the PPC backend, instruction scheduling
263 D: Debug and Dwarf implementation
264 D: Auto upgrade mangler
265 D: llvm-gcc4 svn wrangler
269 W: http://nondot.org/~sabre/
270 D: Primary architect of LLVM
272 N: Tanya Lattner (Tanya Brethour)
274 W: http://nondot.org/~tonic/
275 D: The initial llvm-ar tool, converted regression testsuite to dejagnu
276 D: Modulo scheduling in the SparcV9 backend
277 D: Release manager (1.7+)
280 E: sylvestre@debian.org
281 W: http://sylvestre.ledru.info/
282 W: https://apt.llvm.org/
283 D: Debian and Ubuntu packaging
284 D: Continuous integration with jenkins
287 E: alenhar2@cs.uiuc.edu
288 W: http://www.lenharth.org/~andrewl/
290 D: Sampling based profiling
294 D: PredicateSimplifier pass
296 N: Tony Linthicum, et. al.
297 E: tlinth@codeaurora.org
298 D: Backend for Qualcomm's Hexagon VLIW processor.
300 N: Bruno Cardoso Lopes
301 E: bruno.cardoso@gmail.com
303 W: http://brunocardoso.cc
305 D: Random ARM integrated assembler and assembly parser improvements
306 D: General X86 AVX1 support
309 E: duraid@octopus.com.au
310 W: http://kinoko.c.u-tokyo.ac.jp/~duraid/
311 D: IA64 backend, BigBlock register allocator
314 E: rjmccall@apple.com
315 D: Clang semantic analysis and IR generation
318 E: michael.mccracken@gmail.com
319 D: Line number support for llvmgcc
321 N: Vladimir Merzliakov
323 D: Test suite fixes for FreeBSD
327 D: Added STI Cell SPU backend.
331 D: Support for implicit TLS model used with MS VC runtime
332 D: Dumping of Win64 EH structures
336 E: geek4civic@gmail.com
337 E: chapuni@hf.rim.or.jp
338 D: Maintaining the Git monorepo
339 W: https://github.com/llvm-project/
342 N: Edward O'Callaghan
343 E: eocallaghan@auroraux.org
344 W: http://www.auroraux.org
345 D: Add Clang support with various other improvements to utils/NewNightlyTest.pl
346 D: Fix and maintain Solaris & AuroraUX support for llvm, various build warnings
347 D: and error clean ups.
351 D: Visual C++ compatibility fixes
353 N: Jakob Stoklund Olesen
355 D: Machine code verifier
357 D: Fast register allocator
358 D: Greedy register allocator
365 E: piotr.padlewski@gmail.com
366 D: !invariant.group metadata and other intrinsics for devirtualization in clang
370 D: LTO tool, PassManager rewrite, Loop Pass Manager, Loop Rotate
371 D: GCC PCH Integration (llvm-gcc), llvm-gcc improvements
372 D: Optimizer improvements, Loop Index Split
375 E: apazos@codeaurora.org
376 D: Fixes and improvements to the AArch64 backend
379 E: peckw@wesleypeck.com
380 W: http://wesleypeck.com/
381 D: MicroBlaze backend
384 E: pichet2000@gmail.com
392 W: http://vladimir_prus.blogspot.com
394 D: Made inst_iterator behave like a proper iterator, LowerConstantExprs pass
397 E: kalle.rasikila@nokia.com
398 D: Some bugfixes to CellSPU
402 D: Cmake dependency chain and various bug fixes
405 E: alexr@leftfield.org
407 D: ARM calling conventions rewrite, hard float support
410 E: mcrosier@codeaurora.org
412 D: AArch64 fast instruction selection pass
413 D: Fixes and improvements to the ARM fast-isel pass
414 D: Fixes and improvements to the AArch64 backend
417 E: nadav.rotem@me.com
418 D: X86 code generation improvements, Loop Vectorizer, SLP Vectorizer
421 E: roman@codedgers.com
427 D: Ada support in llvm-gcc
429 D: Exception handling improvements
430 D: Type legalizer rewrite
434 D: Graph coloring register allocator for the Sparc64 backend
436 N: Arnold Schwaighofer
437 E: arnold.schwaighofer@gmail.com
438 D: Tail call optimization for the x86 backend
442 D: Miscellaneous bug fixes
445 E: ashukla@cs.uiuc.edu
448 N: Michael J. Spencer
449 E: bigcheesegs@gmail.com
450 D: Shepherding Windows COFF support into MC.
451 D: Lots of Windows stuff.
454 E: rspencer@reidspencer.com
455 W: http://reidspencer.com/
456 D: Lots of stuff, see: http://wiki.llvm.org/index.php/User:Reid
460 W: http://atoker.com/
461 D: C++ frontend next generation standards implementation
464 E: craig.topper@gmail.com
465 D: X86 codegen and disassembler improvements. AVX2 support.
468 E: edwintorok@gmail.com
469 D: Miscellaneous bug fixes
473 D: C++ bugs filed, and C++ front-end bug fixes.
477 D: Instruction Scheduling, ...
479 N: Lauro Ramos Venancio
480 E: lauro.venancio@indt.org.br
481 D: ARM backend improvements
482 D: Thread Local Storage implementation
486 E: isanbard@gmail.com
487 D: Release manager, IR Linker, LTO
491 E: bob.wilson@acm.org
492 D: Advanced SIMD (NEON) support in the ARM backend.