lib/Target/AMDGPU/AMDGPU.h

   1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 /// \file
   9 //===----------------------------------------------------------------------===//
  10
  11 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
  12 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
  13
  14 #include "llvm/Target/TargetMachine.h"
  15
  16 namespace llvm {
  17
  18 class AMDGPUTargetMachine;
  19 class FunctionPass;
  20 class GCNTargetMachine;
  21 class ModulePass;
  22 class Pass;
  23 class Target;
  24 class TargetMachine;
  25 class TargetOptions;
  26 class PassRegistry;
  27 class Module;
  28
  29 // R600 Passes
  30 FunctionPass *createR600VectorRegMerger();
  31 FunctionPass *createR600ExpandSpecialInstrsPass();
  32 FunctionPass *createR600EmitClauseMarkers();
  33 FunctionPass *createR600ClauseMergePass();
  34 FunctionPass *createR600Packetizer();
  35 FunctionPass *createR600ControlFlowFinalizer();
  36 FunctionPass *createAMDGPUCFGStructurizerPass();
  37 FunctionPass *createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel);
  38
  39 // SI Passes
  40 FunctionPass *createSIAnnotateControlFlowPass();
  41 FunctionPass *createSIFoldOperandsPass();
  42 FunctionPass *createSIPeepholeSDWAPass();
  43 FunctionPass *createSILowerI1CopiesPass();
  44 FunctionPass *createSIShrinkInstructionsPass();
  45 FunctionPass *createSILoadStoreOptimizerPass();
  46 FunctionPass *createSIWholeQuadModePass();
  47 FunctionPass *createSIFixControlFlowLiveIntervalsPass();
  48 FunctionPass *createSIOptimizeExecMaskingPreRAPass();
  49 FunctionPass *createSIFixSGPRCopiesPass();
  50 FunctionPass *createSIMemoryLegalizerPass();
  51 FunctionPass *createSIDebuggerInsertNopsPass();
  52 FunctionPass *createSIInsertWaitcntsPass();
  53 FunctionPass *createSIFixWWMLivenessPass();
  54 FunctionPass *createSIFormMemoryClausesPass();
  55 FunctionPass *createAMDGPUSimplifyLibCallsPass(const TargetOptions &);
  56 FunctionPass *createAMDGPUUseNativeCallsPass();
  57 FunctionPass *createAMDGPUCodeGenPreparePass();
  58 FunctionPass *createAMDGPUMachineCFGStructurizerPass();
  59 FunctionPass *createAMDGPURewriteOutArgumentsPass();
  60
  61 void initializeAMDGPUDAGToDAGISelPass(PassRegistry&);
  62
  63 void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry&);
  64 extern char &AMDGPUMachineCFGStructurizerID;
  65
  66 void initializeAMDGPUAlwaysInlinePass(PassRegistry&);
  67
  68 Pass *createAMDGPUAnnotateKernelFeaturesPass();
  69 void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &);
  70 extern char &AMDGPUAnnotateKernelFeaturesID;
  71
  72 ModulePass *createAMDGPULowerIntrinsicsPass();
  73 void initializeAMDGPULowerIntrinsicsPass(PassRegistry &);
  74 extern char &AMDGPULowerIntrinsicsID;
  75
  76 FunctionPass *createAMDGPULowerKernelArgumentsPass();
  77 void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &);
  78 extern char &AMDGPULowerKernelArgumentsID;
  79
  80 ModulePass *createAMDGPULowerKernelAttributesPass();
  81 void initializeAMDGPULowerKernelAttributesPass(PassRegistry &);
  82 extern char &AMDGPULowerKernelAttributesID;
  83
  84 void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &);
  85 extern char &AMDGPURewriteOutArgumentsID;
  86
  87 void initializeR600ClauseMergePassPass(PassRegistry &);
  88 extern char &R600ClauseMergePassID;
  89
  90 void initializeR600ControlFlowFinalizerPass(PassRegistry &);
  91 extern char &R600ControlFlowFinalizerID;
  92
  93 void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &);
  94 extern char &R600ExpandSpecialInstrsPassID;
  95
  96 void initializeR600VectorRegMergerPass(PassRegistry &);
  97 extern char &R600VectorRegMergerID;
  98
  99 void initializeR600PacketizerPass(PassRegistry &);
 100 extern char &R600PacketizerID;
 101
 102 void initializeSIFoldOperandsPass(PassRegistry &);
 103 extern char &SIFoldOperandsID;
 104
 105 void initializeSIPeepholeSDWAPass(PassRegistry &);
 106 extern char &SIPeepholeSDWAID;
 107
 108 void initializeSIShrinkInstructionsPass(PassRegistry&);
 109 extern char &SIShrinkInstructionsID;
 110
 111 void initializeSIFixSGPRCopiesPass(PassRegistry &);
 112 extern char &SIFixSGPRCopiesID;
 113
 114 void initializeSIFixVGPRCopiesPass(PassRegistry &);
 115 extern char &SIFixVGPRCopiesID;
 116
 117 void initializeSILowerI1CopiesPass(PassRegistry &);
 118 extern char &SILowerI1CopiesID;
 119
 120 void initializeSILoadStoreOptimizerPass(PassRegistry &);
 121 extern char &SILoadStoreOptimizerID;
 122
 123 void initializeSIWholeQuadModePass(PassRegistry &);
 124 extern char &SIWholeQuadModeID;
 125
 126 void initializeSILowerControlFlowPass(PassRegistry &);
 127 extern char &SILowerControlFlowID;
 128
 129 void initializeSIInsertSkipsPass(PassRegistry &);
 130 extern char &SIInsertSkipsPassID;
 131
 132 void initializeSIOptimizeExecMaskingPass(PassRegistry &);
 133 extern char &SIOptimizeExecMaskingID;
 134
 135 void initializeSIFixWWMLivenessPass(PassRegistry &);
 136 extern char &SIFixWWMLivenessID;
 137
 138 void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &);
 139 extern char &AMDGPUSimplifyLibCallsID;
 140
 141 void initializeAMDGPUUseNativeCallsPass(PassRegistry &);
 142 extern char &AMDGPUUseNativeCallsID;
 143
 144 void initializeAMDGPUPerfHintAnalysisPass(PassRegistry &);
 145 extern char &AMDGPUPerfHintAnalysisID;
 146
 147 // Passes common to R600 and SI
 148 FunctionPass *createAMDGPUPromoteAlloca();
 149 void initializeAMDGPUPromoteAllocaPass(PassRegistry&);
 150 extern char &AMDGPUPromoteAllocaID;
 151
 152 Pass *createAMDGPUStructurizeCFGPass();
 153 FunctionPass *createAMDGPUISelDag(
 154   TargetMachine *TM = nullptr,
 155   CodeGenOpt::Level OptLevel = CodeGenOpt::Default);
 156 ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true);
 157 ModulePass *createR600OpenCLImageTypeLoweringPass();
 158 FunctionPass *createAMDGPUAnnotateUniformValues();
 159
 160 ModulePass* createAMDGPUUnifyMetadataPass();
 161 void initializeAMDGPUUnifyMetadataPass(PassRegistry&);
 162 extern char &AMDGPUUnifyMetadataID;
 163
 164 void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry&);
 165 extern char &SIOptimizeExecMaskingPreRAID;
 166
 167 void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&);
 168 extern char &AMDGPUAnnotateUniformValuesPassID;
 169
 170 void initializeAMDGPUCodeGenPreparePass(PassRegistry&);
 171 extern char &AMDGPUCodeGenPrepareID;
 172
 173 void initializeSIAnnotateControlFlowPass(PassRegistry&);
 174 extern char &SIAnnotateControlFlowPassID;
 175
 176 void initializeSIMemoryLegalizerPass(PassRegistry&);
 177 extern char &SIMemoryLegalizerID;
 178
 179 void initializeSIDebuggerInsertNopsPass(PassRegistry&);
 180 extern char &SIDebuggerInsertNopsID;
 181
 182 void initializeSIInsertWaitcntsPass(PassRegistry&);
 183 extern char &SIInsertWaitcntsID;
 184
 185 void initializeSIFormMemoryClausesPass(PassRegistry&);
 186 extern char &SIFormMemoryClausesID;
 187
 188 void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry&);
 189 extern char &AMDGPUUnifyDivergentExitNodesID;
 190
 191 ImmutablePass *createAMDGPUAAWrapperPass();
 192 void initializeAMDGPUAAWrapperPassPass(PassRegistry&);
 193
 194 void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &);
 195
 196 Pass *createAMDGPUFunctionInliningPass();
 197 void initializeAMDGPUInlinerPass(PassRegistry&);
 198
 199 ModulePass *createAMDGPUOpenCLEnqueuedBlockLoweringPass();
 200 void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &);
 201 extern char &AMDGPUOpenCLEnqueuedBlockLoweringID;
 202
 203 Target &getTheAMDGPUTarget();
 204 Target &getTheGCNTarget();
 205
 206 namespace AMDGPU {
 207 enum TargetIndex {
 208   TI_CONSTDATA_START,
 209   TI_SCRATCH_RSRC_DWORD0,
 210   TI_SCRATCH_RSRC_DWORD1,
 211   TI_SCRATCH_RSRC_DWORD2,
 212   TI_SCRATCH_RSRC_DWORD3
 213 };
 214 }
 215
 216 } // End namespace llvm
 217
 218 /// OpenCL uses address spaces to differentiate between
 219 /// various memory regions on the hardware. On the CPU
 220 /// all of the address spaces point to the same memory,
 221 /// however on the GPU, each address space points to
 222 /// a separate piece of memory that is unique from other
 223 /// memory locations.
 224 struct AMDGPUAS {
 225   // The following address space values depend on the triple environment.
 226   unsigned PRIVATE_ADDRESS;  ///< Address space for private memory.
 227   unsigned FLAT_ADDRESS;     ///< Address space for flat memory.
 228   unsigned REGION_ADDRESS;   ///< Address space for region memory.
 229
 230   enum : unsigned {
 231     // The maximum value for flat, generic, local, private, constant and region.
 232     MAX_AMDGPU_ADDRESS = 6,
 233
 234     GLOBAL_ADDRESS = 1,   ///< Address space for global memory (RAT0, VTX0).
 235     CONSTANT_ADDRESS = 4, ///< Address space for constant memory (VTX2)
 236     LOCAL_ADDRESS = 3,    ///< Address space for local memory.
 237
 238     CONSTANT_ADDRESS_32BIT = 6, ///< Address space for 32-bit constant memory
 239
 240     /// Address space for direct addressible parameter memory (CONST0)
 241     PARAM_D_ADDRESS = 6,
 242     /// Address space for indirect addressible parameter memory (VTX1)
 243     PARAM_I_ADDRESS = 7,
 244
 245     // Do not re-order the CONSTANT_BUFFER_* enums.  Several places depend on
 246     // this order to be able to dynamically index a constant buffer, for
 247     // example:
 248     //
 249     // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx
 250
 251     CONSTANT_BUFFER_0 = 8,
 252     CONSTANT_BUFFER_1 = 9,
 253     CONSTANT_BUFFER_2 = 10,
 254     CONSTANT_BUFFER_3 = 11,
 255     CONSTANT_BUFFER_4 = 12,
 256     CONSTANT_BUFFER_5 = 13,
 257     CONSTANT_BUFFER_6 = 14,
 258     CONSTANT_BUFFER_7 = 15,
 259     CONSTANT_BUFFER_8 = 16,
 260     CONSTANT_BUFFER_9 = 17,
 261     CONSTANT_BUFFER_10 = 18,
 262     CONSTANT_BUFFER_11 = 19,
 263     CONSTANT_BUFFER_12 = 20,
 264     CONSTANT_BUFFER_13 = 21,
 265     CONSTANT_BUFFER_14 = 22,
 266     CONSTANT_BUFFER_15 = 23,
 267
 268     // Some places use this if the address space can't be determined.
 269     UNKNOWN_ADDRESS_SPACE = ~0u,
 270   };
 271 };
 272
 273 namespace llvm {
 274 namespace AMDGPU {
 275 AMDGPUAS getAMDGPUAS(const Module &M);
 276 AMDGPUAS getAMDGPUAS(const TargetMachine &TM);
 277 AMDGPUAS getAMDGPUAS(Triple T);
 278 } // namespace AMDGPU
 279 } // namespace llvm
 280
 281 #endif