lib/Target/AMDGPU/Android.mk

   1 LOCAL_PATH := $(call my-dir)
   2
   3 amdgpu_codegen_TBLGEN_TABLES70 := \
   4   AMDGPUGenRegisterInfo.inc \
   5   AMDGPUGenInstrInfo.inc \
   6   AMDGPUGenDAGISel.inc  \
   7   AMDGPUGenSubtargetInfo.inc \
   8   AMDGPUGenMCCodeEmitter.inc \
   9   AMDGPUGenCallingConv.inc \
  10   AMDGPUGenIntrinsicEnums.inc \
  11   AMDGPUGenIntrinsicImpl.inc \
  12   AMDGPUGenAsmWriter.inc \
  13   AMDGPUGenAsmMatcher.inc \
  14   AMDGPUGenDisassemblerTables.inc \
  15   AMDGPUGenMCPseudoLowering.inc \
  16   AMDGPUGenSearchableTables.inc \
  17   AMDGPUGenGlobalISel.inc \
  18   R600GenAsmWriter.inc \
  19   R600GenCallingConv.inc \
  20   R600GenDAGISel.inc \
  21   R600GenDFAPacketizer.inc \
  22   R600GenInstrInfo.inc \
  23   R600GenMCCodeEmitter.inc \
  24   R600GenRegisterInfo.inc \
  25   R600GenSubtargetInfo.inc
  26
  27 amdgpu_codegen_SRC_FILES := \
  28   AMDGPUAliasAnalysis.cpp \
  29   AMDGPUAlwaysInlinePass.cpp \
  30   AMDGPUAnnotateKernelFeatures.cpp \
  31   AMDGPUAnnotateUniformValues.cpp \
  32   AMDGPUArgumentUsageInfo.cpp \
  33   AMDGPUAsmPrinter.cpp \
  34   AMDGPUAtomicOptimizer.cpp \
  35   AMDGPUCodeGenPrepare.cpp \
  36   AMDGPUFixFunctionBitcasts.cpp \
  37   AMDGPUFrameLowering.cpp \
  38   AMDGPUHSAMetadataStreamer.cpp \
  39   AMDGPUInstrInfo.cpp \
  40   AMDGPUIntrinsicInfo.cpp \
  41   AMDGPUISelDAGToDAG.cpp \
  42   AMDGPUISelLowering.cpp \
  43   AMDGPULibCalls.cpp \
  44   AMDGPULibFunc.cpp \
  45   AMDGPULowerIntrinsics.cpp \
  46   AMDGPULowerKernelArguments.cpp \
  47   AMDGPULowerKernelAttributes.cpp \
  48   AMDGPUMachineCFGStructurizer.cpp \
  49   AMDGPUMachineFunction.cpp \
  50   AMDGPUMachineModuleInfo.cpp \
  51   AMDGPUMacroFusion.cpp \
  52   AMDGPUMCInstLower.cpp \
  53   AMDGPUOpenCLEnqueuedBlockLowering.cpp \
  54   AMDGPUPromoteAlloca.cpp \
  55   AMDGPURegAsmNames.inc.cpp \
  56   AMDGPURegisterInfo.cpp \
  57   AMDGPURewriteOutArguments.cpp \
  58   AMDGPUSubtarget.cpp \
  59   AMDGPUTargetMachine.cpp \
  60   AMDGPUTargetObjectFile.cpp \
  61   AMDGPUTargetTransformInfo.cpp \
  62   AMDGPUUnifyDivergentExitNodes.cpp \
  63   AMDGPUUnifyMetadata.cpp \
  64   AMDGPUInline.cpp \
  65   AMDGPUPerfHintAnalysis.cpp \
  66   AMDILCFGStructurizer.cpp \
  67   GCNHazardRecognizer.cpp \
  68   GCNIterativeScheduler.cpp \
  69   GCNMinRegStrategy.cpp \
  70   GCNRegPressure.cpp \
  71   GCNSchedStrategy.cpp \
  72   R600AsmPrinter.cpp \
  73   R600ClauseMergePass.cpp \
  74   R600ControlFlowFinalizer.cpp \
  75   R600EmitClauseMarkers.cpp \
  76   R600ExpandSpecialInstrs.cpp \
  77   R600FrameLowering.cpp \
  78   R600InstrInfo.cpp \
  79   R600ISelLowering.cpp \
  80   R600MachineFunctionInfo.cpp \
  81   R600MachineScheduler.cpp \
  82   R600OpenCLImageTypeLoweringPass.cpp \
  83   R600OptimizeVectorRegisters.cpp \
  84   R600Packetizer.cpp \
  85   R600RegisterInfo.cpp \
  86   SIAddIMGInit.cpp \
  87   SIAnnotateControlFlow.cpp \
  88   SIDebuggerInsertNops.cpp \
  89   SIFixSGPRCopies.cpp \
  90   SIFixupVectorISel.cpp \
  91   SIFixVGPRCopies.cpp \
  92   SIFixWWMLiveness.cpp \
  93   SIFoldOperands.cpp \
  94   SIFormMemoryClauses.cpp \
  95   SIFrameLowering.cpp \
  96   SIInsertSkips.cpp \
  97   SIInsertWaitcnts.cpp \
  98   SIInstrInfo.cpp \
  99   SIISelLowering.cpp \
 100   SILoadStoreOptimizer.cpp \
 101   SILowerControlFlow.cpp \
 102   SILowerI1Copies.cpp \
 103   SIMachineFunctionInfo.cpp \
 104   SIMachineScheduler.cpp \
 105   SIMemoryLegalizer.cpp \
 106   SIOptimizeExecMasking.cpp \
 107   SIOptimizeExecMaskingPreRA.cpp \
 108   SIPeepholeSDWA.cpp \
 109   SIRegisterInfo.cpp \
 110   SIShrinkInstructions.cpp \
 111   SIWholeQuadMode.cpp \
 112   GCNILPSched.cpp \
 113   GCNDPPCombine.cpp \
 114   SIModeRegister.cpp
 115
 116 ifeq ($(FORCE_BUILD_LLVM_GLOBAL_ISEL),true)
 117 amdgpu_codegen_TBLGEN_TABLES70 += \
 118   AMDGPUGenRegisterBank.inc
 119
 120 amdgpu_codegen_SRC_FILES += \
 121   AMDGPUCallLowering.cpp \
 122   AMDGPUInstructionSelector.cpp \
 123   AMDGPULegalizerInfo.cpp \
 124   AMDGPURegisterBankInfo.cpp
 125 endif
 126
 127 # For the host
 128 # =====================================================
 129 include $(CLEAR_VARS)
 130 include $(CLEAR_TBLGEN_VARS70)
 131
 132 TBLGEN_TABLES70 := $(amdgpu_codegen_TBLGEN_TABLES70)
 133
 134 LOCAL_SRC_FILES := $(amdgpu_codegen_SRC_FILES)
 135
 136 LOCAL_MODULE := libLLVM70AMDGPUCodeGen
 137
 138 LOCAL_MODULE_HOST_OS := darwin linux windows
 139
 140 include $(LLVM70_HOST_BUILD_MK)
 141 include $(LLVM70_TBLGEN_RULES_MK)
 142 include $(LLVM70_GEN_ATTRIBUTES_MK)
 143 include $(LLVM70_GEN_INTRINSICS_MK)
 144 include $(BUILD_HOST_STATIC_LIBRARY)
 145
 146 # For the device only
 147 # =====================================================
 148 ifneq (true,$(DISABLE_LLVM_DEVICE_BUILDS))
 149 include $(CLEAR_VARS)
 150 include $(CLEAR_TBLGEN_VARS70)
 151
 152 TBLGEN_TABLES70 := $(amdgpu_codegen_TBLGEN_TABLES70)
 153
 154 LOCAL_SRC_FILES := $(amdgpu_codegen_SRC_FILES)
 155
 156 LOCAL_MODULE := libLLVM70AMDGPUCodeGen
 157
 158 include $(LLVM70_DEVICE_BUILD_MK)
 159 include $(LLVM70_TBLGEN_RULES_MK)
 160 include $(LLVM70_GEN_ATTRIBUTES_MK)
 161 include $(LLVM70_GEN_INTRINSICS_MK)
 162 include $(BUILD_STATIC_LIBRARY)
 163 endif