OSDN Git Service

CLEAR_TBLGEN_VARS to CLEAR_TBLGEN_VARS70
[android-x86/external-llvm.git] / lib / Target / AMDGPU / Android.mk
1 LOCAL_PATH := $(call my-dir)
2
3 amdgpu_codegen_TBLGEN_TABLES70 := \
4   AMDGPUGenRegisterInfo.inc \
5   AMDGPUGenInstrInfo.inc \
6   AMDGPUGenDAGISel.inc  \
7   AMDGPUGenSubtargetInfo.inc \
8   AMDGPUGenMCCodeEmitter.inc \
9   AMDGPUGenCallingConv.inc \
10   AMDGPUGenIntrinsics.inc \
11   AMDGPUGenDFAPacketizer.inc \
12   AMDGPUGenAsmWriter.inc \
13   AMDGPUGenAsmMatcher.inc \
14   AMDGPUGenDisassemblerTables.inc \
15   AMDGPUGenMCPseudoLowering.inc
16
17 amdgpu_codegen_SRC_FILES := \
18   AMDILCFGStructurizer.cpp \
19   AMDGPUAliasAnalysis.cpp \
20   AMDGPUAlwaysInlinePass.cpp \
21   AMDGPUAnnotateKernelFeatures.cpp \
22   AMDGPUAnnotateUniformValues.cpp \
23   AMDGPUAsmPrinter.cpp \
24   AMDGPUCodeGenPrepare.cpp \
25   AMDGPUFrameLowering.cpp \
26   AMDGPUTargetObjectFile.cpp \
27   AMDGPUIntrinsicInfo.cpp \
28   AMDGPUISelDAGToDAG.cpp \
29   AMDGPULowerIntrinsics.cpp \
30   AMDGPUMacroFusion.cpp \
31   AMDGPUMCInstLower.cpp \
32   AMDGPUMachineCFGStructurizer.cpp \
33   AMDGPUMachineFunction.cpp \
34   AMDGPUUnifyMetadata.cpp \
35   AMDGPUOpenCLImageTypeLoweringPass.cpp \
36   AMDGPUSubtarget.cpp \
37   AMDGPUTargetMachine.cpp \
38   AMDGPUTargetTransformInfo.cpp \
39   AMDGPUISelLowering.cpp \
40   AMDGPUInstrInfo.cpp \
41   AMDGPUPromoteAlloca.cpp \
42   AMDGPURegAsmNames.inc.cpp \
43   AMDGPURegisterInfo.cpp \
44   AMDGPUUnifyDivergentExitNodes.cpp \
45   GCNHazardRecognizer.cpp \
46   GCNSchedStrategy.cpp \
47   R600ClauseMergePass.cpp \
48   R600ControlFlowFinalizer.cpp \
49   R600EmitClauseMarkers.cpp \
50   R600ExpandSpecialInstrs.cpp \
51   R600FrameLowering.cpp \
52   R600InstrInfo.cpp \
53   R600ISelLowering.cpp \
54   R600MachineFunctionInfo.cpp \
55   R600MachineScheduler.cpp \
56   R600OptimizeVectorRegisters.cpp \
57   R600Packetizer.cpp \
58   R600RegisterInfo.cpp \
59   SIAnnotateControlFlow.cpp \
60   SIDebuggerInsertNops.cpp \
61   SIFixControlFlowLiveIntervals.cpp \
62   SIFixSGPRCopies.cpp \
63   SIFixVGPRCopies.cpp \
64   SIFoldOperands.cpp \
65   SIFrameLowering.cpp \
66   SIInsertSkips.cpp \
67   SIInsertWaits.cpp \
68   SIInsertWaitcnts.cpp \
69   SIInstrInfo.cpp \
70   SIISelLowering.cpp \
71   SILoadStoreOptimizer.cpp \
72   SILowerControlFlow.cpp \
73   SILowerI1Copies.cpp \
74   SIMachineFunctionInfo.cpp \
75   SIMachineScheduler.cpp \
76   SIOptimizeExecMasking.cpp \
77   SIPeepholeSDWA.cpp \
78   SIRegisterInfo.cpp \
79   SIShrinkInstructions.cpp \
80   SIWholeQuadMode.cpp \
81   GCNIterativeScheduler.cpp \
82   GCNMinRegStrategy.cpp \
83   GCNRegPressure.cpp
84
85 ifeq ($(FORCE_BUILD_LLVM_GLOBAL_ISEL),true)
86 amdgpu_codegen_TBLGEN_TABLES70 += \
87   AMDGPUGenRegisterBank.inc
88
89 amdgpu_codegen_SRC_FILES += \
90   AMDGPUCallLowering.cpp \
91   AMDGPUInstructionSelector.cpp \
92   AMDGPULegalizerInfo.cpp \
93   AMDGPURegisterBankInfo.cpp
94 endif
95
96 # For the host
97 # =====================================================
98 include $(CLEAR_VARS)
99 include $(CLEAR_TBLGEN_VARS70)
100
101 TBLGEN_TABLES70 := $(amdgpu_codegen_TBLGEN_TABLES70)
102
103 LOCAL_SRC_FILES := $(amdgpu_codegen_SRC_FILES)
104
105 LOCAL_MODULE := libLLVM70AMDGPUCodeGen
106
107 LOCAL_MODULE_HOST_OS := darwin linux windows
108
109 include $(LLVM70_HOST_BUILD_MK)
110 include $(LLVM70_TBLGEN_RULES_MK)
111 include $(LLVM70_GEN_ATTRIBUTES_MK)
112 include $(LLVM70_GEN_INTRINSICS_MK)
113 include $(BUILD_HOST_STATIC_LIBRARY)
114
115 # For the device only
116 # =====================================================
117 ifneq (true,$(DISABLE_LLVM_DEVICE_BUILDS))
118 include $(CLEAR_VARS)
119 include $(CLEAR_TBLGEN_VARS70)
120
121 TBLGEN_TABLES70 := $(amdgpu_codegen_TBLGEN_TABLES70)
122
123 LOCAL_SRC_FILES := $(amdgpu_codegen_SRC_FILES)
124
125 LOCAL_MODULE := libLLVM70AMDGPUCodeGen
126
127 include $(LLVM70_DEVICE_BUILD_MK)
128 include $(LLVM70_TBLGEN_RULES_MK)
129 include $(LLVM70_GEN_ATTRIBUTES_MK)
130 include $(LLVM70_GEN_INTRINSICS_MK)
131 include $(BUILD_STATIC_LIBRARY)
132 endif