lib/Target/Mips/Disassembler/MipsDisassembler.cpp

   1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file is part of the Mips Disassembler.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Mips.h"
  15 #include "MipsRegisterInfo.h"
  16 #include "MipsSubtarget.h"
  17 #include "llvm/MC/MCContext.h"
  18 #include "llvm/MC/MCDisassembler.h"
  19 #include "llvm/MC/MCFixedLenDisassembler.h"
  20 #include "llvm/MC/MCInst.h"
  21 #include "llvm/MC/MCSubtargetInfo.h"
  22 #include "llvm/Support/MathExtras.h"
  23 #include "llvm/Support/TargetRegistry.h"
  24
  25 using namespace llvm;
  26
  27 #define DEBUG_TYPE "mips-disassembler"
  28
  29 typedef MCDisassembler::DecodeStatus DecodeStatus;
  30
  31 namespace {
  32
  33 class MipsDisassembler : public MCDisassembler {
  34   bool IsMicroMips;
  35   bool IsBigEndian;
  36 public:
  37   MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian)
  38       : MCDisassembler(STI, Ctx),
  39         IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]),
  40         IsBigEndian(IsBigEndian) {}
  41
  42   bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; }
  43   bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; }
  44   bool hasMips32r6() const {
  45     return STI.getFeatureBits()[Mips::FeatureMips32r6];
  46   }
  47
  48   bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; }
  49
  50   bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; }
  51
  52   bool hasCOP3() const {
  53     // Only present in MIPS-I and MIPS-II
  54     return !hasMips32() && !hasMips3();
  55   }
  56
  57   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
  58                               ArrayRef<uint8_t> Bytes, uint64_t Address,
  59                               raw_ostream &VStream,
  60                               raw_ostream &CStream) const override;
  61 };
  62
  63 } // end anonymous namespace
  64
  65 // Forward declare these because the autogenerated code will reference them.
  66 // Definitions are further down.
  67 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
  68                                              unsigned RegNo,
  69                                              uint64_t Address,
  70                                              const void *Decoder);
  71
  72 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
  73                                                  unsigned RegNo,
  74                                                  uint64_t Address,
  75                                                  const void *Decoder);
  76
  77 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
  78                                                unsigned RegNo,
  79                                                uint64_t Address,
  80                                                const void *Decoder);
  81
  82 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
  83                                                    unsigned RegNo,
  84                                                    uint64_t Address,
  85                                                    const void *Decoder);
  86
  87 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
  88                                                     unsigned RegNo,
  89                                                     uint64_t Address,
  90                                                     const void *Decoder);
  91
  92 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
  93                                              unsigned RegNo,
  94                                              uint64_t Address,
  95                                              const void *Decoder);
  96
  97 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
  98                                            unsigned Insn,
  99                                            uint64_t Address,
 100                                            const void *Decoder);
 101
 102 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 103                                             unsigned RegNo,
 104                                             uint64_t Address,
 105                                             const void *Decoder);
 106
 107 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 108                                              unsigned RegNo,
 109                                              uint64_t Address,
 110                                              const void *Decoder);
 111
 112 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 113                                              unsigned RegNo,
 114                                              uint64_t Address,
 115                                              const void *Decoder);
 116
 117 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 118                                            unsigned RegNo,
 119                                            uint64_t Address,
 120                                            const void *Decoder);
 121
 122 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 123                                            unsigned RegNo,
 124                                            uint64_t Address,
 125                                            const void *Decoder);
 126
 127 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
 128                                              uint64_t Address,
 129                                              const void *Decoder);
 130
 131 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
 132                                               unsigned Insn,
 133                                               uint64_t Address,
 134                                               const void *Decoder);
 135
 136 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
 137                                               unsigned RegNo,
 138                                               uint64_t Address,
 139                                               const void *Decoder);
 140
 141 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
 142                                                 unsigned RegNo,
 143                                                 uint64_t Address,
 144                                                 const void *Decoder);
 145
 146 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
 147                                                unsigned RegNo,
 148                                                uint64_t Address,
 149                                                const void *Decoder);
 150
 151 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
 152                                                unsigned RegNo,
 153                                                uint64_t Address,
 154                                                const void *Decoder);
 155
 156 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
 157                                                unsigned RegNo,
 158                                                uint64_t Address,
 159                                                const void *Decoder);
 160
 161 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
 162                                                unsigned RegNo,
 163                                                uint64_t Address,
 164                                                const void *Decoder);
 165
 166 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
 167                                                unsigned RegNo,
 168                                                uint64_t Address,
 169                                                const void *Decoder);
 170
 171 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
 172                                                unsigned RegNo,
 173                                                uint64_t Address,
 174                                                const void *Decoder);
 175
 176 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
 177                                                unsigned RegNo,
 178                                                uint64_t Address,
 179                                                const void *Decoder);
 180
 181 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
 182                                             unsigned RegNo,
 183                                             uint64_t Address,
 184                                             const void *Decoder);
 185
 186 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
 187                                        unsigned Offset,
 188                                        uint64_t Address,
 189                                        const void *Decoder);
 190
 191 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
 192                                      unsigned Insn,
 193                                      uint64_t Address,
 194                                      const void *Decoder);
 195
 196 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
 197                                          unsigned Offset,
 198                                          uint64_t Address,
 199                                          const void *Decoder);
 200
 201 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
 202                                          unsigned Offset,
 203                                          uint64_t Address,
 204                                          const void *Decoder);
 205
 206 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
 207 // shifted left by 1 bit.
 208 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
 209                                           unsigned Offset,
 210                                           uint64_t Address,
 211                                           const void *Decoder);
 212
 213 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is
 214 // shifted left by 1 bit.
 215 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
 216                                            unsigned Offset,
 217                                            uint64_t Address,
 218                                            const void *Decoder);
 219
 220 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
 221 // shifted left by 1 bit.
 222 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
 223                                          unsigned Offset,
 224                                          uint64_t Address,
 225                                          const void *Decoder);
 226
 227 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
 228 // shifted left by 1 bit.
 229 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
 230                                        unsigned Insn,
 231                                        uint64_t Address,
 232                                        const void *Decoder);
 233
 234 static DecodeStatus DecodeMem(MCInst &Inst,
 235                               unsigned Insn,
 236                               uint64_t Address,
 237                               const void *Decoder);
 238
 239 static DecodeStatus DecodeCacheOp(MCInst &Inst,
 240                               unsigned Insn,
 241                               uint64_t Address,
 242                               const void *Decoder);
 243
 244 static DecodeStatus DecodeCacheOpR6(MCInst &Inst,
 245                                     unsigned Insn,
 246                                     uint64_t Address,
 247                                     const void *Decoder);
 248
 249 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
 250                                     unsigned Insn,
 251                                     uint64_t Address,
 252                                     const void *Decoder);
 253
 254 static DecodeStatus DecodeSyncI(MCInst &Inst,
 255                                 unsigned Insn,
 256                                 uint64_t Address,
 257                                 const void *Decoder);
 258
 259 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 260                                     uint64_t Address, const void *Decoder);
 261
 262 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
 263                                     unsigned Insn,
 264                                     uint64_t Address,
 265                                     const void *Decoder);
 266
 267 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
 268                                           unsigned Insn,
 269                                           uint64_t Address,
 270                                           const void *Decoder);
 271
 272 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
 273                                           unsigned Insn,
 274                                           uint64_t Address,
 275                                           const void *Decoder);
 276
 277 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
 278                                                unsigned Insn,
 279                                                uint64_t Address,
 280                                                const void *Decoder);
 281
 282 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 283                                      unsigned Insn,
 284                                      uint64_t Address,
 285                                      const void *Decoder);
 286
 287 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
 288                                      unsigned Insn,
 289                                      uint64_t Address,
 290                                      const void *Decoder);
 291
 292 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
 293                                uint64_t Address,
 294                                const void *Decoder);
 295
 296 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
 297                                uint64_t Address,
 298                                const void *Decoder);
 299
 300 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn,
 301                                uint64_t Address,
 302                                const void *Decoder);
 303
 304 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
 305                                uint64_t Address,
 306                                const void *Decoder);
 307
 308 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
 309                                        unsigned Insn,
 310                                        uint64_t Address,
 311                                        const void *Decoder);
 312
 313 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
 314                                        unsigned Value,
 315                                        uint64_t Address,
 316                                        const void *Decoder);
 317
 318 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
 319                                     unsigned Value,
 320                                     uint64_t Address,
 321                                     const void *Decoder);
 322
 323 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
 324                                   unsigned Value,
 325                                   uint64_t Address,
 326                                   const void *Decoder);
 327
 328 static DecodeStatus DecodeSimm4(MCInst &Inst,
 329                                 unsigned Value,
 330                                 uint64_t Address,
 331                                 const void *Decoder);
 332
 333 static DecodeStatus DecodeSimm16(MCInst &Inst,
 334                                  unsigned Insn,
 335                                  uint64_t Address,
 336                                  const void *Decoder);
 337
 338 // Decode the immediate field of an LSA instruction which
 339 // is off by one.
 340 static DecodeStatus DecodeLSAImm(MCInst &Inst,
 341                                  unsigned Insn,
 342                                  uint64_t Address,
 343                                  const void *Decoder);
 344
 345 static DecodeStatus DecodeInsSize(MCInst &Inst,
 346                                   unsigned Insn,
 347                                   uint64_t Address,
 348                                   const void *Decoder);
 349
 350 static DecodeStatus DecodeExtSize(MCInst &Inst,
 351                                   unsigned Insn,
 352                                   uint64_t Address,
 353                                   const void *Decoder);
 354
 355 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
 356                                      uint64_t Address, const void *Decoder);
 357
 358 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
 359                                      uint64_t Address, const void *Decoder);
 360
 361 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
 362                                   uint64_t Address, const void *Decoder);
 363
 364 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
 365                                     uint64_t Address, const void *Decoder);
 366
 367 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
 368                                    uint64_t Address, const void *Decoder);
 369
 370 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
 371                                      uint64_t Address, const void *Decoder);
 372
 373 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
 374 /// handle.
 375 template <typename InsnType>
 376 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 377                                    const void *Decoder);
 378
 379 template <typename InsnType>
 380 static DecodeStatus
 381 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 382                       const void *Decoder);
 383
 384 template <typename InsnType>
 385 static DecodeStatus
 386 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 387                        const void *Decoder);
 388
 389 template <typename InsnType>
 390 static DecodeStatus
 391 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 392                        const void *Decoder);
 393
 394 template <typename InsnType>
 395 static DecodeStatus
 396 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 397                        const void *Decoder);
 398
 399 template <typename InsnType>
 400 static DecodeStatus
 401 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 402                       const void *Decoder);
 403
 404 template <typename InsnType>
 405 static DecodeStatus
 406 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 407                        const void *Decoder);
 408
 409 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
 410                                          uint64_t Address,
 411                                          const void *Decoder);
 412
 413 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
 414                                            uint64_t Address,
 415                                            const void *Decoder);
 416
 417 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
 418                                        uint64_t Address,
 419                                        const void *Decoder);
 420
 421 namespace llvm {
 422 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
 423               TheMips64elTarget;
 424 }
 425
 426 static MCDisassembler *createMipsDisassembler(
 427                        const Target &T,
 428                        const MCSubtargetInfo &STI,
 429                        MCContext &Ctx) {
 430   return new MipsDisassembler(STI, Ctx, true);
 431 }
 432
 433 static MCDisassembler *createMipselDisassembler(
 434                        const Target &T,
 435                        const MCSubtargetInfo &STI,
 436                        MCContext &Ctx) {
 437   return new MipsDisassembler(STI, Ctx, false);
 438 }
 439
 440 extern "C" void LLVMInitializeMipsDisassembler() {
 441   // Register the disassembler.
 442   TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
 443                                          createMipsDisassembler);
 444   TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
 445                                          createMipselDisassembler);
 446   TargetRegistry::RegisterMCDisassembler(TheMips64Target,
 447                                          createMipsDisassembler);
 448   TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
 449                                          createMipselDisassembler);
 450 }
 451
 452 #include "MipsGenDisassemblerTables.inc"
 453
 454 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
 455   const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D);
 456   const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
 457   return *(RegInfo->getRegClass(RC).begin() + RegNo);
 458 }
 459
 460 template <typename InsnType>
 461 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 462                                    const void *Decoder) {
 463   typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
 464   // The size of the n field depends on the element size
 465   // The register class also depends on this.
 466   InsnType tmp = fieldFromInstruction(insn, 17, 5);
 467   unsigned NSize = 0;
 468   DecodeFN RegDecoder = nullptr;
 469   if ((tmp & 0x18) == 0x00) { // INSVE_B
 470     NSize = 4;
 471     RegDecoder = DecodeMSA128BRegisterClass;
 472   } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
 473     NSize = 3;
 474     RegDecoder = DecodeMSA128HRegisterClass;
 475   } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
 476     NSize = 2;
 477     RegDecoder = DecodeMSA128WRegisterClass;
 478   } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
 479     NSize = 1;
 480     RegDecoder = DecodeMSA128DRegisterClass;
 481   } else
 482     llvm_unreachable("Invalid encoding");
 483
 484   assert(NSize != 0 && RegDecoder != nullptr);
 485
 486   // $wd
 487   tmp = fieldFromInstruction(insn, 6, 5);
 488   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 489     return MCDisassembler::Fail;
 490   // $wd_in
 491   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 492     return MCDisassembler::Fail;
 493   // $n
 494   tmp = fieldFromInstruction(insn, 16, NSize);
 495   MI.addOperand(MCOperand::createImm(tmp));
 496   // $ws
 497   tmp = fieldFromInstruction(insn, 11, 5);
 498   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 499     return MCDisassembler::Fail;
 500   // $n2
 501   MI.addOperand(MCOperand::createImm(0));
 502
 503   return MCDisassembler::Success;
 504 }
 505
 506 template <typename InsnType>
 507 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
 508                                           uint64_t Address,
 509                                           const void *Decoder) {
 510   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 511   // (otherwise we would have matched the ADDI instruction from the earlier
 512   // ISA's instead).
 513   //
 514   // We have:
 515   //    0b001000 sssss ttttt iiiiiiiiiiiiiiii
 516   //      BOVC if rs >= rt
 517   //      BEQZALC if rs == 0 && rt != 0
 518   //      BEQC if rs < rt && rs != 0
 519
 520   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 521   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 522   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 523   bool HasRs = false;
 524
 525   if (Rs >= Rt) {
 526     MI.setOpcode(Mips::BOVC);
 527     HasRs = true;
 528   } else if (Rs != 0 && Rs < Rt) {
 529     MI.setOpcode(Mips::BEQC);
 530     HasRs = true;
 531   } else
 532     MI.setOpcode(Mips::BEQZALC);
 533
 534   if (HasRs)
 535     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 536                                        Rs)));
 537
 538   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 539                                      Rt)));
 540   MI.addOperand(MCOperand::createImm(Imm));
 541
 542   return MCDisassembler::Success;
 543 }
 544
 545 template <typename InsnType>
 546 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
 547                                            uint64_t Address,
 548                                            const void *Decoder) {
 549   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 550   // (otherwise we would have matched the ADDI instruction from the earlier
 551   // ISA's instead).
 552   //
 553   // We have:
 554   //    0b011000 sssss ttttt iiiiiiiiiiiiiiii
 555   //      BNVC if rs >= rt
 556   //      BNEZALC if rs == 0 && rt != 0
 557   //      BNEC if rs < rt && rs != 0
 558
 559   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 560   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 561   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 562   bool HasRs = false;
 563
 564   if (Rs >= Rt) {
 565     MI.setOpcode(Mips::BNVC);
 566     HasRs = true;
 567   } else if (Rs != 0 && Rs < Rt) {
 568     MI.setOpcode(Mips::BNEC);
 569     HasRs = true;
 570   } else
 571     MI.setOpcode(Mips::BNEZALC);
 572
 573   if (HasRs)
 574     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 575                                        Rs)));
 576
 577   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 578                                      Rt)));
 579   MI.addOperand(MCOperand::createImm(Imm));
 580
 581   return MCDisassembler::Success;
 582 }
 583
 584 template <typename InsnType>
 585 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
 586                                            uint64_t Address,
 587                                            const void *Decoder) {
 588   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 589   // (otherwise we would have matched the BLEZL instruction from the earlier
 590   // ISA's instead).
 591   //
 592   // We have:
 593   //    0b010110 sssss ttttt iiiiiiiiiiiiiiii
 594   //      Invalid if rs == 0
 595   //      BLEZC   if rs == 0  && rt != 0
 596   //      BGEZC   if rs == rt && rt != 0
 597   //      BGEC    if rs != rt && rs != 0  && rt != 0
 598
 599   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 600   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 601   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 602   bool HasRs = false;
 603
 604   if (Rt == 0)
 605     return MCDisassembler::Fail;
 606   else if (Rs == 0)
 607     MI.setOpcode(Mips::BLEZC);
 608   else if (Rs == Rt)
 609     MI.setOpcode(Mips::BGEZC);
 610   else {
 611     HasRs = true;
 612     MI.setOpcode(Mips::BGEC);
 613   }
 614
 615   if (HasRs)
 616     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 617                                        Rs)));
 618
 619   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 620                                      Rt)));
 621
 622   MI.addOperand(MCOperand::createImm(Imm));
 623
 624   return MCDisassembler::Success;
 625 }
 626
 627 template <typename InsnType>
 628 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
 629                                            uint64_t Address,
 630                                            const void *Decoder) {
 631   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 632   // (otherwise we would have matched the BGTZL instruction from the earlier
 633   // ISA's instead).
 634   //
 635   // We have:
 636   //    0b010111 sssss ttttt iiiiiiiiiiiiiiii
 637   //      Invalid if rs == 0
 638   //      BGTZC   if rs == 0  && rt != 0
 639   //      BLTZC   if rs == rt && rt != 0
 640   //      BLTC    if rs != rt && rs != 0  && rt != 0
 641
 642   bool HasRs = false;
 643
 644   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 645   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 646   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 647
 648   if (Rt == 0)
 649     return MCDisassembler::Fail;
 650   else if (Rs == 0)
 651     MI.setOpcode(Mips::BGTZC);
 652   else if (Rs == Rt)
 653     MI.setOpcode(Mips::BLTZC);
 654   else {
 655     MI.setOpcode(Mips::BLTC);
 656     HasRs = true;
 657   }
 658
 659   if (HasRs)
 660     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 661                                               Rs)));
 662
 663   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 664                                      Rt)));
 665
 666   MI.addOperand(MCOperand::createImm(Imm));
 667
 668   return MCDisassembler::Success;
 669 }
 670
 671 template <typename InsnType>
 672 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
 673                                           uint64_t Address,
 674                                           const void *Decoder) {
 675   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 676   // (otherwise we would have matched the BGTZ instruction from the earlier
 677   // ISA's instead).
 678   //
 679   // We have:
 680   //    0b000111 sssss ttttt iiiiiiiiiiiiiiii
 681   //      BGTZ    if rt == 0
 682   //      BGTZALC if rs == 0 && rt != 0
 683   //      BLTZALC if rs != 0 && rs == rt
 684   //      BLTUC   if rs != 0 && rs != rt
 685
 686   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 687   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 688   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 689   bool HasRs = false;
 690   bool HasRt = false;
 691
 692   if (Rt == 0) {
 693     MI.setOpcode(Mips::BGTZ);
 694     HasRs = true;
 695   } else if (Rs == 0) {
 696     MI.setOpcode(Mips::BGTZALC);
 697     HasRt = true;
 698   } else if (Rs == Rt) {
 699     MI.setOpcode(Mips::BLTZALC);
 700     HasRs = true;
 701   } else {
 702     MI.setOpcode(Mips::BLTUC);
 703     HasRs = true;
 704     HasRt = true;
 705   }
 706
 707   if (HasRs)
 708     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 709                                        Rs)));
 710
 711   if (HasRt)
 712     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 713                                        Rt)));
 714
 715   MI.addOperand(MCOperand::createImm(Imm));
 716
 717   return MCDisassembler::Success;
 718 }
 719
 720 template <typename InsnType>
 721 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
 722                                            uint64_t Address,
 723                                            const void *Decoder) {
 724   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 725   // (otherwise we would have matched the BLEZL instruction from the earlier
 726   // ISA's instead).
 727   //
 728   // We have:
 729   //    0b000110 sssss ttttt iiiiiiiiiiiiiiii
 730   //      Invalid   if rs == 0
 731   //      BLEZALC   if rs == 0  && rt != 0
 732   //      BGEZALC   if rs == rt && rt != 0
 733   //      BGEUC     if rs != rt && rs != 0  && rt != 0
 734
 735   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 736   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 737   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 738   bool HasRs = false;
 739
 740   if (Rt == 0)
 741     return MCDisassembler::Fail;
 742   else if (Rs == 0)
 743     MI.setOpcode(Mips::BLEZALC);
 744   else if (Rs == Rt)
 745     MI.setOpcode(Mips::BGEZALC);
 746   else {
 747     HasRs = true;
 748     MI.setOpcode(Mips::BGEUC);
 749   }
 750
 751   if (HasRs)
 752     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 753                                        Rs)));
 754   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 755                                      Rt)));
 756
 757   MI.addOperand(MCOperand::createImm(Imm));
 758
 759   return MCDisassembler::Success;
 760 }
 761
 762 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted
 763 /// according to the given endianess.
 764 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
 765                                       uint64_t &Size, uint32_t &Insn,
 766                                       bool IsBigEndian) {
 767   // We want to read exactly 2 Bytes of data.
 768   if (Bytes.size() < 2) {
 769     Size = 0;
 770     return MCDisassembler::Fail;
 771   }
 772
 773   if (IsBigEndian) {
 774     Insn = (Bytes[0] << 8) | Bytes[1];
 775   } else {
 776     Insn = (Bytes[1] << 8) | Bytes[0];
 777   }
 778
 779   return MCDisassembler::Success;
 780 }
 781
 782 /// Read four bytes from the ArrayRef and return 32 bit word sorted
 783 /// according to the given endianess
 784 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
 785                                       uint64_t &Size, uint32_t &Insn,
 786                                       bool IsBigEndian, bool IsMicroMips) {
 787   // We want to read exactly 4 Bytes of data.
 788   if (Bytes.size() < 4) {
 789     Size = 0;
 790     return MCDisassembler::Fail;
 791   }
 792
 793   // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
 794   // always precede the low 16 bits in the instruction stream (that is, they
 795   // are placed at lower addresses in the instruction stream).
 796   //
 797   // microMIPS byte ordering:
 798   //   Big-endian:    0 | 1 | 2 | 3
 799   //   Little-endian: 1 | 0 | 3 | 2
 800
 801   if (IsBigEndian) {
 802     // Encoded as a big-endian 32-bit word in the stream.
 803     Insn =
 804         (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
 805   } else {
 806     if (IsMicroMips) {
 807       Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
 808              (Bytes[1] << 24);
 809     } else {
 810       Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
 811              (Bytes[3] << 24);
 812     }
 813   }
 814
 815   return MCDisassembler::Success;
 816 }
 817
 818 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
 819                                               ArrayRef<uint8_t> Bytes,
 820                                               uint64_t Address,
 821                                               raw_ostream &VStream,
 822                                               raw_ostream &CStream) const {
 823   uint32_t Insn;
 824   DecodeStatus Result;
 825
 826   if (IsMicroMips) {
 827     Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
 828
 829     DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
 830     // Calling the auto-generated decoder function.
 831     Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
 832                                this, STI);
 833     if (Result != MCDisassembler::Fail) {
 834       Size = 2;
 835       return Result;
 836     }
 837
 838     Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
 839     if (Result == MCDisassembler::Fail)
 840       return MCDisassembler::Fail;
 841
 842     if (hasMips32r6()) {
 843       DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n");
 844       // Calling the auto-generated decoder function.
 845       Result = decodeInstruction(DecoderTableMicroMips32r632, Instr, Insn, Address,
 846                                  this, STI);
 847     } else {
 848       DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
 849       // Calling the auto-generated decoder function.
 850       Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
 851                                  this, STI);
 852     }
 853     if (Result != MCDisassembler::Fail) {
 854       Size = 4;
 855       return Result;
 856     }
 857     return MCDisassembler::Fail;
 858   }
 859
 860   Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
 861   if (Result == MCDisassembler::Fail)
 862     return MCDisassembler::Fail;
 863
 864   if (hasCOP3()) {
 865     DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
 866     Result =
 867         decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
 868     if (Result != MCDisassembler::Fail) {
 869       Size = 4;
 870       return Result;
 871     }
 872   }
 873
 874   if (hasMips32r6() && isGP64()) {
 875     DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
 876     Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
 877                                Address, this, STI);
 878     if (Result != MCDisassembler::Fail) {
 879       Size = 4;
 880       return Result;
 881     }
 882   }
 883
 884   if (hasMips32r6()) {
 885     DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
 886     Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
 887                                Address, this, STI);
 888     if (Result != MCDisassembler::Fail) {
 889       Size = 4;
 890       return Result;
 891     }
 892   }
 893
 894   if (hasCnMips()) {
 895     DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n");
 896     Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn,
 897                                Address, this, STI);
 898     if (Result != MCDisassembler::Fail) {
 899       Size = 4;
 900       return Result;
 901     }
 902   }
 903
 904   if (isGP64()) {
 905     DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n");
 906     Result = decodeInstruction(DecoderTableMips6432, Instr, Insn,
 907                                Address, this, STI);
 908     if (Result != MCDisassembler::Fail) {
 909       Size = 4;
 910       return Result;
 911     }
 912   }
 913
 914   DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
 915   // Calling the auto-generated decoder function.
 916   Result =
 917       decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
 918   if (Result != MCDisassembler::Fail) {
 919     Size = 4;
 920     return Result;
 921   }
 922
 923   return MCDisassembler::Fail;
 924 }
 925
 926 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 927                                                  unsigned RegNo,
 928                                                  uint64_t Address,
 929                                                  const void *Decoder) {
 930
 931   return MCDisassembler::Fail;
 932
 933 }
 934
 935 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
 936                                              unsigned RegNo,
 937                                              uint64_t Address,
 938                                              const void *Decoder) {
 939
 940   if (RegNo > 31)
 941     return MCDisassembler::Fail;
 942
 943   unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
 944   Inst.addOperand(MCOperand::createReg(Reg));
 945   return MCDisassembler::Success;
 946 }
 947
 948 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
 949                                                unsigned RegNo,
 950                                                uint64_t Address,
 951                                                const void *Decoder) {
 952   if (RegNo > 7)
 953     return MCDisassembler::Fail;
 954   unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
 955   Inst.addOperand(MCOperand::createReg(Reg));
 956   return MCDisassembler::Success;
 957 }
 958
 959 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
 960                                                    unsigned RegNo,
 961                                                    uint64_t Address,
 962                                                    const void *Decoder) {
 963   if (RegNo > 7)
 964     return MCDisassembler::Fail;
 965   unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
 966   Inst.addOperand(MCOperand::createReg(Reg));
 967   return MCDisassembler::Success;
 968 }
 969
 970 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
 971                                                     unsigned RegNo,
 972                                                     uint64_t Address,
 973                                                     const void *Decoder) {
 974   if (RegNo > 7)
 975     return MCDisassembler::Fail;
 976   unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo);
 977   Inst.addOperand(MCOperand::createReg(Reg));
 978   return MCDisassembler::Success;
 979 }
 980
 981 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 982                                              unsigned RegNo,
 983                                              uint64_t Address,
 984                                              const void *Decoder) {
 985   if (RegNo > 31)
 986     return MCDisassembler::Fail;
 987   unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
 988   Inst.addOperand(MCOperand::createReg(Reg));
 989   return MCDisassembler::Success;
 990 }
 991
 992 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 993                                            unsigned RegNo,
 994                                            uint64_t Address,
 995                                            const void *Decoder) {
 996   if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())
 997     return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
 998
 999   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1000 }
1001
1002 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
1003                                             unsigned RegNo,
1004                                             uint64_t Address,
1005                                             const void *Decoder) {
1006   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1007 }
1008
1009 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
1010                                              unsigned RegNo,
1011                                              uint64_t Address,
1012                                              const void *Decoder) {
1013   if (RegNo > 31)
1014     return MCDisassembler::Fail;
1015
1016   unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
1017   Inst.addOperand(MCOperand::createReg(Reg));
1018   return MCDisassembler::Success;
1019 }
1020
1021 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
1022                                              unsigned RegNo,
1023                                              uint64_t Address,
1024                                              const void *Decoder) {
1025   if (RegNo > 31)
1026     return MCDisassembler::Fail;
1027
1028   unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
1029   Inst.addOperand(MCOperand::createReg(Reg));
1030   return MCDisassembler::Success;
1031 }
1032
1033 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
1034                                            unsigned RegNo,
1035                                            uint64_t Address,
1036                                            const void *Decoder) {
1037   if (RegNo > 31)
1038     return MCDisassembler::Fail;
1039   unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
1040   Inst.addOperand(MCOperand::createReg(Reg));
1041   return MCDisassembler::Success;
1042 }
1043
1044 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
1045                                            unsigned RegNo,
1046                                            uint64_t Address,
1047                                            const void *Decoder) {
1048   if (RegNo > 7)
1049     return MCDisassembler::Fail;
1050   unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
1051   Inst.addOperand(MCOperand::createReg(Reg));
1052   return MCDisassembler::Success;
1053 }
1054
1055 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
1056                                              uint64_t Address,
1057                                              const void *Decoder) {
1058   if (RegNo > 31)
1059     return MCDisassembler::Fail;
1060
1061   unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
1062   Inst.addOperand(MCOperand::createReg(Reg));
1063   return MCDisassembler::Success;
1064 }
1065
1066 static DecodeStatus DecodeMem(MCInst &Inst,
1067                               unsigned Insn,
1068                               uint64_t Address,
1069                               const void *Decoder) {
1070   int Offset = SignExtend32<16>(Insn & 0xffff);
1071   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1072   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1073
1074   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1075   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1076
1077   if(Inst.getOpcode() == Mips::SC ||
1078      Inst.getOpcode() == Mips::SCD){
1079     Inst.addOperand(MCOperand::createReg(Reg));
1080   }
1081
1082   Inst.addOperand(MCOperand::createReg(Reg));
1083   Inst.addOperand(MCOperand::createReg(Base));
1084   Inst.addOperand(MCOperand::createImm(Offset));
1085
1086   return MCDisassembler::Success;
1087 }
1088
1089 static DecodeStatus DecodeCacheOp(MCInst &Inst,
1090                               unsigned Insn,
1091                               uint64_t Address,
1092                               const void *Decoder) {
1093   int Offset = SignExtend32<16>(Insn & 0xffff);
1094   unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1095   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1096
1097   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1098
1099   Inst.addOperand(MCOperand::createReg(Base));
1100   Inst.addOperand(MCOperand::createImm(Offset));
1101   Inst.addOperand(MCOperand::createImm(Hint));
1102
1103   return MCDisassembler::Success;
1104 }
1105
1106 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
1107                                     unsigned Insn,
1108                                     uint64_t Address,
1109                                     const void *Decoder) {
1110   int Offset = SignExtend32<12>(Insn & 0xfff);
1111   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1112   unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1113
1114   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1115
1116   Inst.addOperand(MCOperand::createReg(Base));
1117   Inst.addOperand(MCOperand::createImm(Offset));
1118   Inst.addOperand(MCOperand::createImm(Hint));
1119
1120   return MCDisassembler::Success;
1121 }
1122
1123 static DecodeStatus DecodeCacheOpR6(MCInst &Inst,
1124                                     unsigned Insn,
1125                                     uint64_t Address,
1126                                     const void *Decoder) {
1127   int Offset = fieldFromInstruction(Insn, 7, 9);
1128   unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1129   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1130
1131   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1132
1133   Inst.addOperand(MCOperand::createReg(Base));
1134   Inst.addOperand(MCOperand::createImm(Offset));
1135   Inst.addOperand(MCOperand::createImm(Hint));
1136
1137   return MCDisassembler::Success;
1138 }
1139
1140 static DecodeStatus DecodeSyncI(MCInst &Inst,
1141                               unsigned Insn,
1142                               uint64_t Address,
1143                               const void *Decoder) {
1144   int Offset = SignExtend32<16>(Insn & 0xffff);
1145   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1146
1147   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1148
1149   Inst.addOperand(MCOperand::createReg(Base));
1150   Inst.addOperand(MCOperand::createImm(Offset));
1151
1152   return MCDisassembler::Success;
1153 }
1154
1155 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1156                                     uint64_t Address, const void *Decoder) {
1157   int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1158   unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1159   unsigned Base = fieldFromInstruction(Insn, 11, 5);
1160
1161   Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1162   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1163
1164   Inst.addOperand(MCOperand::createReg(Reg));
1165   Inst.addOperand(MCOperand::createReg(Base));
1166
1167   // The immediate field of an LD/ST instruction is scaled which means it must
1168   // be multiplied (when decoding) by the size (in bytes) of the instructions'
1169   // data format.
1170   // .b - 1 byte
1171   // .h - 2 bytes
1172   // .w - 4 bytes
1173   // .d - 8 bytes
1174   switch(Inst.getOpcode())
1175   {
1176   default:
1177     assert (0 && "Unexpected instruction");
1178     return MCDisassembler::Fail;
1179     break;
1180   case Mips::LD_B:
1181   case Mips::ST_B:
1182     Inst.addOperand(MCOperand::createImm(Offset));
1183     break;
1184   case Mips::LD_H:
1185   case Mips::ST_H:
1186     Inst.addOperand(MCOperand::createImm(Offset * 2));
1187     break;
1188   case Mips::LD_W:
1189   case Mips::ST_W:
1190     Inst.addOperand(MCOperand::createImm(Offset * 4));
1191     break;
1192   case Mips::LD_D:
1193   case Mips::ST_D:
1194     Inst.addOperand(MCOperand::createImm(Offset * 8));
1195     break;
1196   }
1197
1198   return MCDisassembler::Success;
1199 }
1200
1201 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
1202                                     unsigned Insn,
1203                                     uint64_t Address,
1204                                     const void *Decoder) {
1205   unsigned Offset = Insn & 0xf;
1206   unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1207   unsigned Base = fieldFromInstruction(Insn, 4, 3);
1208
1209   switch (Inst.getOpcode()) {
1210     case Mips::LBU16_MM:
1211     case Mips::LHU16_MM:
1212     case Mips::LW16_MM:
1213       if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
1214             == MCDisassembler::Fail)
1215         return MCDisassembler::Fail;
1216       break;
1217     case Mips::SB16_MM:
1218     case Mips::SH16_MM:
1219     case Mips::SW16_MM:
1220       if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
1221             == MCDisassembler::Fail)
1222         return MCDisassembler::Fail;
1223       break;
1224   }
1225
1226   if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
1227         == MCDisassembler::Fail)
1228     return MCDisassembler::Fail;
1229
1230   switch (Inst.getOpcode()) {
1231     case Mips::LBU16_MM:
1232       if (Offset == 0xf)
1233         Inst.addOperand(MCOperand::createImm(-1));
1234       else
1235         Inst.addOperand(MCOperand::createImm(Offset));
1236       break;
1237     case Mips::SB16_MM:
1238       Inst.addOperand(MCOperand::createImm(Offset));
1239       break;
1240     case Mips::LHU16_MM:
1241     case Mips::SH16_MM:
1242       Inst.addOperand(MCOperand::createImm(Offset << 1));
1243       break;
1244     case Mips::LW16_MM:
1245     case Mips::SW16_MM:
1246       Inst.addOperand(MCOperand::createImm(Offset << 2));
1247       break;
1248   }
1249
1250   return MCDisassembler::Success;
1251 }
1252
1253 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
1254                                           unsigned Insn,
1255                                           uint64_t Address,
1256                                           const void *Decoder) {
1257   unsigned Offset = Insn & 0x1F;
1258   unsigned Reg = fieldFromInstruction(Insn, 5, 5);
1259
1260   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1261
1262   Inst.addOperand(MCOperand::createReg(Reg));
1263   Inst.addOperand(MCOperand::createReg(Mips::SP));
1264   Inst.addOperand(MCOperand::createImm(Offset << 2));
1265
1266   return MCDisassembler::Success;
1267 }
1268
1269 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
1270                                           unsigned Insn,
1271                                           uint64_t Address,
1272                                           const void *Decoder) {
1273   unsigned Offset = Insn & 0x7F;
1274   unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1275
1276   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1277
1278   Inst.addOperand(MCOperand::createReg(Reg));
1279   Inst.addOperand(MCOperand::createReg(Mips::GP));
1280   Inst.addOperand(MCOperand::createImm(Offset << 2));
1281
1282   return MCDisassembler::Success;
1283 }
1284
1285 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
1286                                                unsigned Insn,
1287                                                uint64_t Address,
1288                                                const void *Decoder) {
1289   int Offset = SignExtend32<4>(Insn & 0xf);
1290
1291   if (DecodeRegListOperand16(Inst, Insn, Address, Decoder)
1292       == MCDisassembler::Fail)
1293     return MCDisassembler::Fail;
1294
1295   Inst.addOperand(MCOperand::createReg(Mips::SP));
1296   Inst.addOperand(MCOperand::createImm(Offset << 2));
1297
1298   return MCDisassembler::Success;
1299 }
1300
1301 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1302                                      unsigned Insn,
1303                                      uint64_t Address,
1304                                      const void *Decoder) {
1305   int Offset = SignExtend32<12>(Insn & 0x0fff);
1306   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1307   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1308
1309   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1310   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1311
1312   switch (Inst.getOpcode()) {
1313   case Mips::SWM32_MM:
1314   case Mips::LWM32_MM:
1315     if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1316         == MCDisassembler::Fail)
1317       return MCDisassembler::Fail;
1318     Inst.addOperand(MCOperand::createReg(Base));
1319     Inst.addOperand(MCOperand::createImm(Offset));
1320     break;
1321   case Mips::SC_MM:
1322     Inst.addOperand(MCOperand::createReg(Reg));
1323     // fallthrough
1324   default:
1325     Inst.addOperand(MCOperand::createReg(Reg));
1326     if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
1327       Inst.addOperand(MCOperand::createReg(Reg+1));
1328
1329     Inst.addOperand(MCOperand::createReg(Base));
1330     Inst.addOperand(MCOperand::createImm(Offset));
1331   }
1332
1333   return MCDisassembler::Success;
1334 }
1335
1336 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1337                                      unsigned Insn,
1338                                      uint64_t Address,
1339                                      const void *Decoder) {
1340   int Offset = SignExtend32<16>(Insn & 0xffff);
1341   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1342   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1343
1344   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1345   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1346
1347   Inst.addOperand(MCOperand::createReg(Reg));
1348   Inst.addOperand(MCOperand::createReg(Base));
1349   Inst.addOperand(MCOperand::createImm(Offset));
1350
1351   return MCDisassembler::Success;
1352 }
1353
1354 static DecodeStatus DecodeFMem(MCInst &Inst,
1355                                unsigned Insn,
1356                                uint64_t Address,
1357                                const void *Decoder) {
1358   int Offset = SignExtend32<16>(Insn & 0xffff);
1359   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1360   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1361
1362   Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1363   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1364
1365   Inst.addOperand(MCOperand::createReg(Reg));
1366   Inst.addOperand(MCOperand::createReg(Base));
1367   Inst.addOperand(MCOperand::createImm(Offset));
1368
1369   return MCDisassembler::Success;
1370 }
1371
1372 static DecodeStatus DecodeFMem2(MCInst &Inst,
1373                                unsigned Insn,
1374                                uint64_t Address,
1375                                const void *Decoder) {
1376   int Offset = SignExtend32<16>(Insn & 0xffff);
1377   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1378   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1379
1380   Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1381   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1382
1383   Inst.addOperand(MCOperand::createReg(Reg));
1384   Inst.addOperand(MCOperand::createReg(Base));
1385   Inst.addOperand(MCOperand::createImm(Offset));
1386
1387   return MCDisassembler::Success;
1388 }
1389
1390 static DecodeStatus DecodeFMem3(MCInst &Inst,
1391                                unsigned Insn,
1392                                uint64_t Address,
1393                                const void *Decoder) {
1394   int Offset = SignExtend32<16>(Insn & 0xffff);
1395   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1396   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1397
1398   Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1399   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1400
1401   Inst.addOperand(MCOperand::createReg(Reg));
1402   Inst.addOperand(MCOperand::createReg(Base));
1403   Inst.addOperand(MCOperand::createImm(Offset));
1404
1405   return MCDisassembler::Success;
1406 }
1407
1408 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst,
1409                                     unsigned Insn,
1410                                     uint64_t Address,
1411                                     const void *Decoder) {
1412   int Offset = SignExtend32<11>(Insn & 0x07ff);
1413   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1414   unsigned Base = fieldFromInstruction(Insn, 11, 5);
1415
1416   Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1417   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1418
1419   Inst.addOperand(MCOperand::createReg(Reg));
1420   Inst.addOperand(MCOperand::createReg(Base));
1421   Inst.addOperand(MCOperand::createImm(Offset));
1422
1423   return MCDisassembler::Success;
1424 }
1425 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
1426                                        unsigned Insn,
1427                                        uint64_t Address,
1428                                        const void *Decoder) {
1429   int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1430   unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1431   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1432
1433   Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
1434   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1435
1436   if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1437     Inst.addOperand(MCOperand::createReg(Rt));
1438   }
1439
1440   Inst.addOperand(MCOperand::createReg(Rt));
1441   Inst.addOperand(MCOperand::createReg(Base));
1442   Inst.addOperand(MCOperand::createImm(Offset));
1443
1444   return MCDisassembler::Success;
1445 }
1446
1447 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
1448                                               unsigned RegNo,
1449                                               uint64_t Address,
1450                                               const void *Decoder) {
1451   // Currently only hardware register 29 is supported.
1452   if (RegNo != 29)
1453     return  MCDisassembler::Fail;
1454   Inst.addOperand(MCOperand::createReg(Mips::HWR29));
1455   return MCDisassembler::Success;
1456 }
1457
1458 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
1459                                               unsigned RegNo,
1460                                               uint64_t Address,
1461                                               const void *Decoder) {
1462   if (RegNo > 30 || RegNo %2)
1463     return MCDisassembler::Fail;
1464
1465   ;
1466   unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1467   Inst.addOperand(MCOperand::createReg(Reg));
1468   return MCDisassembler::Success;
1469 }
1470
1471 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
1472                                                 unsigned RegNo,
1473                                                 uint64_t Address,
1474                                                 const void *Decoder) {
1475   if (RegNo >= 4)
1476     return MCDisassembler::Fail;
1477
1478   unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1479   Inst.addOperand(MCOperand::createReg(Reg));
1480   return MCDisassembler::Success;
1481 }
1482
1483 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
1484                                                unsigned RegNo,
1485                                                uint64_t Address,
1486                                                const void *Decoder) {
1487   if (RegNo >= 4)
1488     return MCDisassembler::Fail;
1489
1490   unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1491   Inst.addOperand(MCOperand::createReg(Reg));
1492   return MCDisassembler::Success;
1493 }
1494
1495 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
1496                                                unsigned RegNo,
1497                                                uint64_t Address,
1498                                                const void *Decoder) {
1499   if (RegNo >= 4)
1500     return MCDisassembler::Fail;
1501
1502   unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1503   Inst.addOperand(MCOperand::createReg(Reg));
1504   return MCDisassembler::Success;
1505 }
1506
1507 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
1508                                                unsigned RegNo,
1509                                                uint64_t Address,
1510                                                const void *Decoder) {
1511   if (RegNo > 31)
1512     return MCDisassembler::Fail;
1513
1514   unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1515   Inst.addOperand(MCOperand::createReg(Reg));
1516   return MCDisassembler::Success;
1517 }
1518
1519 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
1520                                                unsigned RegNo,
1521                                                uint64_t Address,
1522                                                const void *Decoder) {
1523   if (RegNo > 31)
1524     return MCDisassembler::Fail;
1525
1526   unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1527   Inst.addOperand(MCOperand::createReg(Reg));
1528   return MCDisassembler::Success;
1529 }
1530
1531 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
1532                                                unsigned RegNo,
1533                                                uint64_t Address,
1534                                                const void *Decoder) {
1535   if (RegNo > 31)
1536     return MCDisassembler::Fail;
1537
1538   unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1539   Inst.addOperand(MCOperand::createReg(Reg));
1540   return MCDisassembler::Success;
1541 }
1542
1543 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
1544                                                unsigned RegNo,
1545                                                uint64_t Address,
1546                                                const void *Decoder) {
1547   if (RegNo > 31)
1548     return MCDisassembler::Fail;
1549
1550   unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1551   Inst.addOperand(MCOperand::createReg(Reg));
1552   return MCDisassembler::Success;
1553 }
1554
1555 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
1556                                                unsigned RegNo,
1557                                                uint64_t Address,
1558                                                const void *Decoder) {
1559   if (RegNo > 7)
1560     return MCDisassembler::Fail;
1561
1562   unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1563   Inst.addOperand(MCOperand::createReg(Reg));
1564   return MCDisassembler::Success;
1565 }
1566
1567 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
1568                                             unsigned RegNo,
1569                                             uint64_t Address,
1570                                             const void *Decoder) {
1571   if (RegNo > 31)
1572     return MCDisassembler::Fail;
1573
1574   unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1575   Inst.addOperand(MCOperand::createReg(Reg));
1576   return MCDisassembler::Success;
1577 }
1578
1579 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1580                                        unsigned Offset,
1581                                        uint64_t Address,
1582                                        const void *Decoder) {
1583   int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
1584   Inst.addOperand(MCOperand::createImm(BranchOffset));
1585   return MCDisassembler::Success;
1586 }
1587
1588 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1589                                      unsigned Insn,
1590                                      uint64_t Address,
1591                                      const void *Decoder) {
1592
1593   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1594   Inst.addOperand(MCOperand::createImm(JumpOffset));
1595   return MCDisassembler::Success;
1596 }
1597
1598 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1599                                          unsigned Offset,
1600                                          uint64_t Address,
1601                                          const void *Decoder) {
1602   int32_t BranchOffset = SignExtend32<21>(Offset) * 4;
1603
1604   Inst.addOperand(MCOperand::createImm(BranchOffset));
1605   return MCDisassembler::Success;
1606 }
1607
1608 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1609                                          unsigned Offset,
1610                                          uint64_t Address,
1611                                          const void *Decoder) {
1612   int32_t BranchOffset = SignExtend32<26>(Offset) * 4;
1613
1614   Inst.addOperand(MCOperand::createImm(BranchOffset));
1615   return MCDisassembler::Success;
1616 }
1617
1618 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
1619                                           unsigned Offset,
1620                                           uint64_t Address,
1621                                           const void *Decoder) {
1622   int32_t BranchOffset = SignExtend32<7>(Offset) << 1;
1623   Inst.addOperand(MCOperand::createImm(BranchOffset));
1624   return MCDisassembler::Success;
1625 }
1626
1627 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
1628                                            unsigned Offset,
1629                                            uint64_t Address,
1630                                            const void *Decoder) {
1631   int32_t BranchOffset = SignExtend32<10>(Offset) << 1;
1632   Inst.addOperand(MCOperand::createImm(BranchOffset));
1633   return MCDisassembler::Success;
1634 }
1635
1636 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1637                                          unsigned Offset,
1638                                          uint64_t Address,
1639                                          const void *Decoder) {
1640   int32_t BranchOffset = SignExtend32<16>(Offset) * 2;
1641   Inst.addOperand(MCOperand::createImm(BranchOffset));
1642   return MCDisassembler::Success;
1643 }
1644
1645 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1646                                        unsigned Insn,
1647                                        uint64_t Address,
1648                                        const void *Decoder) {
1649   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1650   Inst.addOperand(MCOperand::createImm(JumpOffset));
1651   return MCDisassembler::Success;
1652 }
1653
1654 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
1655                                        unsigned Value,
1656                                        uint64_t Address,
1657                                        const void *Decoder) {
1658   if (Value == 0)
1659     Inst.addOperand(MCOperand::createImm(1));
1660   else if (Value == 0x7)
1661     Inst.addOperand(MCOperand::createImm(-1));
1662   else
1663     Inst.addOperand(MCOperand::createImm(Value << 2));
1664   return MCDisassembler::Success;
1665 }
1666
1667 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
1668                                     unsigned Value,
1669                                     uint64_t Address,
1670                                     const void *Decoder) {
1671   Inst.addOperand(MCOperand::createImm(Value << 2));
1672   return MCDisassembler::Success;
1673 }
1674
1675 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
1676                                   unsigned Value,
1677                                   uint64_t Address,
1678                                   const void *Decoder) {
1679   if (Value == 0x7F)
1680     Inst.addOperand(MCOperand::createImm(-1));
1681   else
1682     Inst.addOperand(MCOperand::createImm(Value));
1683   return MCDisassembler::Success;
1684 }
1685
1686 static DecodeStatus DecodeSimm4(MCInst &Inst,
1687                                 unsigned Value,
1688                                 uint64_t Address,
1689                                 const void *Decoder) {
1690   Inst.addOperand(MCOperand::createImm(SignExtend32<4>(Value)));
1691   return MCDisassembler::Success;
1692 }
1693
1694 static DecodeStatus DecodeSimm16(MCInst &Inst,
1695                                  unsigned Insn,
1696                                  uint64_t Address,
1697                                  const void *Decoder) {
1698   Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Insn)));
1699   return MCDisassembler::Success;
1700 }
1701
1702 static DecodeStatus DecodeLSAImm(MCInst &Inst,
1703                                  unsigned Insn,
1704                                  uint64_t Address,
1705                                  const void *Decoder) {
1706   // We add one to the immediate field as it was encoded as 'imm - 1'.
1707   Inst.addOperand(MCOperand::createImm(Insn + 1));
1708   return MCDisassembler::Success;
1709 }
1710
1711 static DecodeStatus DecodeInsSize(MCInst &Inst,
1712                                   unsigned Insn,
1713                                   uint64_t Address,
1714                                   const void *Decoder) {
1715   // First we need to grab the pos(lsb) from MCInst.
1716   int Pos = Inst.getOperand(2).getImm();
1717   int Size = (int) Insn - Pos + 1;
1718   Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
1719   return MCDisassembler::Success;
1720 }
1721
1722 static DecodeStatus DecodeExtSize(MCInst &Inst,
1723                                   unsigned Insn,
1724                                   uint64_t Address,
1725                                   const void *Decoder) {
1726   int Size = (int) Insn  + 1;
1727   Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
1728   return MCDisassembler::Success;
1729 }
1730
1731 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1732                                      uint64_t Address, const void *Decoder) {
1733   Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4));
1734   return MCDisassembler::Success;
1735 }
1736
1737 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1738                                      uint64_t Address, const void *Decoder) {
1739   Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8));
1740   return MCDisassembler::Success;
1741 }
1742
1743 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
1744                                   uint64_t Address, const void *Decoder) {
1745   int32_t DecodedValue;
1746   switch (Insn) {
1747   case 0: DecodedValue = 256; break;
1748   case 1: DecodedValue = 257; break;
1749   case 510: DecodedValue = -258; break;
1750   case 511: DecodedValue = -257; break;
1751   default: DecodedValue = SignExtend32<9>(Insn); break;
1752   }
1753   Inst.addOperand(MCOperand::createImm(DecodedValue * 4));
1754   return MCDisassembler::Success;
1755 }
1756
1757 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
1758                                     uint64_t Address, const void *Decoder) {
1759   // Insn must be >= 0, since it is unsigned that condition is always true.
1760   assert(Insn < 16);
1761   int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
1762                              255, 32768, 65535};
1763   Inst.addOperand(MCOperand::createImm(DecodedValues[Insn]));
1764   return MCDisassembler::Success;
1765 }
1766
1767 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
1768                                     uint64_t Address, const void *Decoder) {
1769   Inst.addOperand(MCOperand::createImm(Insn << 2));
1770   return MCDisassembler::Success;
1771 }
1772
1773 static DecodeStatus DecodeRegListOperand(MCInst &Inst,
1774                                          unsigned Insn,
1775                                          uint64_t Address,
1776                                          const void *Decoder) {
1777   unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
1778                      Mips::S6, Mips::FP};
1779   unsigned RegNum;
1780
1781   unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
1782   // Empty register lists are not allowed.
1783   if (RegLst == 0)
1784     return MCDisassembler::Fail;
1785
1786   RegNum = RegLst & 0xf;
1787   for (unsigned i = 0; i < RegNum; i++)
1788     Inst.addOperand(MCOperand::createReg(Regs[i]));
1789
1790   if (RegLst & 0x10)
1791     Inst.addOperand(MCOperand::createReg(Mips::RA));
1792
1793   return MCDisassembler::Success;
1794 }
1795
1796 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
1797                                            uint64_t Address,
1798                                            const void *Decoder) {
1799   unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
1800   unsigned RegLst = fieldFromInstruction(Insn, 4, 2);
1801   unsigned RegNum = RegLst & 0x3;
1802
1803   for (unsigned i = 0; i <= RegNum; i++)
1804     Inst.addOperand(MCOperand::createReg(Regs[i]));
1805
1806   Inst.addOperand(MCOperand::createReg(Mips::RA));
1807
1808   return MCDisassembler::Success;
1809 }
1810
1811 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
1812                                        uint64_t Address, const void *Decoder) {
1813
1814   unsigned RegPair = fieldFromInstruction(Insn, 7, 3);
1815
1816   switch (RegPair) {
1817   default:
1818     return MCDisassembler::Fail;
1819   case 0:
1820     Inst.addOperand(MCOperand::createReg(Mips::A1));
1821     Inst.addOperand(MCOperand::createReg(Mips::A2));
1822     break;
1823   case 1:
1824     Inst.addOperand(MCOperand::createReg(Mips::A1));
1825     Inst.addOperand(MCOperand::createReg(Mips::A3));
1826     break;
1827   case 2:
1828     Inst.addOperand(MCOperand::createReg(Mips::A2));
1829     Inst.addOperand(MCOperand::createReg(Mips::A3));
1830     break;
1831   case 3:
1832     Inst.addOperand(MCOperand::createReg(Mips::A0));
1833     Inst.addOperand(MCOperand::createReg(Mips::S5));
1834     break;
1835   case 4:
1836     Inst.addOperand(MCOperand::createReg(Mips::A0));
1837     Inst.addOperand(MCOperand::createReg(Mips::S6));
1838     break;
1839   case 5:
1840     Inst.addOperand(MCOperand::createReg(Mips::A0));
1841     Inst.addOperand(MCOperand::createReg(Mips::A1));
1842     break;
1843   case 6:
1844     Inst.addOperand(MCOperand::createReg(Mips::A0));
1845     Inst.addOperand(MCOperand::createReg(Mips::A2));
1846     break;
1847   case 7:
1848     Inst.addOperand(MCOperand::createReg(Mips::A0));
1849     Inst.addOperand(MCOperand::createReg(Mips::A3));
1850     break;
1851   }
1852
1853   return MCDisassembler::Success;
1854 }
1855
1856 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
1857                                      uint64_t Address, const void *Decoder) {
1858   Inst.addOperand(MCOperand::createImm(SignExtend32<23>(Insn) << 2));
1859   return MCDisassembler::Success;
1860 }