lib/Target/Mips/MicroMips32r6InstrInfo.td

   1 //=- MicroMips32r6InstrInfo.td - MicroMips r6 Instruction Information -*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes microMIPSr6 instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 def brtarget26_mm : Operand<OtherVT> {
  15   let EncoderMethod = "getBranchTarget26OpValueMM";
  16   let OperandType = "OPERAND_PCREL";
  17   let DecoderMethod = "DecodeBranchTarget26MM";
  18   let ParserMatchClass = MipsJumpTargetAsmOperand;
  19 }
  20
  21 //===----------------------------------------------------------------------===//
  22 //
  23 // Instruction Encodings
  24 //
  25 //===----------------------------------------------------------------------===//
  26 class ADD_MMR6_ENC : ARITH_FM_MMR6<"add", 0x110>;
  27 class ADDIU_MMR6_ENC : ADDI_FM_MMR6<"addiu", 0xc>;
  28 class ADDU_MMR6_ENC : ARITH_FM_MMR6<"addu", 0x150>;
  29 class ADDIUPC_MMR6_ENC : PCREL19_FM_MMR6<0b00>;
  30 class ALUIPC_MMR6_ENC : PCREL16_FM_MMR6<0b11111>;
  31 class AND_MMR6_ENC : ARITH_FM_MMR6<"and", 0x250>;
  32 class ANDI_MMR6_ENC : ADDI_FM_MMR6<"andi", 0x34>;
  33 class AUIPC_MMR6_ENC  : PCREL16_FM_MMR6<0b11110>;
  34 class ALIGN_MMR6_ENC : POOL32A_ALIGN_FM_MMR6<0b011111>;
  35 class AUI_MMR6_ENC : AUI_FM_MMR6;
  36 class BALC_MMR6_ENC  : BRANCH_OFF26_FM<0b101101>;
  37 class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>;
  38 class BC16_MMR6_ENC : BC16_FM_MM16R6;
  39 class BEQZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x23>;
  40 class BNEZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x2b>;
  41 class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>;
  42 class BRK_MMR6_ENC : BREAK_MMR6_ENC<"break">;
  43 class BEQZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b011101>;
  44 class BNEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b011111>;
  45 class BGTZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b111000>;
  46 class BLTZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<0b111000>;
  47 class BGEZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<0b110000>;
  48 class BLEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b110000>;
  49 class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>;
  50 class CLO_MMR6_ENC : POOL32A_2R_FM_MMR6<0b0100101100>;
  51 class CLZ_MMR6_ENC : SPECIAL_2R_FM_MMR6<0b010000>;
  52 class DIV_MMR6_ENC : ARITH_FM_MMR6<"div", 0x118>;
  53 class DIVU_MMR6_ENC : ARITH_FM_MMR6<"divu", 0x198>;
  54 class EHB_MMR6_ENC : BARRIER_MMR6_ENC<"ehb", 0x3>;
  55 class EI_MMR6_ENC : POOL32A_EIDI_MMR6_ENC<"ei", 0x15d>;
  56 class DI_MMR6_ENC : POOL32A_EIDI_MMR6_ENC<"di", 0b0100011101>;
  57 class ERET_MMR6_ENC : POOL32A_ERET_FM_MMR6<"eret", 0x3cd>;
  58 class DERET_MMR6_ENC : POOL32A_ERET_FM_MMR6<"eret", 0b1110001101>;
  59 class ERETNC_MMR6_ENC : ERETNC_FM_MMR6<"eretnc">;
  60 class JALRC16_MMR6_ENC : POOL16C_JALRC_FM_MM16R6<0xb>;
  61 class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b100000>;
  62 class JIC_MMR6_ENC   : JMP_IDX_COMPACT_FM<0b101000>;
  63 class JRC16_MMR6_ENC: POOL16C_JALRC_FM_MM16R6<0x3>;
  64 class JRCADDIUSP_MMR6_ENC : POOL16C_JRCADDIUSP_FM_MM16R6<0x13>;
  65 class LSA_MMR6_ENC : POOL32A_LSA_FM<0b001111>;
  66 class LWPC_MMR6_ENC  : PCREL19_FM_MMR6<0b01>;
  67 class LWM16_MMR6_ENC : POOL16C_LWM_SWM_FM_MM16R6<0x2>;
  68 class MOD_MMR6_ENC : ARITH_FM_MMR6<"mod", 0x158>;
  69 class MODU_MMR6_ENC : ARITH_FM_MMR6<"modu", 0x1d8>;
  70 class MUL_MMR6_ENC : ARITH_FM_MMR6<"mul", 0x18>;
  71 class MUH_MMR6_ENC : ARITH_FM_MMR6<"muh", 0x58>;
  72 class MULU_MMR6_ENC : ARITH_FM_MMR6<"mulu", 0x98>;
  73 class MUHU_MMR6_ENC : ARITH_FM_MMR6<"muhu", 0xd8>;
  74 class NOR_MMR6_ENC : ARITH_FM_MMR6<"nor", 0x2d0>;
  75 class OR_MMR6_ENC : ARITH_FM_MMR6<"or", 0x290>;
  76 class ORI_MMR6_ENC : ADDI_FM_MMR6<"ori", 0x14>;
  77 class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>;
  78 class SB16_MMR6_ENC : LOAD_STORE_FM_MM16<0x22>;
  79 class SEB_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seb", 0b0010101100>;
  80 class SEH_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seh", 0b0011101100>;
  81 class SELEQZ_MMR6_ENC : POOL32A_FM_MMR6<0b0101000000>;
  82 class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>;
  83 class SH16_MMR6_ENC : LOAD_STORE_FM_MM16<0x2a>;
  84 class SLL_MMR6_ENC : SHIFT_MMR6_ENC<"sll", 0x00, 0b0>;
  85 class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>;
  86 class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>;
  87 class SW_MMR6_ENC : SW32_FM_MMR6<"sw", 0x3e>;
  88 class SWE_MMR6_ENC : POOL32C_SWE_FM_MMR6<"swe", 0x18, 0xa, 0x7>;
  89 class SW16_MMR6_ENC : LOAD_STORE_FM_MM16<0x3a>;
  90 class SWM16_MMR6_ENC : POOL16C_LWM_SWM_FM_MM16R6<0xa>;
  91 class SWSP_MMR6_ENC : LOAD_STORE_SP_FM_MM16<0x32>;
  92 class PREFE_MMR6_ENC : POOL32C_ST_EVA_FM_MMR6<0b011000, 0b010>;
  93 class CACHEE_MMR6_ENC : POOL32C_ST_EVA_FM_MMR6<0b011000, 0b011>;
  94 class WRPGPR_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<0x3c5>;
  95 class WSBH_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<0x1ec>;
  96 class LB_MMR6_ENC : LB32_FM_MMR6;
  97 class LBU_MMR6_ENC : LBU32_FM_MMR6;
  98 class LBE_MMR6_ENC : POOL32C_LB_LBU_FM_MMR6<0b100>;
  99 class LBUE_MMR6_ENC : POOL32C_LB_LBU_FM_MMR6<0b000>;
 100 class PAUSE_MMR6_ENC : POOL32A_PAUSE_FM_MMR6<"pause", 0b00101>;
 101 class RDHWR_MMR6_ENC : POOL32A_RDHWR_FM_MMR6;
 102 class WAIT_MMR6_ENC : WAIT_FM_MM, MMR6Arch<"wait">;
 103 class SSNOP_MMR6_ENC : BARRIER_FM_MM<0x1>, MMR6Arch<"ssnop">;
 104 class SYNC_MMR6_ENC : POOL32A_SYNC_FM_MMR6;
 105 class SYNCI_MMR6_ENC : POOL32I_SYNCI_FM_MMR6, MMR6Arch<"synci">;
 106 class RDPGPR_MMR6_ENC : POOL32A_RDPGPR_FM_MMR6<0b1110000101>;
 107 class SDBBP_MMR6_ENC : SDBBP_FM_MM, MMR6Arch<"sdbbp">;
 108 class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>;
 109 class XORI_MMR6_ENC : ADDI_FM_MMR6<"xori", 0x1c>;
 110 class ABS_S_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.s", 0, 0b0001101>;
 111 class ABS_D_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.d", 1, 0b0001101>;
 112 class FLOOR_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.s", 0, 0b00001100>;
 113 class FLOOR_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.d", 1, 0b00001100>;
 114 class FLOOR_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.s", 0, 0b00101100>;
 115 class FLOOR_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.d", 1, 0b00101100>;
 116 class CEIL_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.s", 0, 0b01001100>;
 117 class CEIL_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.d", 1, 0b01001100>;
 118 class CEIL_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.s", 0, 0b01101100>;
 119 class CEIL_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.d", 1, 0b01101100>;
 120 class TRUNC_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.s", 0, 0b10001100>;
 121 class TRUNC_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.d", 1, 0b10001100>;
 122 class TRUNC_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.s", 0, 0b10101100>;
 123 class TRUNC_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.d", 1, 0b10101100>;
 124 class SQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.s", 0, 0b00101000>;
 125 class SQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.d", 1, 0b00101000>;
 126 class RSQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.s", 0, 0b00001000>;
 127 class RSQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.d", 1, 0b00001000>;
 128 class SB_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b000110>;
 129 class SBE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b100>;
 130 class SCE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b110>;
 131 class SH_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b001110>;
 132 class SHE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b101>;
 133 class LLE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b110>;
 134 class LWE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b111>;
 135 class LW_MMR6_ENC : LOAD_WORD_FM_MMR6;
 136 class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6;
 137 class RECIP_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"recip.s", 0, 0b01001000>;
 138 class RECIP_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"recip.d", 1, 0b01001000>;
 139 class RINT_S_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.s", 0>;
 140 class RINT_D_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.d", 1>;
 141 class ROUND_L_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.s", 0,
 142                                                        0b11001100>;
 143 class ROUND_L_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.d", 1,
 144                                                        0b11001100>;
 145 class ROUND_W_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.w.s", 0,
 146                                                        0b11101100>;
 147 class ROUND_W_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.w.d", 1,
 148                                                        0b11101100>;
 149 class SEL_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"sel.s", 0, 0b010111000>;
 150 class SEL_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"sel.d", 1, 0b010111000>;
 151 class SELEQZ_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"seleqz.s", 0, 0b000111000>;
 152 class SELEQZ_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"seleqz.d", 1, 0b000111000>;
 153 class SELENZ_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"selenz.s", 0, 0b001111000>;
 154 class SELENZ_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"selenz.d", 1, 0b001111000>;
 155 class CLASS_S_MMR6_ENC : POOL32F_CLASS_FM_MMR6<"class.s", 0, 0b001100000>;
 156 class CLASS_D_MMR6_ENC : POOL32F_CLASS_FM_MMR6<"class.d", 1, 0b001100000>;
 157
 158 class ADDU16_MMR6_ENC : POOL16A_ADDU16_FM_MMR6;
 159 class AND16_MMR6_ENC : POOL16C_AND16_FM_MMR6;
 160 class ANDI16_MMR6_ENC : ANDI_FM_MM16<0b001011>, MicroMipsR6Inst16;
 161 class NOT16_MMR6_ENC : POOL16C_NOT16_FM_MMR6;
 162 class OR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1001>;
 163 class SLL16_MMR6_ENC : SHIFT_FM_MM16<0>, MicroMipsR6Inst16;
 164 class SRL16_MMR6_ENC : SHIFT_FM_MM16<1>, MicroMipsR6Inst16;
 165 class BREAK16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b011011>;
 166 class LI16_MMR6_ENC : LI_FM_MM16;
 167 class MOVE16_MMR6_ENC : MOVE_FM_MM16<0b000011>;
 168 class SDBBP16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b111011>;
 169 class SUBU16_MMR6_ENC : POOL16A_SUBU16_FM_MMR6;
 170 class XOR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1000>;
 171
 172 class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
 173                                   RegisterOperand GPROpnd>
 174     : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
 175   dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
 176   dag OutOperandList = (outs);
 177   string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
 178   list<Register> Defs = [AT];
 179 }
 180
 181 class BEQZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"beqzalc", brtarget_mm,
 182                                                       GPR32Opnd> {
 183   list<Register> Defs = [RA];
 184 }
 185
 186 class BGEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgezalc", brtarget_mm,
 187                                                       GPR32Opnd> {
 188   list<Register> Defs = [RA];
 189 }
 190
 191 class BGTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgtzalc", brtarget_mm,
 192                                                       GPR32Opnd> {
 193   list<Register> Defs = [RA];
 194 }
 195
 196 class BLEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"blezalc", brtarget_mm,
 197                                                       GPR32Opnd> {
 198   list<Register> Defs = [RA];
 199 }
 200
 201 class BLTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bltzalc", brtarget_mm,
 202                                                       GPR32Opnd> {
 203   list<Register> Defs = [RA];
 204 }
 205
 206 class BNEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bnezalc", brtarget_mm,
 207                                                       GPR32Opnd> {
 208   list<Register> Defs = [RA];
 209 }
 210
 211 /// Floating Point Instructions
 212 class FADD_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.s", 0, 0b00110000>;
 213 class FADD_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.d", 1, 0b00110000>;
 214 class FSUB_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.s", 0, 0b01110000>;
 215 class FSUB_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.d", 1, 0b01110000>;
 216 class FMUL_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.s", 0, 0b10110000>;
 217 class FMUL_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.d", 1, 0b10110000>;
 218 class FDIV_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.s", 0, 0b11110000>;
 219 class FDIV_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.d", 1, 0b11110000>;
 220 class MADDF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.s", 0, 0b110111000>;
 221 class MADDF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.d", 1, 0b110111000>;
 222 class MSUBF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.s", 0, 0b111111000>;
 223 class MSUBF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.d", 1, 0b111111000>;
 224 class FMOV_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.s", 0, 0b0000001>;
 225 class FMOV_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.d", 1, 0b0000001>;
 226 class FNEG_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.s", 0, 0b0101101>;
 227 class FNEG_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.d", 1, 0b0101101>;
 228 class MAX_S_MMR6_ENC : POOL32F_MINMAX_FM<"max.s", 0, 0b000001011>;
 229 class MAX_D_MMR6_ENC : POOL32F_MINMAX_FM<"max.d", 1, 0b000001011>;
 230 class MAXA_S_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.s", 0, 0b000101011>;
 231 class MAXA_D_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.d", 1, 0b000101011>;
 232 class MIN_S_MMR6_ENC : POOL32F_MINMAX_FM<"min.s", 0, 0b000000011>;
 233 class MIN_D_MMR6_ENC : POOL32F_MINMAX_FM<"min.d", 1, 0b000000011>;
 234 class MINA_S_MMR6_ENC : POOL32F_MINMAX_FM<"mina.s", 0, 0b000100011>;
 235 class MINA_D_MMR6_ENC : POOL32F_MINMAX_FM<"mina.d", 1, 0b000100011>;
 236
 237 class CVT_L_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.s", 0, 0b00000100>;
 238 class CVT_L_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.d", 1, 0b00000100>;
 239 class CVT_W_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.s", 0, 0b00100100>;
 240 class CVT_W_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.d", 1, 0b00100100>;
 241 class CVT_D_S_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.s", 0, 0b1001101>;
 242 class CVT_D_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.w", 1, 0b1001101>;
 243 class CVT_D_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.l", 2, 0b1001101>;
 244 class CVT_S_D_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.d", 0, 0b1101101>;
 245 class CVT_S_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.w", 1, 0b1101101>;
 246 class CVT_S_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.l", 2, 0b1101101>;
 247
 248 //===----------------------------------------------------------------------===//
 249 //
 250 // Instruction Descriptions
 251 //
 252 //===----------------------------------------------------------------------===//
 253
 254 class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd>;
 255 class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd>;
 256 class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd>;
 257 class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd>;
 258 class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd>;
 259 class MULU_MMR6_DESC : ArithLogicR<"mulu", GPR32Opnd>;
 260 class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd>;
 261
 262 class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd>
 263     : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
 264   dag InOperandList = (ins opnd:$offset);
 265   dag OutOperandList = (outs);
 266   string AsmString = !strconcat(instr_asm, "\t$offset");
 267   bit isBarrier = 1;
 268 }
 269
 270 class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26_mm> {
 271   bit isCall = 1;
 272   list<Register> Defs = [RA];
 273 }
 274 class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26_mm>;
 275
 276 class BC16_MMR6_DESC : MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
 277                                        !strconcat("bc16", "\t$offset"), [],
 278                                        II_BC, FrmI>,
 279                        MMR6Arch<"bc16">, MicroMipsR6Inst16 {
 280   let isBranch = 1;
 281   let isTerminator = 1;
 282   let isBarrier = 1;
 283   let hasDelaySlot = 0;
 284   let AdditionalPredicates = [RelocPIC];
 285   let Defs = [AT];
 286 }
 287
 288 class BEQZC_BNEZC_MM16R6_DESC_BASE<string instr_asm>
 289     : CBranchZeroMM<instr_asm, brtarget7_mm, GPRMM16Opnd>, MMR6Arch<instr_asm> {
 290   let isBranch = 1;
 291   let isTerminator = 1;
 292   let hasDelaySlot = 0;
 293   let Defs = [AT];
 294 }
 295 class BEQZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"beqzc16">;
 296 class BNEZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"bnezc16">;
 297
 298 class SUB_MMR6_DESC : ArithLogicR<"sub", GPR32Opnd>;
 299 class SUBU_MMR6_DESC : ArithLogicR<"subu", GPR32Opnd>;
 300
 301 class BITSWAP_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 302     : MMR6Arch<instr_asm> {
 303   dag OutOperandList = (outs GPROpnd:$rd);
 304   dag InOperandList = (ins GPROpnd:$rt);
 305   string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
 306   list<dag> Pattern = [];
 307 }
 308
 309 class BITSWAP_MMR6_DESC : BITSWAP_MMR6_DESC_BASE<"bitswap", GPR32Opnd>;
 310
 311 class BRK_MMR6_DESC : BRK_FT<"break">;
 312
 313 class CACHE_HINT_MMR6_DESC<string instr_asm, Operand MemOpnd,
 314                            RegisterOperand GPROpnd> : MMR6Arch<instr_asm> {
 315   dag OutOperandList = (outs);
 316   dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
 317   string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
 318   list<dag> Pattern = [];
 319   string DecoderMethod = "DecodeCacheOpMM";
 320 }
 321
 322 class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, GPR32Opnd>;
 323 class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, GPR32Opnd>;
 324
 325 class PREFE_CACHEE_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
 326                                   RegisterOperand GPROpnd> :
 327                                   CACHE_HINT_MMR6_DESC<instr_asm, MemOpnd,
 328                                   GPROpnd> {
 329   string DecoderMethod = "DecodePrefeOpMM";
 330 }
 331
 332 class PREFE_MMR6_DESC : PREFE_CACHEE_MMR6_DESC_BASE<"prefe", mem_mm_9, GPR32Opnd>;
 333 class CACHEE_MMR6_DESC : PREFE_CACHEE_MMR6_DESC_BASE<"cachee", mem_mm_9, GPR32Opnd>;
 334
 335 class LB_LBU_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
 336                             RegisterOperand GPROpnd> : MMR6Arch<instr_asm> {
 337   dag OutOperandList = (outs GPROpnd:$rt);
 338   dag InOperandList = (ins MemOpnd:$addr);
 339   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
 340   string DecoderMethod = "DecodeLoadByte15";
 341   bit mayLoad = 1;
 342 }
 343 class LB_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lb", mem_mm_16, GPR32Opnd>;
 344 class LBU_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lbu", mem_mm_16, GPR32Opnd>;
 345
 346 class LBE_LBUE_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
 347                               RegisterOperand GPROpnd>
 348     : LB_LBU_MMR6_DESC_BASE<instr_asm, MemOpnd, GPROpnd> {
 349   let DecoderMethod = "DecodeLoadByte9";
 350 }
 351 class LBE_MMR6_DESC : LBE_LBUE_MMR6_DESC_BASE<"lbe", mem_mm_9, GPR32Opnd>;
 352 class LBUE_MMR6_DESC : LBE_LBUE_MMR6_DESC_BASE<"lbue", mem_mm_9, GPR32Opnd>;
 353
 354 class CLO_CLZ_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 355     : MMR6Arch<instr_asm> {
 356   dag OutOperandList = (outs GPROpnd:$rt);
 357   dag InOperandList = (ins GPROpnd:$rs);
 358   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
 359 }
 360
 361 class CLO_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clo", GPR32Opnd>;
 362 class CLZ_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clz", GPR32Opnd>;
 363
 364 class EHB_MMR6_DESC : Barrier<"ehb">;
 365 class EI_MMR6_DESC : DEI_FT<"ei", GPR32Opnd>;
 366 class DI_MMR6_DESC : DEI_FT<"di", GPR32Opnd>;
 367
 368 class ERET_MMR6_DESC : ER_FT<"eret">;
 369 class DERET_MMR6_DESC : ER_FT<"deret">;
 370 class ERETNC_MMR6_DESC : ER_FT<"eretnc">;
 371
 372 class JALRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
 373     : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
 374                       [(MipsJmpLink RO:$rs)], II_JALR, FrmR>,
 375       MMR6Arch<opstr>, MicroMipsR6Inst16 {
 376   let isCall = 1;
 377   let hasDelaySlot = 0;
 378   let Defs = [RA];
 379 }
 380 class JALRC16_MMR6_DESC : JALRC16_MMR6_DESC_BASE<"jalr", GPR32Opnd>;
 381
 382 class JMP_MMR6_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
 383                                      RegisterOperand GPROpnd>
 384     : MMR6Arch<opstr> {
 385   dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
 386   string AsmString = !strconcat(opstr, "\t$rt, $offset");
 387   list<dag> Pattern = [];
 388   bit isTerminator = 1;
 389   bit hasDelaySlot = 0;
 390 }
 391
 392 class JIALC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
 393                                                        GPR32Opnd> {
 394   bit isCall = 1;
 395   list<Register> Defs = [RA];
 396 }
 397
 398 class JIC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
 399                                                      GPR32Opnd> {
 400   bit isBarrier = 1;
 401   list<Register> Defs = [AT];
 402 }
 403
 404 class JRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
 405     : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
 406                       [], II_JR, FrmR>,
 407       MMR6Arch<opstr>, MicroMipsR6Inst16 {
 408   let hasDelaySlot = 0;
 409   let isBranch = 1;
 410   let isIndirectBranch = 1;
 411 }
 412 class JRC16_MMR6_DESC : JRC16_MMR6_DESC_BASE<"jrc16", GPR32Opnd>;
 413
 414 class JRCADDIUSP_MMR6_DESC
 415     : MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jrcaddiusp\t$imm",
 416                       [], II_JRADDIUSP, FrmR>,
 417       MMR6Arch<"jrcaddiusp">, MicroMipsR6Inst16 {
 418   let hasDelaySlot = 0;
 419   let isTerminator = 1;
 420   let isBarrier = 1;
 421   let isBranch = 1;
 422   let isIndirectBranch = 1;
 423 }
 424
 425 class ALIGN_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 426                       Operand ImmOpnd>  : MMR6Arch<instr_asm> {
 427   dag OutOperandList = (outs GPROpnd:$rd);
 428   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
 429   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
 430   list<dag> Pattern = [];
 431 }
 432
 433 class ALIGN_MMR6_DESC : ALIGN_MMR6_DESC_BASE<"align", GPR32Opnd, uimm2>;
 434
 435 class AUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 436     : MMR6Arch<instr_asm> {
 437   dag OutOperandList = (outs GPROpnd:$rt);
 438   dag InOperandList = (ins GPROpnd:$rs, simm16:$imm);
 439   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
 440   list<dag> Pattern = [];
 441 }
 442
 443 class AUI_MMR6_DESC : AUI_MMR6_DESC_BASE<"aui", GPR32Opnd>;
 444
 445 class SEB_MMR6_DESC : SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>;
 446 class SEH_MMR6_DESC : SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>;
 447 class ALUIPC_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 448     : MMR6Arch<instr_asm> {
 449   dag OutOperandList = (outs GPROpnd:$rt);
 450   dag InOperandList = (ins simm16:$imm);
 451   string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
 452   list<dag> Pattern = [];
 453 }
 454
 455 class ALUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"aluipc", GPR32Opnd>;
 456 class AUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"auipc", GPR32Opnd>;
 457
 458 class LSA_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 459                          Operand ImmOpnd> : MMR6Arch<instr_asm> {
 460   dag OutOperandList = (outs GPROpnd:$rd);
 461   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
 462   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $rd, $imm2");
 463   list<dag> Pattern = [];
 464 }
 465
 466 class LSA_MMR6_DESC : LSA_MMR6_DESC_BASE<"lsa", GPR32Opnd, uimm2_plus1>;
 467
 468 class PCREL_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 469                            Operand ImmOpnd> : MMR6Arch<instr_asm> {
 470   dag OutOperandList = (outs GPROpnd:$rt);
 471   dag InOperandList = (ins ImmOpnd:$imm);
 472   string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
 473   list<dag> Pattern = [];
 474 }
 475
 476 class ADDIUPC_MMR6_DESC : PCREL_MMR6_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2>;
 477 class LWPC_MMR6_DESC: PCREL_MMR6_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2>;
 478
 479 class SELEQNE_Z_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 480     : MMR6Arch<instr_asm> {
 481   dag OutOperandList = (outs GPROpnd:$rd);
 482   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
 483   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 484   list<dag> Pattern = [];
 485 }
 486
 487 class SELEQZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"seleqz", GPR32Opnd>;
 488 class SELNEZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"selnez", GPR32Opnd>;
 489 class PAUSE_MMR6_DESC : Barrier<"pause">;
 490 class RDHWR_MMR6_DESC : MMR6Arch<"rdhwr">, MipsR6Inst {
 491   dag OutOperandList = (outs GPR32Opnd:$rt);
 492   dag InOperandList = (ins HWRegsOpnd:$rs, uimm3:$sel);
 493   string AsmString = !strconcat("rdhwr", "\t$rt, $rs, $sel");
 494   list<dag> Pattern = [];
 495   InstrItinClass Itinerary = II_RDHWR;
 496   Format Form = FrmR;
 497 }
 498
 499 class WAIT_MMR6_DESC : WaitMM<"wait">;
 500 class SSNOP_MMR6_DESC : Barrier<"ssnop">;
 501 class SLL_MMR6_DESC : shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>;
 502 class DIV_MMR6_DESC : ArithLogicR<"div", GPR32Opnd>;
 503 class DIVU_MMR6_DESC : ArithLogicR<"divu", GPR32Opnd>;
 504 class MOD_MMR6_DESC : ArithLogicR<"mod", GPR32Opnd>;
 505 class MODU_MMR6_DESC : ArithLogicR<"modu", GPR32Opnd>;
 506 class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd>;
 507 class ANDI_MMR6_DESC : ArithLogicI<"andi", simm16, GPR32Opnd>;
 508 class NOR_MMR6_DESC : ArithLogicR<"nor", GPR32Opnd>;
 509 class OR_MMR6_DESC : ArithLogicR<"or", GPR32Opnd>;
 510 class ORI_MMR6_DESC : ArithLogicI<"ori", simm16, GPR32Opnd>;
 511 class XOR_MMR6_DESC : ArithLogicR<"xor", GPR32Opnd>;
 512 class XORI_MMR6_DESC : ArithLogicI<"xori", simm16, GPR32Opnd>;
 513
 514 class SWE_MMR6_DESC_BASE<string opstr, DAGOperand RO, DAGOperand MO,
 515                   SDPatternOperator OpNode = null_frag,
 516                   InstrItinClass Itin = NoItinerary,
 517                   ComplexPattern Addr = addr> :
 518   InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
 519          [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
 520   let DecoderMethod = "DecodeMem";
 521   let mayStore = 1;
 522 }
 523 class SW_MMR6_DESC : Store<"sw", GPR32Opnd>;
 524 class SWE_MMR6_DESC : SWE_MMR6_DESC_BASE<"swe", GPR32Opnd, mem_simm9>;
 525
 526 class WRPGPR_WSBH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO>
 527     : MMR6Arch<instr_asm> {
 528   dag InOperandList = (ins RO:$rs);
 529   dag OutOperandList = (outs RO:$rt);
 530   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
 531   list<dag> Pattern = [];
 532   Format f = FrmR;
 533   string BaseOpcode = instr_asm;
 534   bit hasSideEffects = 0;
 535 }
 536 class WRPGPR_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wrpgpr", GPR32Opnd>;
 537 class WSBH_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wsbh", GPR32Opnd>;
 538
 539 /// Floating Point Instructions
 540 class FARITH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RC,
 541                             InstrItinClass Itin, bit isComm,
 542                             SDPatternOperator OpNode = null_frag> : HARDFLOAT {
 543   dag OutOperandList = (outs RC:$fd);
 544   dag InOperandList = (ins RC:$ft, RC:$fs);
 545   string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
 546   list<dag> Pattern = [(set RC:$fd, (OpNode RC:$fs, RC:$ft))];
 547   InstrItinClass Itinerary = Itin;
 548   bit isCommutable = isComm;
 549 }
 550 class FADD_S_MMR6_DESC
 551   : FARITH_MMR6_DESC_BASE<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>;
 552 class FADD_D_MMR6_DESC
 553   : FARITH_MMR6_DESC_BASE<"add.d", AFGR64Opnd, II_ADD_D, 1, fadd>;
 554 class FSUB_S_MMR6_DESC
 555   : FARITH_MMR6_DESC_BASE<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>;
 556 class FSUB_D_MMR6_DESC
 557   : FARITH_MMR6_DESC_BASE<"sub.d", AFGR64Opnd, II_SUB_D, 0, fsub>;
 558 class FMUL_S_MMR6_DESC
 559   : FARITH_MMR6_DESC_BASE<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>;
 560 class FMUL_D_MMR6_DESC
 561   : FARITH_MMR6_DESC_BASE<"mul.d", AFGR64Opnd, II_MUL_D, 1, fmul>;
 562 class FDIV_S_MMR6_DESC
 563   : FARITH_MMR6_DESC_BASE<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>;
 564 class FDIV_D_MMR6_DESC
 565   : FARITH_MMR6_DESC_BASE<"div.d", AFGR64Opnd, II_DIV_D, 0, fdiv>;
 566 class MADDF_S_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>, HARDFLOAT;
 567 class MADDF_D_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>, HARDFLOAT;
 568 class MSUBF_S_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>, HARDFLOAT;
 569 class MSUBF_D_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>, HARDFLOAT;
 570
 571 class FMOV_FNEG_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
 572                                RegisterOperand SrcRC, InstrItinClass Itin,
 573                                SDPatternOperator OpNode = null_frag>
 574                                : HARDFLOAT, NeverHasSideEffects {
 575   dag OutOperandList = (outs DstRC:$ft);
 576   dag InOperandList = (ins SrcRC:$fs);
 577   string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
 578   list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
 579   InstrItinClass Itinerary = Itin;
 580   Format Form = FrmFR;
 581 }
 582 class FMOV_S_MMR6_DESC
 583   : FMOV_FNEG_MMR6_DESC_BASE<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>;
 584 class FMOV_D_MMR6_DESC
 585   : FMOV_FNEG_MMR6_DESC_BASE<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>;
 586 class FNEG_S_MMR6_DESC
 587   : FMOV_FNEG_MMR6_DESC_BASE<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>;
 588 class FNEG_D_MMR6_DESC
 589   : FMOV_FNEG_MMR6_DESC_BASE<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>;
 590
 591 class MAX_S_MMR6_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>, HARDFLOAT;
 592 class MAX_D_MMR6_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>, HARDFLOAT;
 593 class MIN_S_MMR6_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>, HARDFLOAT;
 594 class MIN_D_MMR6_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>, HARDFLOAT;
 595
 596 class MAXA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>, HARDFLOAT;
 597 class MAXA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>, HARDFLOAT;
 598 class MINA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>, HARDFLOAT;
 599 class MINA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>, HARDFLOAT;
 600
 601 class CVT_MMR6_DESC_BASE<
 602     string instr_asm, RegisterOperand DstRC, RegisterOperand SrcRC,
 603     InstrItinClass Itin, SDPatternOperator OpNode = null_frag>
 604     : HARDFLOAT, NeverHasSideEffects {
 605   dag OutOperandList = (outs DstRC:$ft);
 606   dag InOperandList = (ins SrcRC:$fs);
 607   string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
 608   list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
 609   InstrItinClass Itinerary = Itin;
 610   Format Form = FrmFR;
 611 }
 612
 613 class CVT_L_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.s", FGR64Opnd, FGR32Opnd,
 614                                              II_CVT>;
 615 class CVT_L_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.d", FGR64Opnd, FGR64Opnd,
 616                                              II_CVT>;
 617 class CVT_W_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.s", FGR32Opnd, FGR32Opnd,
 618                                              II_CVT>;
 619 class CVT_W_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.d", FGR32Opnd, AFGR64Opnd,
 620                                              II_CVT>;
 621 class CVT_D_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.s", FGR32Opnd, AFGR64Opnd,
 622                                              II_CVT>;
 623 class CVT_D_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.w", FGR32Opnd, AFGR64Opnd,
 624                                              II_CVT>;
 625 class CVT_D_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.l", FGR64Opnd, FGR64Opnd,
 626                                              II_CVT>, FGR_64;
 627 class CVT_S_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.d", AFGR64Opnd, FGR32Opnd,
 628                                              II_CVT>;
 629 class CVT_S_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.w", FGR32Opnd, FGR32Opnd,
 630                                              II_CVT>;
 631 class CVT_S_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.l", FGR64Opnd, FGR32Opnd,
 632                                              II_CVT>, FGR_64;
 633
 634 multiclass CMP_CC_MMR6<bits<6> format, string Typestr,
 635                        RegisterOperand FGROpnd> {
 636   def CMP_AF_#NAME : POOL32F_CMP_FM<
 637       !strconcat("cmp.af.", Typestr), format, FIELD_CMP_COND_AF>,
 638       CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 639       ISA_MICROMIPS32R6;
 640   def CMP_UN_#NAME : POOL32F_CMP_FM<
 641       !strconcat("cmp.un.", Typestr), format, FIELD_CMP_COND_UN>,
 642       CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 643       ISA_MICROMIPS32R6;
 644   def CMP_EQ_#NAME : POOL32F_CMP_FM<
 645       !strconcat("cmp.eq.", Typestr), format, FIELD_CMP_COND_EQ>,
 646       CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 647       ISA_MICROMIPS32R6;
 648   def CMP_UEQ_#NAME : POOL32F_CMP_FM<
 649       !strconcat("cmp.ueq.", Typestr), format, FIELD_CMP_COND_UEQ>,
 650       CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 651       ISA_MICROMIPS32R6;
 652   def CMP_LT_#NAME : POOL32F_CMP_FM<
 653       !strconcat("cmp.lt.", Typestr), format, FIELD_CMP_COND_LT>,
 654       CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 655       ISA_MICROMIPS32R6;
 656   def CMP_ULT_#NAME : POOL32F_CMP_FM<
 657       !strconcat("cmp.ult.", Typestr), format, FIELD_CMP_COND_ULT>,
 658       CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 659       ISA_MICROMIPS32R6;
 660   def CMP_LE_#NAME : POOL32F_CMP_FM<
 661       !strconcat("cmp.le.", Typestr), format, FIELD_CMP_COND_LE>,
 662       CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 663       ISA_MICROMIPS32R6;
 664   def CMP_ULE_#NAME : POOL32F_CMP_FM<
 665       !strconcat("cmp.ule.", Typestr), format, FIELD_CMP_COND_ULE>,
 666       CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 667       ISA_MICROMIPS32R6;
 668   def CMP_SAF_#NAME : POOL32F_CMP_FM<
 669       !strconcat("cmp.saf.", Typestr), format, FIELD_CMP_COND_SAF>,
 670       CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 671       ISA_MICROMIPS32R6;
 672   def CMP_SUN_#NAME : POOL32F_CMP_FM<
 673       !strconcat("cmp.sun.", Typestr), format, FIELD_CMP_COND_SUN>,
 674       CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 675       ISA_MICROMIPS32R6;
 676   def CMP_SEQ_#NAME : POOL32F_CMP_FM<
 677       !strconcat("cmp.seq.", Typestr), format, FIELD_CMP_COND_SEQ>,
 678       CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 679       ISA_MICROMIPS32R6;
 680   def CMP_SUEQ_#NAME : POOL32F_CMP_FM<
 681       !strconcat("cmp.sueq.", Typestr), format, FIELD_CMP_COND_SUEQ>,
 682       CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 683       ISA_MICROMIPS32R6;
 684   def CMP_SLT_#NAME : POOL32F_CMP_FM<
 685       !strconcat("cmp.slt.", Typestr), format, FIELD_CMP_COND_SLT>,
 686       CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 687       ISA_MICROMIPS32R6;
 688   def CMP_SULT_#NAME : POOL32F_CMP_FM<
 689       !strconcat("cmp.sult.", Typestr), format, FIELD_CMP_COND_SULT>,
 690       CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 691       ISA_MICROMIPS32R6;
 692   def CMP_SLE_#NAME : POOL32F_CMP_FM<
 693       !strconcat("cmp.sle.", Typestr), format, FIELD_CMP_COND_SLE>,
 694       CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 695       ISA_MICROMIPS32R6;
 696   def CMP_SULE_#NAME : POOL32F_CMP_FM<
 697       !strconcat("cmp.sule.", Typestr), format, FIELD_CMP_COND_SULE>,
 698       CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 699       ISA_MICROMIPS32R6;
 700 }
 701
 702 class ABSS_FT_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
 703                              RegisterOperand SrcRC, InstrItinClass Itin,
 704                              SDPatternOperator OpNode = null_frag>
 705     : HARDFLOAT, NeverHasSideEffects {
 706   dag OutOperandList = (outs DstRC:$ft);
 707   dag InOperandList  = (ins SrcRC:$fs);
 708   string AsmString   = !strconcat(instr_asm, "\t$ft, $fs");
 709   list<dag>  Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
 710   InstrItinClass Itinerary = Itin;
 711   Format Form = FrmFR;
 712   list<Predicate> EncodingPredicates = [HasStdEnc];
 713 }
 714
 715 class ABS_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.s", FGR32Opnd, FGR32Opnd,
 716                                                 II_ABS, fabs>;
 717 class ABS_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.d", AFGR64Opnd, AFGR64Opnd,
 718                                                 II_ABS, fabs>;
 719 class FLOOR_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.s", FGR64Opnd,
 720                                                     FGR32Opnd, II_FLOOR>;
 721 class FLOOR_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.d", FGR64Opnd,
 722                                                     FGR64Opnd, II_FLOOR>;
 723 class FLOOR_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.s", FGR32Opnd,
 724                                                     FGR32Opnd, II_FLOOR>;
 725 class FLOOR_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.d", FGR32Opnd,
 726                                                     AFGR64Opnd, II_FLOOR>;
 727 class CEIL_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.s", FGR64Opnd,
 728                                                    FGR32Opnd, II_CEIL>;
 729 class CEIL_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.d", FGR64Opnd,
 730                                                    FGR64Opnd, II_CEIL>;
 731 class CEIL_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.s", FGR32Opnd,
 732                                                    FGR32Opnd, II_CEIL>;
 733 class CEIL_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.d", FGR32Opnd,
 734                                                    AFGR64Opnd, II_CEIL>;
 735 class TRUNC_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.s", FGR64Opnd,
 736                                                     FGR32Opnd, II_TRUNC>;
 737 class TRUNC_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.d", FGR64Opnd,
 738                                                     FGR64Opnd, II_TRUNC>;
 739 class TRUNC_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.s", FGR32Opnd,
 740                                                     FGR32Opnd, II_TRUNC>;
 741 class TRUNC_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.d", FGR32Opnd,
 742                                                     AFGR64Opnd, II_TRUNC>;
 743 class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.s", FGR32Opnd, FGR32Opnd,
 744                                                  II_SQRT_S, fsqrt>;
 745 class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd, AFGR64Opnd,
 746                                                  II_SQRT_D, fsqrt>;
 747 class RSQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.s", FGR32Opnd,
 748                                                   FGR32Opnd, II_TRUNC>;
 749 class RSQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.d", FGR32Opnd,
 750                                                   AFGR64Opnd, II_TRUNC>;
 751 class RECIP_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"recip.s", FGR32Opnd,
 752                                                  FGR32Opnd, II_ROUND>;
 753 class RECIP_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"recip.d", FGR32Opnd, FGR32Opnd,
 754                                                  II_ROUND>;
 755 class ROUND_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.s", FGR64Opnd,
 756                                                    FGR32Opnd, II_ROUND>;
 757 class ROUND_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.d", FGR64Opnd,
 758                                                    FGR64Opnd, II_ROUND>;
 759 class ROUND_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.s", FGR32Opnd,
 760                                                    FGR32Opnd, II_ROUND>;
 761 class ROUND_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.d", FGR64Opnd,
 762                                                    FGR64Opnd, II_ROUND>;
 763
 764 class SEL_S_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd>;
 765 class SEL_D_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd> {
 766   // We must insert a SUBREG_TO_REG around $fd_in
 767   bit usesCustomInserter = 1;
 768 }
 769
 770 class SELEQZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>;
 771 class SELEQZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>;
 772 class SELENZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>;
 773 class SELENZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>;
 774 class RINT_S_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>;
 775 class RINT_D_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>;
 776 class CLASS_S_MMR6_DESC  : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>;
 777 class CLASS_D_MMR6_DESC  : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>;
 778
 779 class STORE_MMR6_DESC_BASE<string opstr, DAGOperand RO>
 780     : Store<opstr, RO>, MMR6Arch<opstr> {
 781   let DecoderMethod = "DecodeMemMMImm16";
 782 }
 783 class SB_MMR6_DESC : STORE_MMR6_DESC_BASE<"sb", GPR32Opnd>;
 784
 785 class STORE_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO>
 786     : MMR6Arch<instr_asm>, MipsR6Inst {
 787   dag OutOperandList = (outs);
 788   dag InOperandList = (ins RO:$rt, mem_mm_9:$addr);
 789   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
 790   string DecoderMethod = "DecodeStoreEvaOpMM";
 791   bit mayStore = 1;
 792 }
 793 class SBE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sbe", GPR32Opnd>;
 794 class SCE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sce", GPR32Opnd>;
 795 class SH_MMR6_DESC : STORE_MMR6_DESC_BASE<"sh", GPR32Opnd>;
 796 class SHE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"she", GPR32Opnd>;
 797 class LOAD_WORD_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO> :
 798             MMR6Arch<instr_asm>, MipsR6Inst {
 799   dag OutOperandList = (outs RO:$rt);
 800   dag InOperandList = (ins mem_mm_12:$addr);
 801   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
 802   string DecoderMethod = "DecodeMemMMImm9";
 803   bit mayLoad = 1;
 804 }
 805 class LLE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lle", GPR32Opnd>;
 806 class LWE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lwe", GPR32Opnd>;
 807 class ADDU16_MMR6_DESC : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
 808       MMR6Arch<"addu16">;
 809 class AND16_MMR6_DESC : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
 810       MMR6Arch<"and16">;
 811 class ANDI16_MMR6_DESC : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>,
 812       MMR6Arch<"andi16">;
 813 class NOT16_MMR6_DESC : NotMM16<"not16", GPRMM16Opnd>, MMR6Arch<"not16">;
 814 class OR16_MMR6_DESC : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,
 815       MMR6Arch<"or16">;
 816 class SLL16_MMR6_DESC : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
 817       MMR6Arch<"sll16">;
 818 class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
 819       MMR6Arch<"srl16">;
 820 class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16">, MMR6Arch<"srl16">,
 821       MicroMipsR6Inst16;
 822 class LI16_MMR6_DESC : LoadImmMM16<"li16", li_simm7, GPRMM16Opnd>,
 823       MMR6Arch<"srl16">, MicroMipsR6Inst16, IsAsCheapAsAMove;
 824 class MOVE16_MMR6_DESC : MoveMM16<"move16", GPR32Opnd>, MMR6Arch<"srl16">,
 825       MicroMipsR6Inst16;
 826 class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16">, MMR6Arch<"sdbbp16">,
 827       MicroMipsR6Inst16;
 828 class SUBU16_MMR6_DESC : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
 829       MMR6Arch<"sdbbp16">, MicroMipsR6Inst16;
 830 class XOR16_MMR6_DESC : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
 831       MMR6Arch<"sdbbp16">, MicroMipsR6Inst16;
 832
 833 class LW_MMR6_DESC : MMR6Arch<"lw">, MipsR6Inst {
 834   dag OutOperandList = (outs GPR32Opnd:$rt);
 835   dag InOperandList = (ins mem:$addr);
 836   string AsmString = "lw\t$rt, $addr";
 837   let DecoderMethod = "DecodeMemMMImm16";
 838   let canFoldAsLoad = 1;
 839   let mayLoad = 1;
 840   list<dag> Pattern = [(set GPR32Opnd:$rt, (load addrDefault:$addr))];
 841   InstrItinClass Itinerary = II_LW;
 842 }
 843
 844 class LUI_MMR6_DESC : IsAsCheapAsAMove, MMR6Arch<"lui">, MipsR6Inst{
 845   dag OutOperandList = (outs GPR32Opnd:$rt);
 846   dag InOperandList = (ins uimm16:$imm16);
 847   string AsmString = "lui\t$rt, $imm16";
 848   list<dag> Pattern = [];
 849   bit hasSideEffects = 0;
 850   bit isReMaterializable = 1;
 851   InstrItinClass Itinerary = II_LUI;
 852   Format Form = FrmI;
 853 }
 854
 855 class SYNC_MMR6_DESC : MMR6Arch<"sync">, MipsR6Inst {
 856   dag OutOperandList = (outs);
 857   dag InOperandList = (ins i32imm:$stype);
 858   string AsmString = !strconcat("sync", "\t$stype");
 859   list<dag> Pattern = [(MipsSync imm:$stype)];
 860   InstrItinClass Itinerary = NoItinerary;
 861   bit HasSideEffects = 1;
 862 }
 863
 864 class SYNCI_MMR6_DESC : SYNCI_FT<"synci"> {
 865   let DecoderMethod = "DecodeSynciR6";
 866 }
 867
 868 class RDPGPR_MMR6_DESC : MMR6Arch<"rdpgpr">, MipsR6Inst {
 869   dag OutOperandList = (outs GPR32Opnd:$rt);
 870   dag InOperandList = (ins GPR32Opnd:$rd);
 871   string AsmString = !strconcat("rdpgpr", "\t$rt, $rd");
 872 }
 873
 874 class SDBBP_MMR6_DESC : MipsR6Inst {
 875   dag OutOperandList = (outs);
 876   dag InOperandList = (ins uimm20:$code_);
 877   string AsmString = !strconcat("sdbbp", "\t$code_");
 878   list<dag> Pattern = [];
 879 }
 880
 881 class LWM16_MMR6_DESC
 882     : MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),
 883                       !strconcat("lwm16", "\t$rt, $addr"), [],
 884                       NoItinerary, FrmI>,
 885       MMR6Arch<"lwm16">, MicroMipsR6Inst16 {
 886   let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
 887   let mayLoad = 1;
 888   InstrItinClass Itin = NoItinerary;
 889   ComplexPattern Addr = addr;
 890 }
 891
 892 class SWM16_MMR6_DESC
 893     : MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr),
 894                       !strconcat("swm16", "\t$rt, $addr"), [],
 895                       NoItinerary, FrmI>,
 896       MMR6Arch<"swm16">, MicroMipsR6Inst16 {
 897   let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
 898   let mayStore = 1;
 899   InstrItinClass Itin = NoItinerary;
 900   ComplexPattern Addr = addr;
 901 }
 902
 903 class SB16_MMR6_DESC_BASE<string opstr, DAGOperand RTOpnd, DAGOperand RO,
 904                           SDPatternOperator OpNode, InstrItinClass Itin,
 905                           Operand MemOpnd>
 906     : MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),
 907                       !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI>,
 908       MMR6Arch<opstr>, MicroMipsR6Inst16 {
 909   let DecoderMethod = "DecodeMemMMImm4";
 910   let mayStore = 1;
 911 }
 912 class SB16_MMR6_DESC : SB16_MMR6_DESC_BASE<"sb16", GPRMM16OpndZero, GPRMM16Opnd,
 913                                            truncstorei8, II_SB, mem_mm_4>;
 914 class SH16_MMR6_DESC : SB16_MMR6_DESC_BASE<"sh16", GPRMM16OpndZero, GPRMM16Opnd,
 915                                            truncstorei16, II_SH, mem_mm_4_lsl1>;
 916 class SW16_MMR6_DESC : SB16_MMR6_DESC_BASE<"sw16", GPRMM16OpndZero, GPRMM16Opnd,
 917                                            store, II_SW, mem_mm_4_lsl2>;
 918
 919 class SWSP_MMR6_DESC
 920     : MicroMipsInst16<(outs), (ins GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset),
 921                       !strconcat("sw", "\t$rt, $offset"), [], II_SW, FrmI>,
 922       MMR6Arch<"sw">, MicroMipsR6Inst16 {
 923   let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
 924   let mayStore = 1;
 925 }
 926
 927 //===----------------------------------------------------------------------===//
 928 //
 929 // Instruction Definitions
 930 //
 931 //===----------------------------------------------------------------------===//
 932
 933 let DecoderNamespace = "MicroMipsR6" in {
 934 def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6;
 935 def ADDIU_MMR6 : StdMMR6Rel, ADDIU_MMR6_DESC, ADDIU_MMR6_ENC, ISA_MICROMIPS32R6;
 936 def ADDU_MMR6 : StdMMR6Rel, ADDU_MMR6_DESC, ADDU_MMR6_ENC, ISA_MICROMIPS32R6;
 937 def ADDIUPC_MMR6 : R6MMR6Rel, ADDIUPC_MMR6_ENC, ADDIUPC_MMR6_DESC,
 938                    ISA_MICROMIPS32R6;
 939 def ALUIPC_MMR6 : R6MMR6Rel, ALUIPC_MMR6_ENC, ALUIPC_MMR6_DESC,
 940                   ISA_MICROMIPS32R6;
 941 def AND_MMR6 : StdMMR6Rel, AND_MMR6_DESC, AND_MMR6_ENC, ISA_MICROMIPS32R6;
 942 def ANDI_MMR6 : StdMMR6Rel, ANDI_MMR6_DESC, ANDI_MMR6_ENC, ISA_MICROMIPS32R6;
 943 def AUIPC_MMR6 : R6MMR6Rel, AUIPC_MMR6_ENC, AUIPC_MMR6_DESC, ISA_MICROMIPS32R6;
 944 def ALIGN_MMR6 : R6MMR6Rel, ALIGN_MMR6_ENC, ALIGN_MMR6_DESC, ISA_MICROMIPS32R6;
 945 def AUI_MMR6 : R6MMR6Rel, AUI_MMR6_ENC, AUI_MMR6_DESC, ISA_MICROMIPS32R6;
 946 def BALC_MMR6 : R6MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPS32R6;
 947 def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6;
 948 def BC16_MMR6 : StdMMR6Rel, BC16_MMR6_DESC, BC16_MMR6_ENC, ISA_MICROMIPS32R6;
 949 def BEQZC16_MMR6 : StdMMR6Rel, BEQZC16_MMR6_DESC, BEQZC16_MMR6_ENC,
 950                    ISA_MICROMIPS32R6;
 951 def BNEZC16_MMR6 : StdMMR6Rel, BNEZC16_MMR6_DESC, BNEZC16_MMR6_ENC,
 952                    ISA_MICROMIPS32R6;
 953 def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC,
 954                    ISA_MICROMIPS32R6;
 955 def BEQZALC_MMR6 : R6MMR6Rel, BEQZALC_MMR6_ENC, BEQZALC_MMR6_DESC,
 956                    ISA_MICROMIPS32R6;
 957 def BGEZALC_MMR6 : R6MMR6Rel, BGEZALC_MMR6_ENC, BGEZALC_MMR6_DESC,
 958                    ISA_MICROMIPS32R6;
 959 def BGTZALC_MMR6 : R6MMR6Rel, BGTZALC_MMR6_ENC, BGTZALC_MMR6_DESC,
 960                    ISA_MICROMIPS32R6;
 961 def BLEZALC_MMR6 : R6MMR6Rel, BLEZALC_MMR6_ENC, BLEZALC_MMR6_DESC,
 962                    ISA_MICROMIPS32R6;
 963 def BLTZALC_MMR6 : R6MMR6Rel, BLTZALC_MMR6_ENC, BLTZALC_MMR6_DESC,
 964                    ISA_MICROMIPS32R6;
 965 def BNEZALC_MMR6 : R6MMR6Rel, BNEZALC_MMR6_ENC, BNEZALC_MMR6_DESC,
 966                    ISA_MICROMIPS32R6;
 967 def BREAK_MMR6 : StdMMR6Rel, BRK_MMR6_DESC, BRK_MMR6_ENC, ISA_MICROMIPS32R6;
 968 def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6;
 969 def CLO_MMR6 : R6MMR6Rel, CLO_MMR6_ENC, CLO_MMR6_DESC, ISA_MICROMIPS32R6;
 970 def CLZ_MMR6 : R6MMR6Rel, CLZ_MMR6_ENC, CLZ_MMR6_DESC, ISA_MICROMIPS32R6;
 971 def DIV_MMR6 : R6MMR6Rel, DIV_MMR6_DESC, DIV_MMR6_ENC, ISA_MICROMIPS32R6;
 972 def DIVU_MMR6 : R6MMR6Rel, DIVU_MMR6_DESC, DIVU_MMR6_ENC, ISA_MICROMIPS32R6;
 973 def EHB_MMR6 : StdMMR6Rel, EHB_MMR6_DESC, EHB_MMR6_ENC, ISA_MICROMIPS32R6;
 974 def EI_MMR6 : StdMMR6Rel, EI_MMR6_DESC, EI_MMR6_ENC, ISA_MICROMIPS32R6;
 975 def DI_MMR6 : StdMMR6Rel, DI_MMR6_DESC, DI_MMR6_ENC, ISA_MICROMIPS32R6;
 976 def ERET_MMR6 : StdMMR6Rel, ERET_MMR6_DESC, ERET_MMR6_ENC, ISA_MICROMIPS32R6;
 977 def DERET_MMR6 : StdMMR6Rel, DERET_MMR6_DESC, DERET_MMR6_ENC, ISA_MICROMIPS32R6;
 978 def ERETNC_MMR6 : R6MMR6Rel, ERETNC_MMR6_DESC, ERETNC_MMR6_ENC,
 979                   ISA_MICROMIPS32R6;
 980 def JALRC16_MMR6 : R6MMR6Rel, JALRC16_MMR6_DESC, JALRC16_MMR6_ENC,
 981                    ISA_MICROMIPS32R6;
 982 def JIALC_MMR6 : R6MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPS32R6;
 983 def JIC_MMR6 : R6MMR6Rel, JIC_MMR6_ENC, JIC_MMR6_DESC, ISA_MICROMIPS32R6;
 984 def JRC16_MMR6 : R6MMR6Rel, JRC16_MMR6_DESC, JRC16_MMR6_ENC, ISA_MICROMIPS32R6;
 985 def JRCADDIUSP_MMR6 : R6MMR6Rel, JRCADDIUSP_MMR6_DESC, JRCADDIUSP_MMR6_ENC,
 986                       ISA_MICROMIPS32R6;
 987 def LSA_MMR6 : R6MMR6Rel, LSA_MMR6_ENC, LSA_MMR6_DESC, ISA_MICROMIPS32R6;
 988 def LWPC_MMR6 : R6MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPS32R6;
 989 def LWM16_MMR6 : StdMMR6Rel, LWM16_MMR6_DESC, LWM16_MMR6_ENC, ISA_MICROMIPS32R6;
 990 def MOD_MMR6 : R6MMR6Rel, MOD_MMR6_DESC, MOD_MMR6_ENC, ISA_MICROMIPS32R6;
 991 def MODU_MMR6 : R6MMR6Rel, MODU_MMR6_DESC, MODU_MMR6_ENC, ISA_MICROMIPS32R6;
 992 def MUL_MMR6 : R6MMR6Rel, MUL_MMR6_DESC, MUL_MMR6_ENC, ISA_MICROMIPS32R6;
 993 def MUH_MMR6 : R6MMR6Rel, MUH_MMR6_DESC, MUH_MMR6_ENC, ISA_MICROMIPS32R6;
 994 def MULU_MMR6 : R6MMR6Rel, MULU_MMR6_DESC, MULU_MMR6_ENC, ISA_MICROMIPS32R6;
 995 def MUHU_MMR6 : R6MMR6Rel, MUHU_MMR6_DESC, MUHU_MMR6_ENC, ISA_MICROMIPS32R6;
 996 def NOR_MMR6 : StdMMR6Rel, NOR_MMR6_DESC, NOR_MMR6_ENC, ISA_MICROMIPS32R6;
 997 def OR_MMR6 : StdMMR6Rel, OR_MMR6_DESC, OR_MMR6_ENC, ISA_MICROMIPS32R6;
 998 def ORI_MMR6 : StdMMR6Rel, ORI_MMR6_DESC, ORI_MMR6_ENC, ISA_MICROMIPS32R6;
 999 def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6;
1000 def SB16_MMR6 : StdMMR6Rel, SB16_MMR6_DESC, SB16_MMR6_ENC, ISA_MICROMIPS32R6;
1001 def SEB_MMR6 : StdMMR6Rel, SEB_MMR6_DESC, SEB_MMR6_ENC, ISA_MICROMIPS32R6;
1002 def SEH_MMR6 : StdMMR6Rel, SEH_MMR6_DESC, SEH_MMR6_ENC, ISA_MICROMIPS32R6;
1003 def SELEQZ_MMR6 : R6MMR6Rel, SELEQZ_MMR6_ENC, SELEQZ_MMR6_DESC,
1004                   ISA_MICROMIPS32R6;
1005 def SELNEZ_MMR6 : R6MMR6Rel, SELNEZ_MMR6_ENC, SELNEZ_MMR6_DESC,
1006                   ISA_MICROMIPS32R6;
1007 def SH16_MMR6 : StdMMR6Rel, SH16_MMR6_DESC, SH16_MMR6_ENC, ISA_MICROMIPS32R6;
1008 def SLL_MMR6 : StdMMR6Rel, SLL_MMR6_DESC, SLL_MMR6_ENC, ISA_MICROMIPS32R6;
1009 def SUB_MMR6 : StdMMR6Rel, SUB_MMR6_DESC, SUB_MMR6_ENC, ISA_MICROMIPS32R6;
1010 def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6;
1011 def SW16_MMR6 : StdMMR6Rel, SW16_MMR6_DESC, SW16_MMR6_ENC, ISA_MICROMIPS32R6;
1012 def SWM16_MMR6 : StdMMR6Rel, SWM16_MMR6_DESC, SWM16_MMR6_ENC, ISA_MICROMIPS32R6;
1013 def SWSP_MMR6 : StdMMR6Rel, SWSP_MMR6_DESC, SWSP_MMR6_ENC, ISA_MICROMIPS32R6;
1014 def PREFE_MMR6 : StdMMR6Rel, PREFE_MMR6_ENC, PREFE_MMR6_DESC, ISA_MICROMIPS32R6;
1015 def CACHEE_MMR6 : StdMMR6Rel, CACHEE_MMR6_ENC, CACHEE_MMR6_DESC,
1016                   ISA_MICROMIPS32R6;
1017 def WRPGPR_MMR6 : StdMMR6Rel, WRPGPR_MMR6_ENC, WRPGPR_MMR6_DESC,
1018                   ISA_MICROMIPS32R6;
1019 def WSBH_MMR6 : StdMMR6Rel, WSBH_MMR6_ENC, WSBH_MMR6_DESC, ISA_MICROMIPS32R6;
1020 def LB_MMR6 : R6MMR6Rel, LB_MMR6_ENC, LB_MMR6_DESC, ISA_MICROMIPS32R6;
1021 def LBU_MMR6 : R6MMR6Rel, LBU_MMR6_ENC, LBU_MMR6_DESC, ISA_MICROMIPS32R6;
1022 def LBE_MMR6 : R6MMR6Rel, LBE_MMR6_ENC, LBE_MMR6_DESC, ISA_MICROMIPS32R6;
1023 def LBUE_MMR6 : R6MMR6Rel, LBUE_MMR6_ENC, LBUE_MMR6_DESC, ISA_MICROMIPS32R6;
1024 def PAUSE_MMR6 : StdMMR6Rel, PAUSE_MMR6_DESC, PAUSE_MMR6_ENC, ISA_MICROMIPS32R6;
1025 def RDHWR_MMR6 : R6MMR6Rel, RDHWR_MMR6_DESC, RDHWR_MMR6_ENC, ISA_MICROMIPS32R6;
1026 def WAIT_MMR6 : StdMMR6Rel, WAIT_MMR6_DESC, WAIT_MMR6_ENC, ISA_MICROMIPS32R6;
1027 def SSNOP_MMR6 : StdMMR6Rel, SSNOP_MMR6_DESC, SSNOP_MMR6_ENC, ISA_MICROMIPS32R6;
1028 def SYNC_MMR6 : StdMMR6Rel, SYNC_MMR6_DESC, SYNC_MMR6_ENC, ISA_MICROMIPS32R6;
1029 def SYNCI_MMR6 : StdMMR6Rel, SYNCI_MMR6_DESC, SYNCI_MMR6_ENC, ISA_MICROMIPS32R6;
1030 def RDPGPR_MMR6 : R6MMR6Rel, RDPGPR_MMR6_DESC, RDPGPR_MMR6_ENC,
1031                   ISA_MICROMIPS32R6;
1032 def SDBBP_MMR6 : R6MMR6Rel, SDBBP_MMR6_DESC, SDBBP_MMR6_ENC, ISA_MICROMIPS32R6;
1033 def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6;
1034 def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6;
1035 let DecoderMethod = "DecodeMemMMImm16" in {
1036   def SW_MMR6 : StdMMR6Rel, SW_MMR6_DESC, SW_MMR6_ENC, ISA_MICROMIPS32R6;
1037 }
1038 let DecoderMethod = "DecodeMemMMImm9" in {
1039   def SWE_MMR6 : StdMMR6Rel, SWE_MMR6_DESC, SWE_MMR6_ENC, ISA_MICROMIPS32R6;
1040 }
1041 /// Floating Point Instructions
1042 def FADD_S_MMR6 : StdMMR6Rel, FADD_S_MMR6_ENC, FADD_S_MMR6_DESC,
1043                   ISA_MICROMIPS32R6;
1044 def FADD_D_MMR6 : StdMMR6Rel, FADD_D_MMR6_ENC, FADD_D_MMR6_DESC,
1045                   ISA_MICROMIPS32R6;
1046 def FSUB_S_MMR6 : StdMMR6Rel, FSUB_S_MMR6_ENC, FSUB_S_MMR6_DESC,
1047                   ISA_MICROMIPS32R6;
1048 def FSUB_D_MMR6 : StdMMR6Rel, FSUB_D_MMR6_ENC, FSUB_D_MMR6_DESC,
1049                   ISA_MICROMIPS32R6;
1050 def FMUL_S_MMR6 : StdMMR6Rel, FMUL_S_MMR6_ENC, FMUL_S_MMR6_DESC,
1051                   ISA_MICROMIPS32R6;
1052 def FMUL_D_MMR6 : StdMMR6Rel, FMUL_D_MMR6_ENC, FMUL_D_MMR6_DESC,
1053                   ISA_MICROMIPS32R6;
1054 def FDIV_S_MMR6 : StdMMR6Rel, FDIV_S_MMR6_ENC, FDIV_S_MMR6_DESC,
1055                   ISA_MICROMIPS32R6;
1056 def FDIV_D_MMR6 : StdMMR6Rel, FDIV_D_MMR6_ENC, FDIV_D_MMR6_DESC,
1057                   ISA_MICROMIPS32R6;
1058 def MADDF_S_MMR6 : R6MMR6Rel, MADDF_S_MMR6_ENC, MADDF_S_MMR6_DESC,
1059                    ISA_MICROMIPS32R6;
1060 def MADDF_D_MMR6 : R6MMR6Rel, MADDF_D_MMR6_ENC, MADDF_D_MMR6_DESC,
1061                    ISA_MICROMIPS32R6;
1062 def MSUBF_S_MMR6 : R6MMR6Rel, MSUBF_S_MMR6_ENC, MSUBF_S_MMR6_DESC,
1063                    ISA_MICROMIPS32R6;
1064 def MSUBF_D_MMR6 : R6MMR6Rel, MSUBF_D_MMR6_ENC, MSUBF_D_MMR6_DESC,
1065                    ISA_MICROMIPS32R6;
1066 def FMOV_S_MMR6 : StdMMR6Rel, FMOV_S_MMR6_ENC, FMOV_S_MMR6_DESC,
1067                   ISA_MICROMIPS32R6;
1068 def FMOV_D_MMR6 : StdMMR6Rel, FMOV_D_MMR6_ENC, FMOV_D_MMR6_DESC,
1069                   ISA_MICROMIPS32R6;
1070 def FNEG_S_MMR6 : StdMMR6Rel, FNEG_S_MMR6_ENC, FNEG_S_MMR6_DESC,
1071                   ISA_MICROMIPS32R6;
1072 def FNEG_D_MMR6 : StdMMR6Rel, FNEG_D_MMR6_ENC, FNEG_D_MMR6_DESC,
1073                   ISA_MICROMIPS32R6;
1074 def MAX_S_MMR6 : R6MMR6Rel, MAX_S_MMR6_ENC, MAX_S_MMR6_DESC, ISA_MICROMIPS32R6;
1075 def MAX_D_MMR6 : R6MMR6Rel, MAX_D_MMR6_ENC, MAX_D_MMR6_DESC, ISA_MICROMIPS32R6;
1076 def MIN_S_MMR6 : R6MMR6Rel, MIN_S_MMR6_ENC, MIN_S_MMR6_DESC, ISA_MICROMIPS32R6;
1077 def MIN_D_MMR6 : R6MMR6Rel, MIN_D_MMR6_ENC, MIN_D_MMR6_DESC, ISA_MICROMIPS32R6;
1078 def MAXA_S_MMR6 : R6MMR6Rel, MAXA_S_MMR6_ENC, MAXA_S_MMR6_DESC,
1079                   ISA_MICROMIPS32R6;
1080 def MAXA_D_MMR6 : R6MMR6Rel, MAXA_D_MMR6_ENC, MAXA_D_MMR6_DESC,
1081                   ISA_MICROMIPS32R6;
1082 def MINA_S_MMR6 : R6MMR6Rel, MINA_S_MMR6_ENC, MINA_S_MMR6_DESC,
1083                   ISA_MICROMIPS32R6;
1084 def MINA_D_MMR6 : R6MMR6Rel, MINA_D_MMR6_ENC, MINA_D_MMR6_DESC,
1085                   ISA_MICROMIPS32R6;
1086 def CVT_L_S_MMR6 : StdMMR6Rel, CVT_L_S_MMR6_ENC, CVT_L_S_MMR6_DESC,
1087                    ISA_MICROMIPS32R6;
1088 def CVT_L_D_MMR6 : StdMMR6Rel, CVT_L_D_MMR6_ENC, CVT_L_D_MMR6_DESC,
1089                    ISA_MICROMIPS32R6;
1090 def CVT_W_S_MMR6 : StdMMR6Rel, CVT_W_S_MMR6_ENC, CVT_W_S_MMR6_DESC,
1091                    ISA_MICROMIPS32R6;
1092 def CVT_W_D_MMR6 : StdMMR6Rel, CVT_W_D_MMR6_ENC, CVT_W_D_MMR6_DESC,
1093                    ISA_MICROMIPS32R6;
1094 def CVT_D_S_MMR6 : StdMMR6Rel, CVT_D_S_MMR6_ENC, CVT_D_S_MMR6_DESC,
1095                    ISA_MICROMIPS32R6;
1096 def CVT_D_W_MMR6 : StdMMR6Rel, CVT_D_W_MMR6_ENC, CVT_D_W_MMR6_DESC,
1097                    ISA_MICROMIPS32R6;
1098 def CVT_D_L_MMR6 : StdMMR6Rel, CVT_D_L_MMR6_ENC, CVT_D_L_MMR6_DESC,
1099                    ISA_MICROMIPS32R6;
1100 def CVT_S_D_MMR6 : StdMMR6Rel, CVT_S_D_MMR6_ENC, CVT_S_D_MMR6_DESC,
1101                    ISA_MICROMIPS32R6;
1102 def CVT_S_W_MMR6 : StdMMR6Rel, CVT_S_W_MMR6_ENC, CVT_S_W_MMR6_DESC,
1103                    ISA_MICROMIPS32R6;
1104 def CVT_S_L_MMR6 : StdMMR6Rel, CVT_S_L_MMR6_ENC, CVT_S_L_MMR6_DESC,
1105                    ISA_MICROMIPS32R6;
1106 defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd>;
1107 defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd>;
1108 def ABS_S_MMR6 : StdMMR6Rel, ABS_S_MMR6_ENC, ABS_S_MMR6_DESC, ISA_MICROMIPS32R6;
1109 def ABS_D_MMR6 : StdMMR6Rel, ABS_D_MMR6_ENC, ABS_D_MMR6_DESC, ISA_MICROMIPS32R6;
1110 def FLOOR_L_S_MMR6 : StdMMR6Rel, FLOOR_L_S_MMR6_ENC, FLOOR_L_S_MMR6_DESC,
1111                      ISA_MICROMIPS32R6;
1112 def FLOOR_L_D_MMR6 : StdMMR6Rel, FLOOR_L_D_MMR6_ENC, FLOOR_L_D_MMR6_DESC,
1113                      ISA_MICROMIPS32R6;
1114 def FLOOR_W_S_MMR6 : StdMMR6Rel, FLOOR_W_S_MMR6_ENC, FLOOR_W_S_MMR6_DESC,
1115                      ISA_MICROMIPS32R6;
1116 def FLOOR_W_D_MMR6 : StdMMR6Rel, FLOOR_W_D_MMR6_ENC, FLOOR_W_D_MMR6_DESC,
1117                      ISA_MICROMIPS32R6;
1118 def CEIL_L_S_MMR6 : StdMMR6Rel, CEIL_L_S_MMR6_ENC, CEIL_L_S_MMR6_DESC,
1119                     ISA_MICROMIPS32R6;
1120 def CEIL_L_D_MMR6 : StdMMR6Rel, CEIL_L_D_MMR6_ENC, CEIL_L_D_MMR6_DESC,
1121                     ISA_MICROMIPS32R6;
1122 def CEIL_W_S_MMR6 : StdMMR6Rel, CEIL_W_S_MMR6_ENC, CEIL_W_S_MMR6_DESC,
1123                     ISA_MICROMIPS32R6;
1124 def CEIL_W_D_MMR6 : StdMMR6Rel, CEIL_W_D_MMR6_ENC, CEIL_W_D_MMR6_DESC,
1125                     ISA_MICROMIPS32R6;
1126 def TRUNC_L_S_MMR6 : StdMMR6Rel, TRUNC_L_S_MMR6_ENC, TRUNC_L_S_MMR6_DESC,
1127                      ISA_MICROMIPS32R6;
1128 def TRUNC_L_D_MMR6 : StdMMR6Rel, TRUNC_L_D_MMR6_ENC, TRUNC_L_D_MMR6_DESC,
1129                      ISA_MICROMIPS32R6;
1130 def TRUNC_W_S_MMR6 : StdMMR6Rel, TRUNC_W_S_MMR6_ENC, TRUNC_W_S_MMR6_DESC,
1131                      ISA_MICROMIPS32R6;
1132 def TRUNC_W_D_MMR6 : StdMMR6Rel, TRUNC_W_D_MMR6_ENC, TRUNC_W_D_MMR6_DESC,
1133                      ISA_MICROMIPS32R6;
1134 def SQRT_S_MMR6 : StdMMR6Rel, SQRT_S_MMR6_ENC, SQRT_S_MMR6_DESC,
1135                   ISA_MICROMIPS32R6;
1136 def SQRT_D_MMR6 : StdMMR6Rel, SQRT_D_MMR6_ENC, SQRT_D_MMR6_DESC,
1137                   ISA_MICROMIPS32R6;
1138 def RSQRT_S_MMR6 : StdMMR6Rel, RSQRT_S_MMR6_ENC, RSQRT_S_MMR6_DESC,
1139                    ISA_MICROMIPS32R6;
1140 def RSQRT_D_MMR6 : StdMMR6Rel, RSQRT_D_MMR6_ENC, RSQRT_D_MMR6_DESC,
1141                    ISA_MICROMIPS32R6;
1142 def SB_MMR6 : StdMMR6Rel, SB_MMR6_DESC, SB_MMR6_ENC, ISA_MICROMIPS32R6;
1143 def SBE_MMR6 : StdMMR6Rel, SBE_MMR6_DESC, SBE_MMR6_ENC, ISA_MICROMIPS32R6;
1144 def SCE_MMR6 : StdMMR6Rel, SCE_MMR6_DESC, SCE_MMR6_ENC, ISA_MICROMIPS32R6;
1145 def SH_MMR6 : StdMMR6Rel, SH_MMR6_DESC, SH_MMR6_ENC, ISA_MICROMIPS32R6;
1146 def SHE_MMR6 : StdMMR6Rel, SHE_MMR6_DESC, SHE_MMR6_ENC, ISA_MICROMIPS32R6;
1147 def LLE_MMR6 : StdMMR6Rel, LLE_MMR6_DESC, LLE_MMR6_ENC, ISA_MICROMIPS32R6;
1148 def LWE_MMR6 : StdMMR6Rel, LWE_MMR6_DESC, LWE_MMR6_ENC, ISA_MICROMIPS32R6;
1149 def LW_MMR6 : StdMMR6Rel, LW_MMR6_DESC, LW_MMR6_ENC, ISA_MICROMIPS32R6;
1150 def LUI_MMR6 : R6MMR6Rel, LUI_MMR6_DESC, LUI_MMR6_ENC, ISA_MICROMIPS32R6;
1151 def ADDU16_MMR6 : StdMMR6Rel, ADDU16_MMR6_DESC, ADDU16_MMR6_ENC,
1152                   ISA_MICROMIPS32R6;
1153 def AND16_MMR6 : StdMMR6Rel, AND16_MMR6_DESC, AND16_MMR6_ENC,
1154                   ISA_MICROMIPS32R6;
1155 def ANDI16_MMR6 : StdMMR6Rel, ANDI16_MMR6_DESC, ANDI16_MMR6_ENC,
1156                   ISA_MICROMIPS32R6;
1157 def NOT16_MMR6 : StdMMR6Rel, NOT16_MMR6_DESC, NOT16_MMR6_ENC,
1158                   ISA_MICROMIPS32R6;
1159 def OR16_MMR6 : StdMMR6Rel, OR16_MMR6_DESC, OR16_MMR6_ENC,
1160                   ISA_MICROMIPS32R6;
1161 def SLL16_MMR6 : StdMMR6Rel, SLL16_MMR6_DESC, SLL16_MMR6_ENC,
1162                   ISA_MICROMIPS32R6;
1163 def SRL16_MMR6 : StdMMR6Rel, SRL16_MMR6_DESC, SRL16_MMR6_ENC,
1164                   ISA_MICROMIPS32R6;
1165 def BREAK16_MMR6 : StdMMR6Rel, BREAK16_MMR6_DESC, BREAK16_MMR6_ENC,
1166                    ISA_MICROMIPS32R6;
1167 def LI16_MMR6 : StdMMR6Rel, LI16_MMR6_DESC, LI16_MMR6_ENC,
1168                 ISA_MICROMIPS32R6;
1169 def MOVE16_MMR6 : StdMMR6Rel, MOVE16_MMR6_DESC, MOVE16_MMR6_ENC,
1170                   ISA_MICROMIPS32R6;
1171 def SDBBP16_MMR6 : StdMMR6Rel, SDBBP16_MMR6_DESC, SDBBP16_MMR6_ENC,
1172                    ISA_MICROMIPS32R6;
1173 def SUBU16_MMR6 : StdMMR6Rel, SUBU16_MMR6_DESC, SUBU16_MMR6_ENC,
1174                   ISA_MICROMIPS32R6;
1175 def XOR16_MMR6 : StdMMR6Rel, XOR16_MMR6_DESC, XOR16_MMR6_ENC,
1176                  ISA_MICROMIPS32R6;
1177 def RECIP_S_MMR6 : StdMMR6Rel, RECIP_S_MMR6_ENC, RECIP_S_MMR6_DESC,
1178                    ISA_MICROMIPS32R6;
1179 def RECIP_D_MMR6 : StdMMR6Rel, RECIP_D_MMR6_ENC, RECIP_D_MMR6_DESC, ISA_MICROMIPS32R6;
1180 def RINT_S_MMR6 : StdMMR6Rel, RINT_S_MMR6_ENC, RINT_S_MMR6_DESC,
1181                   ISA_MICROMIPS32R6;
1182 def RINT_D_MMR6 : StdMMR6Rel, RINT_D_MMR6_ENC, RINT_D_MMR6_DESC, ISA_MICROMIPS32R6;
1183 def ROUND_L_S_MMR6 : StdMMR6Rel, ROUND_L_S_MMR6_ENC, ROUND_L_S_MMR6_DESC,
1184                      ISA_MICROMIPS32R6;
1185 def ROUND_L_D_MMR6 : StdMMR6Rel, ROUND_L_D_MMR6_ENC, ROUND_L_D_MMR6_DESC,
1186                      ISA_MICROMIPS32R6;
1187 def ROUND_W_S_MMR6 : StdMMR6Rel, ROUND_W_S_MMR6_ENC, ROUND_W_S_MMR6_DESC,
1188                      ISA_MICROMIPS32R6;
1189 def ROUND_W_D_MMR6 : StdMMR6Rel, ROUND_W_D_MMR6_ENC, ROUND_W_D_MMR6_DESC,
1190                      ISA_MICROMIPS32R6;
1191 def SEL_S_MMR6 : StdMMR6Rel, SEL_S_MMR6_ENC, SEL_S_MMR6_DESC, ISA_MICROMIPS32R6;
1192 def SEL_D_MMR6 : StdMMR6Rel, SEL_D_MMR6_ENC, SEL_D_MMR6_DESC, ISA_MICROMIPS32R6;
1193 def SELEQZ_S_MMR6 : StdMMR6Rel, SELEQZ_S_MMR6_ENC, SELEQZ_S_MMR6_DESC,
1194                     ISA_MICROMIPS32R6;
1195 def SELEQZ_D_MMR6 : StdMMR6Rel, SELEQZ_D_MMR6_ENC, SELEQZ_D_MMR6_DESC,
1196                     ISA_MICROMIPS32R6;
1197 def SELENZ_S_MMR6 : StdMMR6Rel, SELENZ_S_MMR6_ENC, SELENZ_S_MMR6_DESC,
1198                     ISA_MICROMIPS32R6;
1199 def SELENZ_D_MMR6 : StdMMR6Rel, SELENZ_D_MMR6_ENC, SELENZ_D_MMR6_DESC,
1200                     ISA_MICROMIPS32R6;
1201 def CLASS_S_MMR6 : StdMMR6Rel, CLASS_S_MMR6_ENC, CLASS_S_MMR6_DESC,
1202                    ISA_MICROMIPS32R6;
1203 def CLASS_D_MMR6 : StdMMR6Rel, CLASS_D_MMR6_ENC, CLASS_D_MMR6_DESC,
1204                    ISA_MICROMIPS32R6;
1205 }
1206
1207 //===----------------------------------------------------------------------===//
1208 //
1209 // MicroMips instruction aliases
1210 //
1211 //===----------------------------------------------------------------------===//
1212
1213 def : MipsInstAlias<"ei", (EI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
1214 def : MipsInstAlias<"di", (DI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
1215 def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6;
1216 def B_MMR6_Pseudo : MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
1217                                       !strconcat("b", "\t$offset")> {
1218   string DecoderNamespace = "MicroMipsR6";
1219 }
1220 def : MipsInstAlias<"sync", (SYNC_MMR6 0), 1>, ISA_MICROMIPS32R6;
1221 def : MipsInstAlias<"sdbbp", (SDBBP_MMR6 0), 1>, ISA_MICROMIPS32R6;
1222 def : MipsInstAlias<"rdhwr $rt, $rs",
1223                     (RDHWR_MMR6 GPR32Opnd:$rt, HWRegsOpnd:$rs, 0), 1>,
1224                     ISA_MICROMIPS32R6;
1225
1226 //===----------------------------------------------------------------------===//
1227 //
1228 // MicroMips arbitrary patterns that map to one or more instructions
1229 //
1230 //===----------------------------------------------------------------------===//
1231
1232 def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr),
1233               (SW16_MMR6 GPRMM16:$src, addrimm4lsl2:$addr)>, ISA_MICROMIPS32R6;