llvm-tblgen-rules.mk

   1 ###########################################################
   2 ## Commands for running tblgen to compile a td file
   3 ##########################################################
   4 define transform-td-to-out
   5 $(if $(LOCAL_IS_HOST_MODULE),   \
   6         $(call transform-host-td-to-out,$(1)),  \
   7         $(call transform-device-td-to-out,$(1)))
   8 endef
   9
  10 ###########################################################
  11 ## TableGen: Compile .td files to .inc.
  12 ###########################################################
  13
  14 # Set LOCAL_MODULE_CLASS to STATIC_LIBRARIES default (require
  15 # for macro local-generated-sources-dir)
  16 ifeq ($(LOCAL_MODULE_CLASS),)
  17         LOCAL_MODULE_CLASS := STATIC_LIBRARIES
  18 endif
  19
  20 ifneq ($(strip $(TBLGEN_TABLES)),)
  21
  22 generated_sources := $(call local-generated-sources-dir)
  23 tblgen_gen_tables := $(addprefix $(generated_sources)/,$(TBLGEN_TABLES))
  24 LOCAL_GENERATED_SOURCES += $(tblgen_gen_tables)
  25
  26 tblgen_source_dir := $(LOCAL_PATH)
  27 ifneq ($(TBLGEN_TD_DIR),)
  28 tblgen_source_dir := $(TBLGEN_TD_DIR)
  29 endif
  30
  31 ifneq (,$(filter $(tblgen_source_dir),MCTargetDesc))
  32 tblgen_td_deps := $(tblgen_source_dir)/../*.td
  33 else
  34 tblgen_td_deps := $(tblgen_source_dir)/*.td
  35 endif
  36 tblgen_td_deps := $(wildcard $(tblgen_td_deps))
  37
  38 #
  39 # The directory and the .td directory is not the same.
  40 #
  41 ifeq ($(tblgen_source_dir),$(LLVM_ROOT_PATH)/lib/Target/ARM/MCTargetDesc)
  42 $(generated_sources)/%GenRegisterInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
  43 $(generated_sources)/%GenRegisterInfo.inc: $(tblgen_source_dir)/../%.td \
  44                                        $(tblgen_td_deps) | $(TBLGEN)
  45         $(call transform-td-to-out, register-info)
  46
  47 $(generated_sources)/%GenInstrInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
  48 $(generated_sources)/%GenInstrInfo.inc: $(tblgen_source_dir)/../%.td \
  49                                     $(tblgen_td_deps) | $(TBLGEN)
  50         $(call transform-td-to-out,instr-info)
  51
  52 $(generated_sources)/%GenSubtargetInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
  53 $(generated_sources)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/../%.td \
  54                                         $(tblgen_td_deps) | $(TBLGEN)
  55         $(call transform-td-to-out,subtarget)
  56 endif
  57
  58 ifeq ($(tblgen_source_dir),$(LLVM_ROOT_PATH)/lib/Target/X86/MCTargetDesc)
  59 $(generated_sources)/%GenRegisterInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
  60 $(generated_sources)/%GenRegisterInfo.inc: $(tblgen_source_dir)/../%.td \
  61                                        $(tblgen_td_deps) | $(TBLGEN)
  62         $(call transform-td-to-out, register-info)
  63
  64 $(generated_sources)/%GenInstrInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
  65 $(generated_sources)/%GenInstrInfo.inc: $(tblgen_source_dir)/../%.td \
  66                                     $(tblgen_td_deps) | $(TBLGEN)
  67         $(call transform-td-to-out,instr-info)
  68
  69 $(generated_sources)/%GenSubtargetInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
  70 $(generated_sources)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/../%.td \
  71                                         $(tblgen_td_deps) | $(TBLGEN)
  72         $(call transform-td-to-out,subtarget)
  73 endif
  74
  75 ifeq ($(tblgen_source_dir),$(LLVM_ROOT_PATH)/lib/Target/Mips/MCTargetDesc)
  76 $(generated_sources)/%GenRegisterInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
  77 $(generated_sources)/%GenRegisterInfo.inc: $(tblgen_source_dir)/../%.td \
  78                                        $(tblgen_td_deps) | $(TBLGEN)
  79         $(call transform-td-to-out, register-info)
  80
  81 $(generated_sources)/%GenInstrInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
  82 $(generated_sources)/%GenInstrInfo.inc: $(tblgen_source_dir)/../%.td \
  83                                     $(tblgen_td_deps) | $(TBLGEN)
  84         $(call transform-td-to-out,instr-info)
  85
  86 $(generated_sources)/%GenSubtargetInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
  87 $(generated_sources)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/../%.td \
  88                                         $(tblgen_td_deps) | $(TBLGEN)
  89         $(call transform-td-to-out,subtarget)
  90 endif
  91
  92
  93 ifneq ($(filter %GenRegisterInfo.inc,$(tblgen_gen_tables)),)
  94 $(generated_sources)/%GenRegisterInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
  95 $(generated_sources)/%GenRegisterInfo.inc: $(tblgen_source_dir)/%.td \
  96                                        $(tblgen_td_deps) | $(TBLGEN)
  97         $(call transform-td-to-out,register-info)
  98 endif
  99
 100 ifneq ($(filter %GenInstrInfo.inc,$(tblgen_gen_tables)),)
 101 $(generated_sources)/%GenInstrInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
 102 $(generated_sources)/%GenInstrInfo.inc: $(tblgen_source_dir)/%.td \
 103                                     $(tblgen_td_deps) | $(TBLGEN)
 104         $(call transform-td-to-out,instr-info)
 105 endif
 106
 107 ifneq ($(filter %GenAsmWriter.inc,$(tblgen_gen_tables)),)
 108 $(generated_sources)/%GenAsmWriter.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
 109 $(generated_sources)/%GenAsmWriter.inc: $(tblgen_source_dir)/%.td \
 110                                     $(tblgen_td_deps) | $(TBLGEN)
 111         $(call transform-td-to-out,asm-writer)
 112 endif
 113
 114 ifneq ($(filter %GenAsmWriter1.inc,$(tblgen_gen_tables)),)
 115 $(generated_sources)/%GenAsmWriter1.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
 116 $(generated_sources)/%GenAsmWriter1.inc: $(tblgen_source_dir)/%.td \
 117                                      $(tblgen_td_deps) | $(TBLGEN)
 118         $(call transform-td-to-out,asm-writer -asmwriternum=1)
 119 endif
 120
 121 ifneq ($(filter %GenAsmMatcher.inc,$(tblgen_gen_tables)),)
 122 $(generated_sources)/%GenAsmMatcher.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
 123 $(generated_sources)/%GenAsmMatcher.inc: $(tblgen_source_dir)/%.td \
 124                                      $(tblgen_td_deps) | $(TBLGEN)
 125         $(call transform-td-to-out,asm-matcher)
 126 endif
 127
 128 ifneq ($(filter %GenCodeEmitter.inc,$(tblgen_gen_tables)),)
 129 $(generated_sources)/%GenCodeEmitter.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
 130 $(generated_sources)/%GenCodeEmitter.inc: $(tblgen_source_dir)/%.td \
 131                                       $(tblgen_td_deps) | $(TBLGEN)
 132         $(call transform-td-to-out,emitter)
 133 endif
 134
 135 ifneq ($(filter %GenMCCodeEmitter.inc,$(tblgen_gen_tables)),)
 136 $(generated_sources)/%GenMCCodeEmitter.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
 137 $(generated_sources)/%GenMCCodeEmitter.inc: $(tblgen_source_dir)/%.td \
 138                                         $(tblgen_td_deps) | $(TBLGEN)
 139         $(call transform-td-to-out,emitter -mc-emitter)
 140 endif
 141
 142 ifneq ($(filter %GenMCPseudoLowering.inc,$(tblgen_gen_tables)),)
 143 $(generated_sources)/%GenMCPseudoLowering.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
 144 $(generated_sources)/%GenMCPseudoLowering.inc: $(tblgen_source_dir)/%.td \
 145                                            $(tblgen_td_deps) | $(TBLGEN)
 146         $(call transform-td-to-out,pseudo-lowering)
 147 endif
 148
 149 ifneq ($(filter %GenDAGISel.inc,$(tblgen_gen_tables)),)
 150 $(generated_sources)/%GenDAGISel.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
 151 $(generated_sources)/%GenDAGISel.inc: $(tblgen_source_dir)/%.td \
 152                                   $(tblgen_td_deps) | $(TBLGEN)
 153         $(call transform-td-to-out,dag-isel)
 154 endif
 155
 156 ifneq ($(filter %GenDisassemblerTables.inc,$(tblgen_gen_tables)),)
 157 $(generated_sources)/%GenDisassemblerTables.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
 158 $(generated_sources)/%GenDisassemblerTables.inc: $(tblgen_source_dir)/%.td \
 159                                              $(tblgen_td_deps) | $(TBLGEN)
 160         $(call transform-td-to-out,disassembler)
 161 endif
 162
 163 ifneq ($(filter %GenEDInfo.inc,$(tblgen_gen_tables)),)
 164 $(generated_sources)/%GenEDInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
 165 $(generated_sources)/%GenEDInfo.inc: $(tblgen_source_dir)/%.td \
 166                                  $(tblgen_td_deps) | $(TBLGEN)
 167         $(call transform-td-to-out,enhanced-disassembly-info)
 168 endif
 169
 170 ifneq ($(filter %GenFastISel.inc,$(tblgen_gen_tables)),)
 171 $(generated_sources)/%GenFastISel.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
 172 $(generated_sources)/%GenFastISel.inc: $(tblgen_source_dir)/%.td \
 173                                    $(tblgen_td_deps) | $(TBLGEN)
 174         $(call transform-td-to-out,fast-isel)
 175 endif
 176
 177 ifneq ($(filter %GenSubtargetInfo.inc,$(tblgen_gen_tables)),)
 178 $(generated_sources)/%GenSubtargetInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
 179 $(generated_sources)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/%.td \
 180                                         $(tblgen_td_deps) | $(TBLGEN)
 181         $(call transform-td-to-out,subtarget)
 182 endif
 183
 184 ifneq ($(filter %GenCallingConv.inc,$(tblgen_gen_tables)),)
 185 $(generated_sources)/%GenCallingConv.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
 186 $(generated_sources)/%GenCallingConv.inc: $(tblgen_source_dir)/%.td \
 187                                       $(tblgen_td_deps) | $(TBLGEN)
 188         $(call transform-td-to-out,callingconv)
 189 endif
 190
 191 ifneq ($(filter %GenIntrinsics.inc,$(tblgen_gen_tables)),)
 192 $(generated_sources)/%GenIntrinsics.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
 193 $(generated_sources)/%GenIntrinsics.inc: $(tblgen_source_dir)/%.td \
 194                                      $(tblgen_td_deps) | $(TBLGEN)
 195         $(call transform-td-to-out,tgt_intrinsics)
 196 endif
 197
 198 ifneq ($(findstring ARMGenDecoderTables.inc,$(tblgen_gen_tables)),)
 199 $(generated_sources)/ARMGenDecoderTables.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
 200 $(generated_sources)/ARMGenDecoderTables.inc: $(tblgen_source_dir)/ARM.td \
 201                                           $(tblgen_td_deps) | $(TBLGEN)
 202         $(call transform-td-to-out,arm-decoder)
 203 endif
 204
 205 # Reset local variables
 206 tblgen_td_deps :=
 207
 208 endif