1 ###########################################################
2 ## Commands for running tblgen to compile a td file
3 ##########################################################
4 define transform-td-to-out
5 $(if $(LOCAL_IS_HOST_MODULE), \
6 $(call transform-host-td-to-out,$(1)), \
7 $(call transform-device-td-to-out,$(1)))
10 ###########################################################
11 ## TableGen: Compile .td files to .inc.
12 ###########################################################
14 # Set LOCAL_MODULE_CLASS to STATIC_LIBRARIES default (require
15 # for macro local-generated-sources-dir)
16 ifeq ($(LOCAL_MODULE_CLASS),)
17 LOCAL_MODULE_CLASS := STATIC_LIBRARIES
20 ifneq ($(strip $(TBLGEN_TABLES)),)
22 generated_sources := $(call local-generated-sources-dir)
23 tblgen_gen_tables := $(addprefix $(generated_sources)/,$(TBLGEN_TABLES))
24 LOCAL_GENERATED_SOURCES += $(tblgen_gen_tables)
26 tblgen_source_dir := $(LOCAL_PATH)
27 ifneq ($(TBLGEN_TD_DIR),)
28 tblgen_source_dir := $(TBLGEN_TD_DIR)
31 ifneq (,$(filter $(tblgen_source_dir),MCTargetDesc))
32 tblgen_td_deps := $(tblgen_source_dir)/../*.td
34 tblgen_td_deps := $(tblgen_source_dir)/*.td
36 tblgen_td_deps := $(wildcard $(tblgen_td_deps))
39 # The directory and the .td directory is not the same.
41 ifeq ($(tblgen_source_dir),$(LLVM_ROOT_PATH)/lib/Target/ARM/MCTargetDesc)
42 $(generated_sources)/%GenRegisterInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
43 $(generated_sources)/%GenRegisterInfo.inc: $(tblgen_source_dir)/../%.td \
44 $(tblgen_td_deps) $(LLVM_TBLGEN)
45 $(call transform-td-to-out, register-info)
47 $(generated_sources)/%GenInstrInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
48 $(generated_sources)/%GenInstrInfo.inc: $(tblgen_source_dir)/../%.td \
49 $(tblgen_td_deps) $(LLVM_TBLGEN)
50 $(call transform-td-to-out,instr-info)
52 $(generated_sources)/%GenSubtargetInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
53 $(generated_sources)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/../%.td \
54 $(tblgen_td_deps) $(LLVM_TBLGEN)
55 $(call transform-td-to-out,subtarget)
58 ifeq ($(tblgen_source_dir),$(LLVM_ROOT_PATH)/lib/Target/X86/MCTargetDesc)
59 $(generated_sources)/%GenRegisterInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
60 $(generated_sources)/%GenRegisterInfo.inc: $(tblgen_source_dir)/../%.td \
61 $(tblgen_td_deps) $(LLVM_TBLGEN)
62 $(call transform-td-to-out, register-info)
64 $(generated_sources)/%GenInstrInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
65 $(generated_sources)/%GenInstrInfo.inc: $(tblgen_source_dir)/../%.td \
66 $(tblgen_td_deps) $(LLVM_TBLGEN)
67 $(call transform-td-to-out,instr-info)
69 $(generated_sources)/%GenSubtargetInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
70 $(generated_sources)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/../%.td \
71 $(tblgen_td_deps) $(LLVM_TBLGEN)
72 $(call transform-td-to-out,subtarget)
75 ifeq ($(tblgen_source_dir),$(LLVM_ROOT_PATH)/lib/Target/Mips/MCTargetDesc)
76 $(generated_sources)/%GenRegisterInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
77 $(generated_sources)/%GenRegisterInfo.inc: $(tblgen_source_dir)/../%.td \
78 $(tblgen_td_deps) $(LLVM_TBLGEN)
79 $(call transform-td-to-out, register-info)
81 $(generated_sources)/%GenInstrInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
82 $(generated_sources)/%GenInstrInfo.inc: $(tblgen_source_dir)/../%.td \
83 $(tblgen_td_deps) $(LLVM_TBLGEN)
84 $(call transform-td-to-out,instr-info)
86 $(generated_sources)/%GenSubtargetInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
87 $(generated_sources)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/../%.td \
88 $(tblgen_td_deps) $(LLVM_TBLGEN)
89 $(call transform-td-to-out,subtarget)
93 ifneq ($(filter %GenRegisterInfo.inc,$(tblgen_gen_tables)),)
94 $(generated_sources)/%GenRegisterInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
95 $(generated_sources)/%GenRegisterInfo.inc: $(tblgen_source_dir)/%.td \
96 $(tblgen_td_deps) $(LLVM_TBLGEN)
97 $(call transform-td-to-out,register-info)
100 ifneq ($(filter %GenInstrInfo.inc,$(tblgen_gen_tables)),)
101 $(generated_sources)/%GenInstrInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
102 $(generated_sources)/%GenInstrInfo.inc: $(tblgen_source_dir)/%.td \
103 $(tblgen_td_deps) $(LLVM_TBLGEN)
104 $(call transform-td-to-out,instr-info)
107 ifneq ($(filter %GenAsmWriter.inc,$(tblgen_gen_tables)),)
108 $(generated_sources)/%GenAsmWriter.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
109 $(generated_sources)/%GenAsmWriter.inc: $(tblgen_source_dir)/%.td \
110 $(tblgen_td_deps) $(LLVM_TBLGEN)
111 $(call transform-td-to-out,asm-writer)
114 ifneq ($(filter %GenAsmWriter1.inc,$(tblgen_gen_tables)),)
115 $(generated_sources)/%GenAsmWriter1.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
116 $(generated_sources)/%GenAsmWriter1.inc: $(tblgen_source_dir)/%.td \
117 $(tblgen_td_deps) $(LLVM_TBLGEN)
118 $(call transform-td-to-out,asm-writer -asmwriternum=1)
121 ifneq ($(filter %GenAsmMatcher.inc,$(tblgen_gen_tables)),)
122 $(generated_sources)/%GenAsmMatcher.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
123 $(generated_sources)/%GenAsmMatcher.inc: $(tblgen_source_dir)/%.td \
124 $(tblgen_td_deps) $(LLVM_TBLGEN)
125 $(call transform-td-to-out,asm-matcher)
128 # TODO(srhines): Is this needed
129 ifneq ($(filter %GenCodeEmitter.inc,$(tblgen_gen_tables)),)
130 $(generated_sources)/%GenCodeEmitter.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
131 $(generated_sources)/%GenCodeEmitter.inc: $(tblgen_source_dir)/%.td \
132 $(tblgen_td_deps) $(LLVM_TBLGEN)
133 $(call transform-td-to-out,emitter)
136 ifneq ($(filter %GenMCCodeEmitter.inc,$(tblgen_gen_tables)),)
137 $(generated_sources)/%GenMCCodeEmitter.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
138 $(generated_sources)/%GenMCCodeEmitter.inc: $(tblgen_source_dir)/%.td \
139 $(tblgen_td_deps) $(LLVM_TBLGEN)
140 $(call transform-td-to-out,emitter)
143 ifneq ($(filter %GenMCPseudoLowering.inc,$(tblgen_gen_tables)),)
144 $(generated_sources)/%GenMCPseudoLowering.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
145 $(generated_sources)/%GenMCPseudoLowering.inc: $(tblgen_source_dir)/%.td \
146 $(tblgen_td_deps) $(LLVM_TBLGEN)
147 $(call transform-td-to-out,pseudo-lowering)
150 ifneq ($(filter %GenDAGISel.inc,$(tblgen_gen_tables)),)
151 $(generated_sources)/%GenDAGISel.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
152 $(generated_sources)/%GenDAGISel.inc: $(tblgen_source_dir)/%.td \
153 $(tblgen_td_deps) $(LLVM_TBLGEN)
154 $(call transform-td-to-out,dag-isel)
157 ifneq ($(filter %GenDisassemblerTables.inc,$(tblgen_gen_tables)),)
158 $(generated_sources)/%GenDisassemblerTables.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
159 $(generated_sources)/%GenDisassemblerTables.inc: $(tblgen_source_dir)/%.td \
160 $(tblgen_td_deps) $(LLVM_TBLGEN)
161 $(call transform-td-to-out,disassembler)
164 ifneq ($(filter %GenEDInfo.inc,$(tblgen_gen_tables)),)
165 $(generated_sources)/%GenEDInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
166 $(generated_sources)/%GenEDInfo.inc: $(tblgen_source_dir)/%.td \
167 $(tblgen_td_deps) $(LLVM_TBLGEN)
168 $(call transform-td-to-out,enhanced-disassembly-info)
171 ifneq ($(filter %GenFastISel.inc,$(tblgen_gen_tables)),)
172 $(generated_sources)/%GenFastISel.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
173 $(generated_sources)/%GenFastISel.inc: $(tblgen_source_dir)/%.td \
174 $(tblgen_td_deps) $(LLVM_TBLGEN)
175 $(call transform-td-to-out,fast-isel)
178 ifneq ($(filter %GenSubtargetInfo.inc,$(tblgen_gen_tables)),)
179 $(generated_sources)/%GenSubtargetInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
180 $(generated_sources)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/%.td \
181 $(tblgen_td_deps) $(LLVM_TBLGEN)
182 $(call transform-td-to-out,subtarget)
185 ifneq ($(filter %GenCallingConv.inc,$(tblgen_gen_tables)),)
186 $(generated_sources)/%GenCallingConv.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
187 $(generated_sources)/%GenCallingConv.inc: $(tblgen_source_dir)/%.td \
188 $(tblgen_td_deps) $(LLVM_TBLGEN)
189 $(call transform-td-to-out,callingconv)
192 ifneq ($(filter %GenIntrinsics.inc,$(tblgen_gen_tables)),)
193 $(generated_sources)/%GenIntrinsics.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
194 $(generated_sources)/%GenIntrinsics.inc: $(tblgen_source_dir)/%.td \
195 $(tblgen_td_deps) $(LLVM_TBLGEN)
196 $(call transform-td-to-out,tgt_intrinsics)
199 ifneq ($(findstring ARMGenDecoderTables.inc,$(tblgen_gen_tables)),)
200 $(generated_sources)/ARMGenDecoderTables.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
201 $(generated_sources)/ARMGenDecoderTables.inc: $(tblgen_source_dir)/ARM.td \
202 $(tblgen_td_deps) $(LLVM_TBLGEN)
203 $(call transform-td-to-out,arm-decoder)
206 ifneq ($(findstring Options.inc,$(tblgen_gen_tables)),)
207 $(generated_sources)/Options.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
208 $(generated_sources)/Options.inc: $(tblgen_source_dir)/Options.td \
211 $(LLVM_ROOT_PATH)/include/llvm/Option/OptParser.td
212 $(call transform-td-to-out,opt-parser-defs)
215 # Reset local variables