1 ###########################################################
2 ## Commands for running tblgen to compile a td file
3 ##########################################################
4 define transform-td-to-out70
5 $(if $(LOCAL_IS_HOST_MODULE), \
6 $(call transform-host-td-to-out70,$(1)), \
7 $(call transform-device-td-to-out70,$(1)))
10 ###########################################################
11 ## TableGen: Compile .td files to .inc.
12 ###########################################################
14 # Set LOCAL_MODULE_CLASS to STATIC_LIBRARIES default (require
15 # for macro local-generated-sources-dir)
16 ifeq ($(LOCAL_MODULE_CLASS),)
17 LOCAL_MODULE_CLASS := STATIC_LIBRARIES
20 ifneq ($(strip $(TBLGEN_TABLES70)),)
22 generated_sources := $(call local-generated-sources-dir)
23 tblgen_gen_tables := $(addprefix $(generated_sources)/,$(TBLGEN_TABLES70))
24 LOCAL_GENERATED_SOURCES += $(tblgen_gen_tables)
26 tblgen_source_dir := $(LOCAL_PATH)
27 ifneq ($(TBLGEN_TD_DIR70),)
28 tblgen_source_dir := $(TBLGEN_TD_DIR70)
31 ifneq (,$(filter $(tblgen_source_dir),MCTargetDesc))
32 tblgen_td_deps := $(tblgen_source_dir)/../*.td
34 tblgen_td_deps := $(tblgen_source_dir)/*.td
36 tblgen_td_deps := $(wildcard $(tblgen_td_deps))
39 # The directory and the .td directory is not the same.
41 ifeq ($(tblgen_source_dir),$(LLVM70_ROOT_PATH)/lib/Target/ARM/MCTargetDesc)
42 $(generated_sources)/%GenRegisterInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
43 $(generated_sources)/%GenRegisterInfo.inc: $(tblgen_source_dir)/../%.td \
44 $(tblgen_td_deps) $(LLVM70_TBLGEN)
45 $(call transform-td-to-out70, register-info)
47 $(generated_sources)/%GenInstrInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
48 $(generated_sources)/%GenInstrInfo.inc: $(tblgen_source_dir)/../%.td \
49 $(tblgen_td_deps) $(LLVM70_TBLGEN)
50 $(call transform-td-to-out70,instr-info)
52 $(generated_sources)/%GenSubtargetInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
53 $(generated_sources)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/../%.td \
54 $(tblgen_td_deps) $(LLVM70_TBLGEN)
55 $(call transform-td-to-out70,subtarget)
58 ifeq ($(tblgen_source_dir),$(LLVM70_ROOT_PATH)/lib/Target/X86/MCTargetDesc)
59 $(generated_sources)/%GenRegisterInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
60 $(generated_sources)/%GenRegisterInfo.inc: $(tblgen_source_dir)/../%.td \
61 $(tblgen_td_deps) $(LLVM70_TBLGEN)
62 $(call transform-td-to-out70, register-info)
64 $(generated_sources)/%GenInstrInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
65 $(generated_sources)/%GenInstrInfo.inc: $(tblgen_source_dir)/../%.td \
66 $(tblgen_td_deps) $(LLVM70_TBLGEN)
67 $(call transform-td-to-out70,instr-info)
69 $(generated_sources)/%GenSubtargetInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
70 $(generated_sources)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/../%.td \
71 $(tblgen_td_deps) $(LLVM70_TBLGEN)
72 $(call transform-td-to-out70,subtarget)
75 ifeq ($(tblgen_source_dir),$(LLVM70_ROOT_PATH)/lib/Target/Mips/MCTargetDesc)
76 $(generated_sources)/%GenRegisterInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
77 $(generated_sources)/%GenRegisterInfo.inc: $(tblgen_source_dir)/../%.td \
78 $(tblgen_td_deps) $(LLVM70_TBLGEN)
79 $(call transform-td-to-out70, register-info)
81 $(generated_sources)/%GenInstrInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
82 $(generated_sources)/%GenInstrInfo.inc: $(tblgen_source_dir)/../%.td \
83 $(tblgen_td_deps) $(LLVM70_TBLGEN)
84 $(call transform-td-to-out70,instr-info)
86 $(generated_sources)/%GenSubtargetInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
87 $(generated_sources)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/../%.td \
88 $(tblgen_td_deps) $(LLVM70_TBLGEN)
89 $(call transform-td-to-out70,subtarget)
92 ifneq ($(filter %GenRegisterInfo.inc,$(tblgen_gen_tables)),)
93 $(generated_sources)/%GenRegisterInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
94 $(generated_sources)/%GenRegisterInfo.inc: $(tblgen_source_dir)/%.td \
95 $(tblgen_td_deps) $(LLVM70_TBLGEN)
96 $(call transform-td-to-out70,register-info)
99 ifneq ($(filter %GenInstrInfo.inc,$(tblgen_gen_tables)),)
100 $(generated_sources)/%GenInstrInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
101 $(generated_sources)/%GenInstrInfo.inc: $(tblgen_source_dir)/%.td \
102 $(tblgen_td_deps) $(LLVM70_TBLGEN)
103 $(call transform-td-to-out70,instr-info)
106 ifneq ($(filter %GenAsmWriter.inc,$(tblgen_gen_tables)),)
107 $(generated_sources)/%GenAsmWriter.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
108 $(generated_sources)/%GenAsmWriter.inc: $(tblgen_source_dir)/%.td \
109 $(tblgen_td_deps) $(LLVM70_TBLGEN)
110 $(call transform-td-to-out70,asm-writer)
113 ifneq ($(filter %GenAsmWriter1.inc,$(tblgen_gen_tables)),)
114 $(generated_sources)/%GenAsmWriter1.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
115 $(generated_sources)/%GenAsmWriter1.inc: $(tblgen_source_dir)/%.td \
116 $(tblgen_td_deps) $(LLVM70_TBLGEN)
117 $(call transform-td-to-out70,asm-writer -asmwriternum=1)
120 ifneq ($(filter %GenAsmMatcher.inc,$(tblgen_gen_tables)),)
121 $(generated_sources)/%GenAsmMatcher.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
122 $(generated_sources)/%GenAsmMatcher.inc: $(tblgen_source_dir)/%.td \
123 $(tblgen_td_deps) $(LLVM70_TBLGEN)
124 $(call transform-td-to-out70,asm-matcher)
127 # TODO(srhines): Is this needed
128 ifneq ($(filter %GenCodeEmitter.inc,$(tblgen_gen_tables)),)
129 $(generated_sources)/%GenCodeEmitter.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
130 $(generated_sources)/%GenCodeEmitter.inc: $(tblgen_source_dir)/%.td \
131 $(tblgen_td_deps) $(LLVM70_TBLGEN)
132 $(call transform-td-to-out70,emitter)
135 ifneq ($(filter %GenMCCodeEmitter.inc,$(tblgen_gen_tables)),)
136 $(generated_sources)/%GenMCCodeEmitter.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
137 $(generated_sources)/%GenMCCodeEmitter.inc: $(tblgen_source_dir)/%.td \
138 $(tblgen_td_deps) $(LLVM70_TBLGEN)
139 $(call transform-td-to-out70,emitter)
142 ifneq ($(filter %GenMCPseudoLowering.inc,$(tblgen_gen_tables)),)
143 $(generated_sources)/%GenMCPseudoLowering.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
144 $(generated_sources)/%GenMCPseudoLowering.inc: $(tblgen_source_dir)/%.td \
145 $(tblgen_td_deps) $(LLVM70_TBLGEN)
146 $(call transform-td-to-out70,pseudo-lowering)
149 ifneq ($(filter %GenDAGISel.inc,$(tblgen_gen_tables)),)
150 $(generated_sources)/%GenDAGISel.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
151 $(generated_sources)/%GenDAGISel.inc: $(tblgen_source_dir)/%.td \
152 $(tblgen_td_deps) $(LLVM70_TBLGEN)
153 $(call transform-td-to-out70,dag-isel)
156 ifneq ($(filter %GenRegisterBank.inc,$(tblgen_gen_tables)),)
157 $(generated_sources)/%GenRegisterBank.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
158 $(generated_sources)/%GenRegisterBank.inc: $(tblgen_source_dir)/%.td \
159 $(tblgen_td_deps) $(LLVM70_TBLGEN)
160 $(call transform-td-to-out70,register-bank)
163 ifneq ($(filter %GenDisassemblerTables.inc,$(tblgen_gen_tables)),)
164 $(generated_sources)/%GenDisassemblerTables.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
165 $(generated_sources)/%GenDisassemblerTables.inc: $(tblgen_source_dir)/%.td \
166 $(tblgen_td_deps) $(LLVM70_TBLGEN)
167 $(call transform-td-to-out70,disassembler)
170 ifneq ($(filter %GenEDInfo.inc,$(tblgen_gen_tables)),)
171 $(generated_sources)/%GenEDInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
172 $(generated_sources)/%GenEDInfo.inc: $(tblgen_source_dir)/%.td \
173 $(tblgen_td_deps) $(LLVM70_TBLGEN)
174 $(call transform-td-to-out70,enhanced-disassembly-info)
177 ifneq ($(filter %GenFastISel.inc,$(tblgen_gen_tables)),)
178 $(generated_sources)/%GenFastISel.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
179 $(generated_sources)/%GenFastISel.inc: $(tblgen_source_dir)/%.td \
180 $(tblgen_td_deps) $(LLVM70_TBLGEN)
181 $(call transform-td-to-out70,fast-isel)
184 ifneq ($(filter %GenGlobalISel.inc,$(tblgen_gen_tables)),)
185 $(generated_sources)/%GenGlobalISel.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
186 $(generated_sources)/%GenGlobalISel.inc: $(tblgen_source_dir)/%.td \
187 $(tblgen_td_deps) $(LLVM70_TBLGEN)
188 $(call transform-td-to-out70,global-isel)
191 ifneq ($(filter %GenSubtargetInfo.inc,$(tblgen_gen_tables)),)
192 $(generated_sources)/%GenSubtargetInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
193 $(generated_sources)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/%.td \
194 $(tblgen_td_deps) $(LLVM70_TBLGEN)
195 $(call transform-td-to-out70,subtarget)
198 ifneq ($(filter %GenCallingConv.inc,$(tblgen_gen_tables)),)
199 $(generated_sources)/%GenCallingConv.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
200 $(generated_sources)/%GenCallingConv.inc: $(tblgen_source_dir)/%.td \
201 $(tblgen_td_deps) $(LLVM70_TBLGEN)
202 $(call transform-td-to-out70,callingconv)
205 ifneq ($(filter %GenIntrinsicEnums.inc,$(tblgen_gen_tables)),)
206 $(generated_sources)/%GenIntrinsicEnums.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
207 $(generated_sources)/%GenIntrinsicEnums.inc: $(tblgen_source_dir)/%.td \
208 $(tblgen_td_deps) $(LLVM70_TBLGEN)
209 $(call transform-td-to-out70,tgt-intrinsic-enums)
212 ifneq ($(filter %GenIntrinsicImpl.inc,$(tblgen_gen_tables)),)
213 $(generated_sources)/%GenIntrinsicImpl.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
214 $(generated_sources)/%GenIntrinsicImpl.inc: $(tblgen_source_dir)/%.td \
215 $(tblgen_td_deps) $(LLVM70_TBLGEN)
216 $(call transform-td-to-out70,tgt-intrinsic-impl)
219 ifneq ($(filter %GenSearchableTables.inc,$(tblgen_gen_tables)),)
220 $(generated_sources)/%GenSearchableTables.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
221 $(generated_sources)/%GenSearchableTables.inc: $(tblgen_source_dir)/%.td \
222 $(tblgen_td_deps) $(LLVM70_TBLGEN)
223 $(call transform-td-to-out70,searchable-tables)
226 ifneq ($(filter %GenSystemOperands.inc,$(tblgen_gen_tables)),)
227 $(generated_sources)/%GenSystemOperands.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
228 $(generated_sources)/%GenSystemOperands.inc: $(tblgen_source_dir)/%.td \
229 $(tblgen_td_deps) $(LLVM70_TBLGEN)
230 $(call transform-td-to-out70,searchable-tables)
233 ifneq ($(filter %GenDFAPacketizer.inc,$(tblgen_gen_tables)),)
234 $(generated_sources)/%GenDFAPacketizer.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
235 $(generated_sources)/%GenDFAPacketizer.inc: $(tblgen_source_dir)/%.td \
236 $(tblgen_td_deps) | $(LLVM70_TBLGEN)
237 $(call transform-td-to-out70,dfa-packetizer)
240 ifneq ($(findstring ARMGenDecoderTables.inc,$(tblgen_gen_tables)),)
241 $(generated_sources)/ARMGenDecoderTables.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
242 $(generated_sources)/ARMGenDecoderTables.inc: $(tblgen_source_dir)/ARM.td \
243 $(tblgen_td_deps) $(LLVM70_TBLGEN)
244 $(call transform-td-to-out70,arm-decoder)
247 ifneq ($(findstring ARMGenSystemRegister.inc,$(tblgen_gen_tables)),)
248 $(generated_sources)/ARMGenSystemRegister.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
249 $(generated_sources)/ARMGenSystemRegister.inc: $(tblgen_source_dir)/ARM.td \
250 $(tblgen_td_deps) $(LLVM70_TBLGEN)
251 $(call transform-td-to-out70,searchable-tables)
254 ifneq ($(findstring InstCombineTables.inc,$(tblgen_gen_tables)),)
255 $(generated_sources)/InstCombineTables.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
256 $(generated_sources)/InstCombineTables.inc: $(tblgen_source_dir)/InstCombineTables.td \
257 $(tblgen_td_deps) $(LLVM70_TBLGEN)
258 $(call transform-td-to-out70,searchable-tables)
261 ifneq ($(findstring Options.inc,$(tblgen_gen_tables)),)
262 $(generated_sources)/Options.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
263 $(generated_sources)/Options.inc: $(tblgen_source_dir)/Options.td \
266 $(LLVM70_ROOT_PATH)/include/llvm/Option/OptParser.td
267 $(call transform-td-to-out70,opt-parser-defs)
270 ifneq ($(findstring X86GenEVEX2VEXTables.inc,$(tblgen_gen_tables)),)
271 $(generated_sources)/X86GenEVEX2VEXTables.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
272 $(generated_sources)/X86GenEVEX2VEXTables.inc: $(tblgen_source_dir)/X86.td \
273 $(tblgen_td_deps) $(LLVM70_TBLGEN)
274 $(call transform-td-to-out70,x86-EVEX2VEX-tables)
277 # Reset local variables