Summary:
Some target lowerings of FP_TO_FP16, for instance ARM's vcvtb.f16.f32
instruction, do not guarantee that the top 16 bits are zeroed out.
Remove the unsafe AssertZext and add tests to exercise this.
Reviewers: jmolloy, sbaranga, kristof.beyls, aadg
Subscribers: llvm-commits, srhines, aemerson
Differential Revision: http://reviews.llvm.org/D18426
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264285
91177308-0d34-0410-b5e6-
96231b3b80d8
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
SDLoc dl(N);
- SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
-
- return DAG.getNode(ISD::AssertZext, dl,
- NVT, Res, DAG.getValueType(N->getValueType(0)));
+ return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
}
SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
ret void
}
+; CHECK-LABEL: test_bitcast:
+; CHECK: vcvtb.f16.f32
+; CHECK: vcvtb.f16.f32
+; CHECK: vcvtb.f16.f32
+; CHECK: pkhbt
+; CHECK: uxth
+define void @test_bitcast(<3 x half> %inp, <3 x i16>* %arr) #0 {
+ %bc = bitcast <3 x half> %inp to <3 x i16>
+ store <3 x i16> %bc, <3 x i16>* %arr, align 8
+ ret void
+}
+
attributes #0 = { nounwind }