O << ", " << getRegisterName(MO2.getReg());
assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
- if (CommentStream) printAnnotation(*CommentStream, Annot);
+ if (CommentStream) printAnnotation(O, Annot);
return;
}
<< ", " << getRegisterName(MO1.getReg());
if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
- if (CommentStream) printAnnotation(*CommentStream, Annot);
+ if (CommentStream) printAnnotation(O, Annot);
return;
}
O << ", #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
- if (CommentStream) printAnnotation(*CommentStream, Annot);
+ if (CommentStream) printAnnotation(O, Annot);
return;
}
O << ".w";
O << '\t';
printRegisterList(MI, 4, O);
- if (CommentStream) printAnnotation(*CommentStream, Annot);
+ if (CommentStream) printAnnotation(O, Annot);
return;
}
if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
O << '\t' << "push";
printPredicateOperand(MI, 4, O);
O << "\t{" << getRegisterName(MI->getOperand(1).getReg()) << "}";
- if (CommentStream) printAnnotation(*CommentStream, Annot);
+ if (CommentStream) printAnnotation(O, Annot);
return;
}
O << ".w";
O << '\t';
printRegisterList(MI, 4, O);
- if (CommentStream) printAnnotation(*CommentStream, Annot);
+ if (CommentStream) printAnnotation(O, Annot);
return;
}
if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() == ARM::SP &&
O << '\t' << "pop";
printPredicateOperand(MI, 5, O);
O << "\t{" << getRegisterName(MI->getOperand(0).getReg()) << "}";
- if (CommentStream) printAnnotation(*CommentStream, Annot);
+ if (CommentStream) printAnnotation(O, Annot);
return;
}
printPredicateOperand(MI, 2, O);
O << '\t';
printRegisterList(MI, 4, O);
- if (CommentStream) printAnnotation(*CommentStream, Annot);
+ if (CommentStream) printAnnotation(O, Annot);
return;
}
printPredicateOperand(MI, 2, O);
O << '\t';
printRegisterList(MI, 4, O);
- if (CommentStream) printAnnotation(*CommentStream, Annot);
+ if (CommentStream) printAnnotation(O, Annot);
return;
}
if (Writeback) O << "!";
O << ", ";
printRegisterList(MI, 3, O);
- if (CommentStream) printAnnotation(*CommentStream, Annot);
+ if (CommentStream) printAnnotation(O, Annot);
return;
}
MI->getOperand(1).getReg() == ARM::R8) {
O << "\tnop";
printPredicateOperand(MI, 2, O);
- if (CommentStream) printAnnotation(*CommentStream, Annot);
+ if (CommentStream) printAnnotation(O, Annot);
return;
}
printInstruction(MI, O);
- if (CommentStream) printAnnotation(*CommentStream, Annot);
+ if (CommentStream) printAnnotation(O, Annot);
}
void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
printOperand(MI, 1, O);
O << ", " << (unsigned int)SH;
- if (CommentStream) printAnnotation(*CommentStream, Annot);
+ if (CommentStream) printAnnotation(O, Annot);
return;
}
}
printOperand(MI, 0, O);
O << ", ";
printOperand(MI, 1, O);
- if (CommentStream) printAnnotation(*CommentStream, Annot);
+ if (CommentStream) printAnnotation(O, Annot);
return;
}
O << ", ";
printOperand(MI, 1, O);
O << ", " << (unsigned int)SH;
- if (CommentStream) printAnnotation(*CommentStream, Annot);
+ if (CommentStream) printAnnotation(O, Annot);
return;
}
}
printInstruction(MI, O);
- if (CommentStream) printAnnotation(*CommentStream, Annot);
+ if (CommentStream) printAnnotation(O, Annot);
}