class Div64<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
Div<op, func, instr_asm, itin, CPU64Regs, [HI64, LO64]>;
-// Count Leading Ones/Zeros in Word
-class CountLeading64<bits<6> func, string instr_asm, list<dag> pattern>:
- FR<0x1c, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$src),
- !strconcat(instr_asm, "\t$dst, $src"), pattern, IIAlu>,
- Requires<[HasBitCount]> {
- let shamt = 0;
- let rt = rd;
-}
-
//===----------------------------------------------------------------------===//
// Instruction definition
//===----------------------------------------------------------------------===//
def MFLO64 : MoveFromLOHI<0x12, "mflo", CPU64Regs, [LO64]>;
/// Count Leading
-def DCLZ : CountLeading64<0x24, "dclz",
- [(set CPU64Regs:$dst, (ctlz CPU64Regs:$src))]>;
-def DCLO : CountLeading64<0x25, "dclo",
- [(set CPU64Regs:$dst, (ctlz (not CPU64Regs:$src)))]>;
+def DCLZ : CountLeading0<0x24, "dclz", CPU64Regs>;
+def DCLO : CountLeading1<0x25, "dclo", CPU64Regs>;
//===----------------------------------------------------------------------===//
// Arbitrary patterns that map to one or more instructions
instr_asm, [(set CPURegs:$rt, addr:$addr)], IIAlu>;
// Count Leading Ones/Zeros in Word
-class CountLeading<bits<6> func, string instr_asm, list<dag> pattern>:
- FR<0x1c, func, (outs CPURegs:$rd), (ins CPURegs:$rs),
- !strconcat(instr_asm, "\t$rd, $rs"), pattern, IIAlu>,
+class CountLeading0<bits<6> func, string instr_asm, RegisterClass RC>:
+ FR<0x1c, func, (outs RC:$rd), (ins RC:$rs),
+ !strconcat(instr_asm, "\t$rd, $rs"),
+ [(set RC:$rd, (ctlz RC:$rs))], IIAlu>,
+ Requires<[HasBitCount]> {
+ let shamt = 0;
+ let rt = rd;
+}
+
+class CountLeading1<bits<6> func, string instr_asm, RegisterClass RC>:
+ FR<0x1c, func, (outs RC:$rd), (ins RC:$rs),
+ !strconcat(instr_asm, "\t$rd, $rs"),
+ [(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu>,
Requires<[HasBitCount]> {
let shamt = 0;
let rt = rd;
def SEH : SignExtInReg<0x18, "seh", i16>;
/// Count Leading
-def CLZ : CountLeading<0x20, "clz",
- [(set CPURegs:$rd, (ctlz CPURegs:$rs))]>;
-def CLO : CountLeading<0x21, "clo",
- [(set CPURegs:$rd, (ctlz (not CPURegs:$rs)))]>;
+def CLZ : CountLeading0<0x20, "clz", CPURegs>;
+def CLO : CountLeading1<0x21, "clo", CPURegs>;
/// Byte Swap
def WSBW : ByteSwap<0x20, 0x2, "wsbw">;