src/amd/vulkan/radv_meta_clear.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "radv_debug.h"
  25 #include "radv_meta.h"
  26 #include "radv_private.h"
  27 #include "nir/nir_builder.h"
  28
  29 #include "util/format_rgb9e5.h"
  30 #include "vk_format.h"
  31
  32 enum {
  33         DEPTH_CLEAR_SLOW,
  34         DEPTH_CLEAR_FAST_EXPCLEAR,
  35         DEPTH_CLEAR_FAST_NO_EXPCLEAR
  36 };
  37
  38 static void
  39 build_color_shaders(struct nir_shader **out_vs,
  40                     struct nir_shader **out_fs,
  41                     uint32_t frag_output)
  42 {
  43         nir_builder vs_b;
  44         nir_builder fs_b;
  45
  46         nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
  47         nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
  48
  49         vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_color_vs");
  50         fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_color_fs");
  51
  52         const struct glsl_type *position_type = glsl_vec4_type();
  53         const struct glsl_type *color_type = glsl_vec4_type();
  54
  55         nir_variable *vs_out_pos =
  56                 nir_variable_create(vs_b.shader, nir_var_shader_out, position_type,
  57                                     "gl_Position");
  58         vs_out_pos->data.location = VARYING_SLOT_POS;
  59
  60         nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(fs_b.shader, nir_intrinsic_load_push_constant);
  61         nir_intrinsic_set_base(in_color_load, 0);
  62         nir_intrinsic_set_range(in_color_load, 16);
  63         in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&fs_b, 0));
  64         in_color_load->num_components = 4;
  65         nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 4, 32, "clear color");
  66         nir_builder_instr_insert(&fs_b, &in_color_load->instr);
  67
  68         nir_variable *fs_out_color =
  69                 nir_variable_create(fs_b.shader, nir_var_shader_out, color_type,
  70                                     "f_color");
  71         fs_out_color->data.location = FRAG_RESULT_DATA0 + frag_output;
  72
  73         nir_store_var(&fs_b, fs_out_color, &in_color_load->dest.ssa, 0xf);
  74
  75         nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&vs_b);
  76         nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
  77
  78         const struct glsl_type *layer_type = glsl_int_type();
  79         nir_variable *vs_out_layer =
  80                 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
  81                                     "v_layer");
  82         vs_out_layer->data.location = VARYING_SLOT_LAYER;
  83         vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
  84         nir_ssa_def *inst_id = nir_load_system_value(&vs_b, nir_intrinsic_load_instance_id, 0);
  85         nir_ssa_def *base_instance = nir_load_system_value(&vs_b, nir_intrinsic_load_base_instance, 0);
  86
  87         nir_ssa_def *layer_id = nir_iadd(&vs_b, inst_id, base_instance);
  88         nir_store_var(&vs_b, vs_out_layer, layer_id, 0x1);
  89
  90         *out_vs = vs_b.shader;
  91         *out_fs = fs_b.shader;
  92 }
  93
  94 static VkResult
  95 create_pipeline(struct radv_device *device,
  96                 struct radv_render_pass *render_pass,
  97                 uint32_t samples,
  98                 struct nir_shader *vs_nir,
  99                 struct nir_shader *fs_nir,
 100                 const VkPipelineVertexInputStateCreateInfo *vi_state,
 101                 const VkPipelineDepthStencilStateCreateInfo *ds_state,
 102                 const VkPipelineColorBlendStateCreateInfo *cb_state,
 103                 const VkPipelineLayout layout,
 104                 const struct radv_graphics_pipeline_create_info *extra,
 105                 const VkAllocationCallbacks *alloc,
 106                 VkPipeline *pipeline)
 107 {
 108         VkDevice device_h = radv_device_to_handle(device);
 109         VkResult result;
 110
 111         struct radv_shader_module vs_m = { .nir = vs_nir };
 112         struct radv_shader_module fs_m = { .nir = fs_nir };
 113
 114         result = radv_graphics_pipeline_create(device_h,
 115                                                radv_pipeline_cache_to_handle(&device->meta_state.cache),
 116                                                &(VkGraphicsPipelineCreateInfo) {
 117                                                        .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
 118                                                                .stageCount = fs_nir ? 2 : 1,
 119                                                                .pStages = (VkPipelineShaderStageCreateInfo[]) {
 120                                                                {
 121                                                                        .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
 122                                                                        .stage = VK_SHADER_STAGE_VERTEX_BIT,
 123                                                                        .module = radv_shader_module_to_handle(&vs_m),
 124                                                                        .pName = "main",
 125                                                                },
 126                                                                {
 127                                                                        .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
 128                                                                        .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
 129                                                                        .module = radv_shader_module_to_handle(&fs_m),
 130                                                                        .pName = "main",
 131                                                                },
 132                                                        },
 133                                                                .pVertexInputState = vi_state,
 134                                                                         .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
 135                                                                .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
 136                                                                .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
 137                                                                .primitiveRestartEnable = false,
 138                                                        },
 139                                                                         .pViewportState = &(VkPipelineViewportStateCreateInfo) {
 140                                                                .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
 141                                                                .viewportCount = 1,
 142                                                                .scissorCount = 1,
 143                                                        },
 144                                                                                  .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
 145                                                                .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
 146                                                                .rasterizerDiscardEnable = false,
 147                                                                .polygonMode = VK_POLYGON_MODE_FILL,
 148                                                                .cullMode = VK_CULL_MODE_NONE,
 149                                                                .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE,
 150                                                                .depthBiasEnable = false,
 151                                                        },
 152                                                                                           .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
 153                                                                .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
 154                                                                .rasterizationSamples = samples,
 155                                                                .sampleShadingEnable = false,
 156                                                                .pSampleMask = NULL,
 157                                                                .alphaToCoverageEnable = false,
 158                                                                .alphaToOneEnable = false,
 159                                                        },
 160                                                                                                    .pDepthStencilState = ds_state,
 161                                                                                                             .pColorBlendState = cb_state,
 162                                                                                                             .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
 163                                                                /* The meta clear pipeline declares all state as dynamic.
 164                                                                 * As a consequence, vkCmdBindPipeline writes no dynamic state
 165                                                                 * to the cmd buffer. Therefore, at the end of the meta clear,
 166                                                                 * we need only restore dynamic state was vkCmdSet.
 167                                                                 */
 168                                                                .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
 169                                                                .dynamicStateCount = 8,
 170                                                                .pDynamicStates = (VkDynamicState[]) {
 171                                                                        /* Everything except stencil write mask */
 172                                                                        VK_DYNAMIC_STATE_VIEWPORT,
 173                                                                        VK_DYNAMIC_STATE_SCISSOR,
 174                                                                        VK_DYNAMIC_STATE_LINE_WIDTH,
 175                                                                        VK_DYNAMIC_STATE_DEPTH_BIAS,
 176                                                                        VK_DYNAMIC_STATE_BLEND_CONSTANTS,
 177                                                                        VK_DYNAMIC_STATE_DEPTH_BOUNDS,
 178                                                                        VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
 179                                                                        VK_DYNAMIC_STATE_STENCIL_REFERENCE,
 180                                                                },
 181                                                        },
 182                                                     .layout = layout,
 183                                                     .flags = 0,
 184                                                     .renderPass = radv_render_pass_to_handle(render_pass),
 185                                                     .subpass = 0,
 186                                                 },
 187                                                extra,
 188                                                alloc,
 189                                                pipeline);
 190
 191         ralloc_free(vs_nir);
 192         ralloc_free(fs_nir);
 193
 194         return result;
 195 }
 196
 197 static VkResult
 198 create_color_renderpass(struct radv_device *device,
 199                         VkFormat vk_format,
 200                         uint32_t samples,
 201                         VkRenderPass *pass)
 202 {
 203         mtx_lock(&device->meta_state.mtx);
 204         if (*pass) {
 205                 mtx_unlock (&device->meta_state.mtx);
 206                 return VK_SUCCESS;
 207         }
 208
 209         VkResult result = radv_CreateRenderPass(radv_device_to_handle(device),
 210                                        &(VkRenderPassCreateInfo) {
 211                                                .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
 212                                                        .attachmentCount = 1,
 213                                                        .pAttachments = &(VkAttachmentDescription) {
 214                                                        .format = vk_format,
 215                                                        .samples = samples,
 216                                                        .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
 217                                                        .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
 218                                                        .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
 219                                                        .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
 220                                                },
 221                                                        .subpassCount = 1,
 222                                                                 .pSubpasses = &(VkSubpassDescription) {
 223                                                        .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
 224                                                        .inputAttachmentCount = 0,
 225                                                        .colorAttachmentCount = 1,
 226                                                        .pColorAttachments = &(VkAttachmentReference) {
 227                                                                .attachment = 0,
 228                                                                .layout = VK_IMAGE_LAYOUT_GENERAL,
 229                                                        },
 230                                                        .pResolveAttachments = NULL,
 231                                                        .pDepthStencilAttachment = &(VkAttachmentReference) {
 232                                                                .attachment = VK_ATTACHMENT_UNUSED,
 233                                                                .layout = VK_IMAGE_LAYOUT_GENERAL,
 234                                                        },
 235                                                        .preserveAttachmentCount = 1,
 236                                                        .pPreserveAttachments = (uint32_t[]) { 0 },
 237                                                },
 238                                                                 .dependencyCount = 0,
 239                                                                          }, &device->meta_state.alloc, pass);
 240         mtx_unlock(&device->meta_state.mtx);
 241         return result;
 242 }
 243
 244 static VkResult
 245 create_color_pipeline(struct radv_device *device,
 246                       uint32_t samples,
 247                       uint32_t frag_output,
 248                       VkPipeline *pipeline,
 249                       VkRenderPass pass)
 250 {
 251         struct nir_shader *vs_nir;
 252         struct nir_shader *fs_nir;
 253         VkResult result;
 254
 255         mtx_lock(&device->meta_state.mtx);
 256         if (*pipeline) {
 257                 mtx_unlock(&device->meta_state.mtx);
 258                 return VK_SUCCESS;
 259         }
 260
 261         build_color_shaders(&vs_nir, &fs_nir, frag_output);
 262
 263         const VkPipelineVertexInputStateCreateInfo vi_state = {
 264                 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
 265                 .vertexBindingDescriptionCount = 0,
 266                 .vertexAttributeDescriptionCount = 0,
 267         };
 268
 269         const VkPipelineDepthStencilStateCreateInfo ds_state = {
 270                 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
 271                 .depthTestEnable = false,
 272                 .depthWriteEnable = false,
 273                 .depthBoundsTestEnable = false,
 274                 .stencilTestEnable = false,
 275         };
 276
 277         VkPipelineColorBlendAttachmentState blend_attachment_state[MAX_RTS] = { 0 };
 278         blend_attachment_state[frag_output] = (VkPipelineColorBlendAttachmentState) {
 279                 .blendEnable = false,
 280                 .colorWriteMask = VK_COLOR_COMPONENT_A_BIT |
 281                 VK_COLOR_COMPONENT_R_BIT |
 282                 VK_COLOR_COMPONENT_G_BIT |
 283                 VK_COLOR_COMPONENT_B_BIT,
 284         };
 285
 286         const VkPipelineColorBlendStateCreateInfo cb_state = {
 287                 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
 288                 .logicOpEnable = false,
 289                 .attachmentCount = MAX_RTS,
 290                 .pAttachments = blend_attachment_state
 291         };
 292
 293
 294         struct radv_graphics_pipeline_create_info extra = {
 295                 .use_rectlist = true,
 296         };
 297         result = create_pipeline(device, radv_render_pass_from_handle(pass),
 298                                  samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
 299                                  device->meta_state.clear_color_p_layout,
 300                                  &extra, &device->meta_state.alloc, pipeline);
 301
 302         mtx_unlock(&device->meta_state.mtx);
 303         return result;
 304 }
 305
 306 void
 307 radv_device_finish_meta_clear_state(struct radv_device *device)
 308 {
 309         struct radv_meta_state *state = &device->meta_state;
 310
 311         for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
 312                 for (uint32_t j = 0; j < ARRAY_SIZE(state->clear[i].color_pipelines); ++j) {
 313                         radv_DestroyPipeline(radv_device_to_handle(device),
 314                                              state->clear[i].color_pipelines[j],
 315                                              &state->alloc);
 316                         radv_DestroyRenderPass(radv_device_to_handle(device),
 317                                                state->clear[i].render_pass[j],
 318                                                &state->alloc);
 319                 }
 320
 321                 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
 322                         radv_DestroyPipeline(radv_device_to_handle(device),
 323                                              state->clear[i].depth_only_pipeline[j],
 324                                              &state->alloc);
 325                         radv_DestroyPipeline(radv_device_to_handle(device),
 326                                              state->clear[i].stencil_only_pipeline[j],
 327                                              &state->alloc);
 328                         radv_DestroyPipeline(radv_device_to_handle(device),
 329                                              state->clear[i].depthstencil_pipeline[j],
 330                                              &state->alloc);
 331                 }
 332                 radv_DestroyRenderPass(radv_device_to_handle(device),
 333                                       state->clear[i].depthstencil_rp,
 334                                       &state->alloc);
 335         }
 336         radv_DestroyPipelineLayout(radv_device_to_handle(device),
 337                                    state->clear_color_p_layout,
 338                                    &state->alloc);
 339         radv_DestroyPipelineLayout(radv_device_to_handle(device),
 340                                    state->clear_depth_p_layout,
 341                                    &state->alloc);
 342 }
 343
 344 static void
 345 emit_color_clear(struct radv_cmd_buffer *cmd_buffer,
 346                  const VkClearAttachment *clear_att,
 347                  const VkClearRect *clear_rect,
 348                  uint32_t view_mask)
 349 {
 350         struct radv_device *device = cmd_buffer->device;
 351         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
 352         const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
 353         const uint32_t subpass_att = clear_att->colorAttachment;
 354         const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
 355         const struct radv_image_view *iview = fb ? fb->attachments[pass_att].attachment : NULL;
 356         uint32_t samples, samples_log2;
 357         VkFormat format;
 358         unsigned fs_key;
 359         VkClearColorValue clear_value = clear_att->clearValue.color;
 360         VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
 361         VkPipeline pipeline;
 362
 363         /* When a framebuffer is bound to the current command buffer, get the
 364          * number of samples from it. Otherwise, get the number of samples from
 365          * the render pass because it's likely a secondary command buffer.
 366          */
 367         if (iview) {
 368                 samples = iview->image->info.samples;
 369                 format = iview->vk_format;
 370         } else {
 371                 samples = cmd_buffer->state.pass->attachments[pass_att].samples;
 372                 format = cmd_buffer->state.pass->attachments[pass_att].format;
 373         }
 374
 375         samples_log2 = ffs(samples) - 1;
 376         fs_key = radv_format_meta_fs_key(format);
 377
 378         if (fs_key == -1) {
 379                 radv_finishme("color clears incomplete");
 380                 return;
 381         }
 382
 383         if (device->meta_state.clear[samples_log2].render_pass[fs_key] == VK_NULL_HANDLE) {
 384                 VkResult ret = create_color_renderpass(device, radv_fs_key_format_exemplars[fs_key],
 385                                                        samples,
 386                                                        &device->meta_state.clear[samples_log2].render_pass[fs_key]);
 387                 if (ret != VK_SUCCESS) {
 388                         cmd_buffer->record_result = ret;
 389                         return;
 390                 }
 391         }
 392
 393         if (device->meta_state.clear[samples_log2].color_pipelines[fs_key] == VK_NULL_HANDLE) {
 394                 VkResult ret = create_color_pipeline(device, samples, 0,
 395                                                      &device->meta_state.clear[samples_log2].color_pipelines[fs_key],
 396                                                      device->meta_state.clear[samples_log2].render_pass[fs_key]);
 397                 if (ret != VK_SUCCESS) {
 398                         cmd_buffer->record_result = ret;
 399                         return;
 400                 }
 401         }
 402
 403         pipeline = device->meta_state.clear[samples_log2].color_pipelines[fs_key];
 404         if (!pipeline) {
 405                 radv_finishme("color clears incomplete");
 406                 return;
 407         }
 408         assert(samples_log2 < ARRAY_SIZE(device->meta_state.clear));
 409         assert(pipeline);
 410         assert(clear_att->aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
 411         assert(clear_att->colorAttachment < subpass->color_count);
 412
 413         radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
 414                               device->meta_state.clear_color_p_layout,
 415                               VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16,
 416                               &clear_value);
 417
 418         struct radv_subpass clear_subpass = {
 419                 .color_count = 1,
 420                 .color_attachments = (struct radv_subpass_attachment[]) {
 421                         subpass->color_attachments[clear_att->colorAttachment]
 422                 },
 423                 .depth_stencil_attachment = (struct radv_subpass_attachment) { VK_ATTACHMENT_UNUSED, VK_IMAGE_LAYOUT_UNDEFINED }
 424         };
 425
 426         radv_cmd_buffer_set_subpass(cmd_buffer, &clear_subpass, false);
 427
 428         radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
 429                              pipeline);
 430
 431         radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
 432                         .x = clear_rect->rect.offset.x,
 433                         .y = clear_rect->rect.offset.y,
 434                         .width = clear_rect->rect.extent.width,
 435                         .height = clear_rect->rect.extent.height,
 436                         .minDepth = 0.0f,
 437                         .maxDepth = 1.0f
 438                 });
 439
 440         radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
 441
 442         if (view_mask) {
 443                 unsigned i;
 444                 for_each_bit(i, view_mask)
 445                         radv_CmdDraw(cmd_buffer_h, 3, 1, 0, i);
 446         } else {
 447                 radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
 448         }
 449
 450         radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
 451 }
 452
 453
 454 static void
 455 build_depthstencil_shader(struct nir_shader **out_vs, struct nir_shader **out_fs)
 456 {
 457         nir_builder vs_b, fs_b;
 458
 459         nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL);
 460         nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
 461
 462         vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_depthstencil_vs");
 463         fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_depthstencil_fs");
 464         const struct glsl_type *position_out_type = glsl_vec4_type();
 465
 466         nir_variable *vs_out_pos =
 467                 nir_variable_create(vs_b.shader, nir_var_shader_out, position_out_type,
 468                                     "gl_Position");
 469         vs_out_pos->data.location = VARYING_SLOT_POS;
 470
 471         nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(vs_b.shader, nir_intrinsic_load_push_constant);
 472         nir_intrinsic_set_base(in_color_load, 0);
 473         nir_intrinsic_set_range(in_color_load, 4);
 474         in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&vs_b, 0));
 475         in_color_load->num_components = 1;
 476         nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 1, 32, "depth value");
 477         nir_builder_instr_insert(&vs_b, &in_color_load->instr);
 478
 479         nir_ssa_def *outvec = radv_meta_gen_rect_vertices_comp2(&vs_b, &in_color_load->dest.ssa);
 480         nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
 481
 482         const struct glsl_type *layer_type = glsl_int_type();
 483         nir_variable *vs_out_layer =
 484                 nir_variable_create(vs_b.shader, nir_var_shader_out, layer_type,
 485                                     "v_layer");
 486         vs_out_layer->data.location = VARYING_SLOT_LAYER;
 487         vs_out_layer->data.interpolation = INTERP_MODE_FLAT;
 488         nir_ssa_def *inst_id = nir_load_system_value(&vs_b, nir_intrinsic_load_instance_id, 0);
 489         nir_ssa_def *base_instance = nir_load_system_value(&vs_b, nir_intrinsic_load_base_instance, 0);
 490
 491         nir_ssa_def *layer_id = nir_iadd(&vs_b, inst_id, base_instance);
 492         nir_store_var(&vs_b, vs_out_layer, layer_id, 0x1);
 493
 494         *out_vs = vs_b.shader;
 495         *out_fs = fs_b.shader;
 496 }
 497
 498 static VkResult
 499 create_depthstencil_renderpass(struct radv_device *device,
 500                                uint32_t samples,
 501                                VkRenderPass *render_pass)
 502 {
 503         mtx_lock(&device->meta_state.mtx);
 504         if (*render_pass) {
 505                 mtx_unlock(&device->meta_state.mtx);
 506                 return VK_SUCCESS;
 507         }
 508
 509         VkResult result = radv_CreateRenderPass(radv_device_to_handle(device),
 510                                        &(VkRenderPassCreateInfo) {
 511                                                .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
 512                                                        .attachmentCount = 1,
 513                                                        .pAttachments = &(VkAttachmentDescription) {
 514                                                        .format = VK_FORMAT_D32_SFLOAT_S8_UINT,
 515                                                        .samples = samples,
 516                                                        .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
 517                                                        .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
 518                                                        .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
 519                                                        .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
 520                                                },
 521                                                        .subpassCount = 1,
 522                                                                 .pSubpasses = &(VkSubpassDescription) {
 523                                                        .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
 524                                                        .inputAttachmentCount = 0,
 525                                                        .colorAttachmentCount = 0,
 526                                                        .pColorAttachments = NULL,
 527                                                        .pResolveAttachments = NULL,
 528                                                        .pDepthStencilAttachment = &(VkAttachmentReference) {
 529                                                                .attachment = 0,
 530                                                                .layout = VK_IMAGE_LAYOUT_GENERAL,
 531                                                        },
 532                                                        .preserveAttachmentCount = 1,
 533                                                        .pPreserveAttachments = (uint32_t[]) { 0 },
 534                                                },
 535                                                                 .dependencyCount = 0,
 536                                                                          }, &device->meta_state.alloc, render_pass);
 537         mtx_unlock(&device->meta_state.mtx);
 538         return result;
 539 }
 540
 541 static VkResult
 542 create_depthstencil_pipeline(struct radv_device *device,
 543                              VkImageAspectFlags aspects,
 544                              uint32_t samples,
 545                              int index,
 546                              VkPipeline *pipeline,
 547                              VkRenderPass render_pass)
 548 {
 549         struct nir_shader *vs_nir, *fs_nir;
 550         VkResult result;
 551
 552         mtx_lock(&device->meta_state.mtx);
 553         if (*pipeline) {
 554                 mtx_unlock(&device->meta_state.mtx);
 555                 return VK_SUCCESS;
 556         }
 557
 558         build_depthstencil_shader(&vs_nir, &fs_nir);
 559
 560         const VkPipelineVertexInputStateCreateInfo vi_state = {
 561                 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
 562                 .vertexBindingDescriptionCount = 0,
 563                 .vertexAttributeDescriptionCount = 0,
 564         };
 565
 566         const VkPipelineDepthStencilStateCreateInfo ds_state = {
 567                 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
 568                 .depthTestEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
 569                 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
 570                 .depthWriteEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
 571                 .depthBoundsTestEnable = false,
 572                 .stencilTestEnable = (aspects & VK_IMAGE_ASPECT_STENCIL_BIT),
 573                 .front = {
 574                         .passOp = VK_STENCIL_OP_REPLACE,
 575                         .compareOp = VK_COMPARE_OP_ALWAYS,
 576                         .writeMask = UINT32_MAX,
 577                         .reference = 0, /* dynamic */
 578                 },
 579                 .back = { 0 /* dont care */ },
 580         };
 581
 582         const VkPipelineColorBlendStateCreateInfo cb_state = {
 583                 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
 584                 .logicOpEnable = false,
 585                 .attachmentCount = 0,
 586                 .pAttachments = NULL,
 587         };
 588
 589         struct radv_graphics_pipeline_create_info extra = {
 590                 .use_rectlist = true,
 591         };
 592
 593         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
 594                 extra.db_depth_clear = index == DEPTH_CLEAR_SLOW ? false : true;
 595                 extra.db_depth_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
 596         }
 597         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
 598                 extra.db_stencil_clear = index == DEPTH_CLEAR_SLOW ? false : true;
 599                 extra.db_stencil_disable_expclear = index == DEPTH_CLEAR_FAST_NO_EXPCLEAR ? true : false;
 600         }
 601         result = create_pipeline(device, radv_render_pass_from_handle(render_pass),
 602                                  samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
 603                                  device->meta_state.clear_depth_p_layout,
 604                                  &extra, &device->meta_state.alloc, pipeline);
 605
 606         mtx_unlock(&device->meta_state.mtx);
 607         return result;
 608 }
 609
 610 static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer,
 611                                       const struct radv_image_view *iview,
 612                                       VkImageAspectFlags aspects,
 613                                       VkImageLayout layout,
 614                                       const VkClearRect *clear_rect,
 615                                       VkClearDepthStencilValue clear_value)
 616 {
 617         if (!iview)
 618                 return false;
 619
 620         uint32_t queue_mask = radv_image_queue_family_mask(iview->image,
 621                                                            cmd_buffer->queue_family_index,
 622                                                            cmd_buffer->queue_family_index);
 623         if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
 624             clear_rect->rect.extent.width != iview->extent.width ||
 625             clear_rect->rect.extent.height != iview->extent.height)
 626                 return false;
 627         if (radv_image_is_tc_compat_htile(iview->image) &&
 628             (((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) && clear_value.depth != 0.0 &&
 629               clear_value.depth != 1.0) ||
 630              ((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) && clear_value.stencil != 0)))
 631                 return false;
 632         if (radv_image_has_htile(iview->image) &&
 633             iview->base_mip == 0 &&
 634             iview->base_layer == 0 &&
 635             radv_layout_is_htile_compressed(iview->image, layout, queue_mask) &&
 636             radv_image_extent_compare(iview->image, &iview->extent))
 637                 return true;
 638         return false;
 639 }
 640
 641 static VkPipeline
 642 pick_depthstencil_pipeline(struct radv_cmd_buffer *cmd_buffer,
 643                            struct radv_meta_state *meta_state,
 644                            const struct radv_image_view *iview,
 645                            int samples_log2,
 646                            VkImageAspectFlags aspects,
 647                            VkImageLayout layout,
 648                            const VkClearRect *clear_rect,
 649                            VkClearDepthStencilValue clear_value)
 650 {
 651         bool fast = depth_view_can_fast_clear(cmd_buffer, iview, aspects, layout, clear_rect, clear_value);
 652         int index = DEPTH_CLEAR_SLOW;
 653         VkPipeline *pipeline;
 654
 655         if (fast) {
 656                 /* we don't know the previous clear values, so we always have
 657                  * the NO_EXPCLEAR path */
 658                 index = DEPTH_CLEAR_FAST_NO_EXPCLEAR;
 659         }
 660
 661         switch (aspects) {
 662         case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
 663                 pipeline = &meta_state->clear[samples_log2].depthstencil_pipeline[index];
 664                 break;
 665         case VK_IMAGE_ASPECT_DEPTH_BIT:
 666                 pipeline = &meta_state->clear[samples_log2].depth_only_pipeline[index];
 667                 break;
 668         case VK_IMAGE_ASPECT_STENCIL_BIT:
 669                 pipeline = &meta_state->clear[samples_log2].stencil_only_pipeline[index];
 670                 break;
 671         default:
 672                 unreachable("expected depth or stencil aspect");
 673         }
 674
 675         if (cmd_buffer->device->meta_state.clear[samples_log2].depthstencil_rp == VK_NULL_HANDLE) {
 676                 VkResult ret = create_depthstencil_renderpass(cmd_buffer->device, 1u << samples_log2,
 677                                                               &cmd_buffer->device->meta_state.clear[samples_log2].depthstencil_rp);
 678                 if (ret != VK_SUCCESS) {
 679                         cmd_buffer->record_result = ret;
 680                         return VK_NULL_HANDLE;
 681                 }
 682         }
 683
 684         if (*pipeline == VK_NULL_HANDLE) {
 685                 VkResult ret = create_depthstencil_pipeline(cmd_buffer->device, aspects, 1u << samples_log2, index,
 686                                                             pipeline, cmd_buffer->device->meta_state.clear[samples_log2].depthstencil_rp);
 687                 if (ret != VK_SUCCESS) {
 688                         cmd_buffer->record_result = ret;
 689                         return VK_NULL_HANDLE;
 690                 }
 691         }
 692         return *pipeline;
 693 }
 694
 695 static void
 696 emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
 697                         const VkClearAttachment *clear_att,
 698                         const VkClearRect *clear_rect)
 699 {
 700         struct radv_device *device = cmd_buffer->device;
 701         struct radv_meta_state *meta_state = &device->meta_state;
 702         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
 703         const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
 704         const uint32_t pass_att = subpass->depth_stencil_attachment.attachment;
 705         VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
 706         VkImageAspectFlags aspects = clear_att->aspectMask;
 707         const struct radv_image_view *iview = fb ? fb->attachments[pass_att].attachment : NULL;
 708         uint32_t samples, samples_log2;
 709         VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
 710
 711         /* When a framebuffer is bound to the current command buffer, get the
 712          * number of samples from it. Otherwise, get the number of samples from
 713          * the render pass because it's likely a secondary command buffer.
 714          */
 715         if (iview) {
 716                 samples = iview->image->info.samples;
 717         } else {
 718                 samples = cmd_buffer->state.pass->attachments[pass_att].samples;
 719         }
 720
 721         samples_log2 = ffs(samples) - 1;
 722
 723         assert(pass_att != VK_ATTACHMENT_UNUSED);
 724
 725         if (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
 726                 clear_value.depth = 1.0f;
 727
 728         radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
 729                               device->meta_state.clear_depth_p_layout,
 730                               VK_SHADER_STAGE_VERTEX_BIT, 0, 4,
 731                               &clear_value.depth);
 732
 733         uint32_t prev_reference = cmd_buffer->state.dynamic.stencil_reference.front;
 734         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
 735                 radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
 736                                                   clear_value.stencil);
 737         }
 738
 739         VkPipeline pipeline = pick_depthstencil_pipeline(cmd_buffer,
 740                                                          meta_state,
 741                                                          iview,
 742                                                          samples_log2,
 743                                                          aspects,
 744                                                          subpass->depth_stencil_attachment.layout,
 745                                                          clear_rect,
 746                                                          clear_value);
 747         if (!pipeline)
 748                 return;
 749
 750         radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
 751                              pipeline);
 752
 753         if (depth_view_can_fast_clear(cmd_buffer, iview, aspects,
 754                                       subpass->depth_stencil_attachment.layout,
 755                                       clear_rect, clear_value))
 756                 radv_update_ds_clear_metadata(cmd_buffer, iview->image,
 757                                               clear_value, aspects);
 758
 759         radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
 760                         .x = clear_rect->rect.offset.x,
 761                         .y = clear_rect->rect.offset.y,
 762                         .width = clear_rect->rect.extent.width,
 763                         .height = clear_rect->rect.extent.height,
 764                         .minDepth = 0.0f,
 765                         .maxDepth = 1.0f
 766                 });
 767
 768         radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &clear_rect->rect);
 769
 770         radv_CmdDraw(cmd_buffer_h, 3, clear_rect->layerCount, 0, clear_rect->baseArrayLayer);
 771
 772         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
 773                 radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT,
 774                                                   prev_reference);
 775         }
 776 }
 777
 778 static bool
 779 emit_fast_htile_clear(struct radv_cmd_buffer *cmd_buffer,
 780                       const VkClearAttachment *clear_att,
 781                       const VkClearRect *clear_rect,
 782                       enum radv_cmd_flush_bits *pre_flush,
 783                       enum radv_cmd_flush_bits *post_flush)
 784 {
 785         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
 786         const uint32_t pass_att = subpass->depth_stencil_attachment.attachment;
 787         VkImageLayout image_layout = subpass->depth_stencil_attachment.layout;
 788         const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
 789         const struct radv_image_view *iview = fb ? fb->attachments[pass_att].attachment : NULL;
 790         VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil;
 791         VkImageAspectFlags aspects = clear_att->aspectMask;
 792         uint32_t clear_word, flush_bits;
 793
 794         if (!iview)
 795                 return false;
 796
 797         if (!radv_image_has_htile(iview->image))
 798                 return false;
 799
 800         if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
 801                 return false;
 802
 803         if (!radv_layout_is_htile_compressed(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
 804                 goto fail;
 805
 806         /* don't fast clear 3D */
 807         if (iview->image->type == VK_IMAGE_TYPE_3D)
 808                 goto fail;
 809
 810         /* all layers are bound */
 811         if (iview->base_layer > 0)
 812                 goto fail;
 813         if (iview->image->info.array_size != iview->layer_count)
 814                 goto fail;
 815
 816         if (!radv_image_extent_compare(iview->image, &iview->extent))
 817                 goto fail;
 818
 819         if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
 820             clear_rect->rect.extent.width != iview->image->info.width ||
 821             clear_rect->rect.extent.height != iview->image->info.height)
 822                 goto fail;
 823
 824         if (clear_rect->baseArrayLayer != 0)
 825                 goto fail;
 826         if (clear_rect->layerCount != iview->image->info.array_size)
 827                 goto fail;
 828
 829         if ((clear_value.depth != 0.0 && clear_value.depth != 1.0) || !(aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
 830                 goto fail;
 831
 832         /* GFX8 only supports 32-bit depth surfaces but we can enable TC-compat
 833          * HTILE for 16-bit surfaces if no Z planes are compressed. Though,
 834          * fast HTILE clears don't seem to work.
 835          */
 836         if (cmd_buffer->device->physical_device->rad_info.chip_class == VI &&
 837             iview->image->vk_format == VK_FORMAT_D16_UNORM)
 838                 goto fail;
 839
 840         if (vk_format_aspects(iview->image->vk_format) & VK_IMAGE_ASPECT_STENCIL_BIT) {
 841                 if (clear_value.stencil != 0 || !(aspects & VK_IMAGE_ASPECT_STENCIL_BIT))
 842                         goto fail;
 843                 clear_word = clear_value.depth ? 0xfffc0000 : 0;
 844         } else
 845                 clear_word = clear_value.depth ? 0xfffffff0 : 0;
 846
 847         if (pre_flush) {
 848                 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_DB |
 849                                                  RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) & ~ *pre_flush;
 850                 *pre_flush |= cmd_buffer->state.flush_bits;
 851         } else
 852                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
 853                                                 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
 854
 855         flush_bits = radv_fill_buffer(cmd_buffer, iview->image->bo,
 856                                       iview->image->offset + iview->image->htile_offset,
 857                                       iview->image->surface.htile_size, clear_word);
 858
 859         radv_update_ds_clear_metadata(cmd_buffer, iview->image, clear_value, aspects);
 860         if (post_flush) {
 861                 *post_flush |= flush_bits;
 862         } else {
 863                 cmd_buffer->state.flush_bits |= flush_bits;
 864         }
 865
 866         return true;
 867 fail:
 868         return false;
 869 }
 870
 871 VkResult
 872 radv_device_init_meta_clear_state(struct radv_device *device, bool on_demand)
 873 {
 874         VkResult res;
 875         struct radv_meta_state *state = &device->meta_state;
 876
 877         VkPipelineLayoutCreateInfo pl_color_create_info = {
 878                 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
 879                 .setLayoutCount = 0,
 880                 .pushConstantRangeCount = 1,
 881                 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_FRAGMENT_BIT, 0, 16},
 882         };
 883
 884         res = radv_CreatePipelineLayout(radv_device_to_handle(device),
 885                                         &pl_color_create_info,
 886                                         &device->meta_state.alloc,
 887                                         &device->meta_state.clear_color_p_layout);
 888         if (res != VK_SUCCESS)
 889                 goto fail;
 890
 891         VkPipelineLayoutCreateInfo pl_depth_create_info = {
 892                 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
 893                 .setLayoutCount = 0,
 894                 .pushConstantRangeCount = 1,
 895                 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_VERTEX_BIT, 0, 4},
 896         };
 897
 898         res = radv_CreatePipelineLayout(radv_device_to_handle(device),
 899                                         &pl_depth_create_info,
 900                                         &device->meta_state.alloc,
 901                                         &device->meta_state.clear_depth_p_layout);
 902         if (res != VK_SUCCESS)
 903                 goto fail;
 904
 905         if (on_demand)
 906                 return VK_SUCCESS;
 907
 908         for (uint32_t i = 0; i < ARRAY_SIZE(state->clear); ++i) {
 909                 uint32_t samples = 1 << i;
 910                 for (uint32_t j = 0; j < NUM_META_FS_KEYS; ++j) {
 911                         VkFormat format = radv_fs_key_format_exemplars[j];
 912                         unsigned fs_key = radv_format_meta_fs_key(format);
 913                         assert(!state->clear[i].color_pipelines[fs_key]);
 914
 915                         res = create_color_renderpass(device, format, samples,
 916                                                       &state->clear[i].render_pass[fs_key]);
 917                         if (res != VK_SUCCESS)
 918                                 goto fail;
 919
 920                         res = create_color_pipeline(device, samples, 0, &state->clear[i].color_pipelines[fs_key],
 921                                                     state->clear[i].render_pass[fs_key]);
 922                         if (res != VK_SUCCESS)
 923                                 goto fail;
 924
 925                 }
 926
 927                 res = create_depthstencil_renderpass(device,
 928                                                      samples,
 929                                                      &state->clear[i].depthstencil_rp);
 930                 if (res != VK_SUCCESS)
 931                         goto fail;
 932
 933                 for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) {
 934                         res = create_depthstencil_pipeline(device,
 935                                                            VK_IMAGE_ASPECT_DEPTH_BIT,
 936                                                            samples,
 937                                                            j,
 938                                                            &state->clear[i].depth_only_pipeline[j],
 939                                                            state->clear[i].depthstencil_rp);
 940                         if (res != VK_SUCCESS)
 941                                 goto fail;
 942
 943                         res = create_depthstencil_pipeline(device,
 944                                                            VK_IMAGE_ASPECT_STENCIL_BIT,
 945                                                            samples,
 946                                                            j,
 947                                                            &state->clear[i].stencil_only_pipeline[j],
 948                                                            state->clear[i].depthstencil_rp);
 949                         if (res != VK_SUCCESS)
 950                                 goto fail;
 951
 952                         res = create_depthstencil_pipeline(device,
 953                                                            VK_IMAGE_ASPECT_DEPTH_BIT |
 954                                                            VK_IMAGE_ASPECT_STENCIL_BIT,
 955                                                            samples,
 956                                                            j,
 957                                                            &state->clear[i].depthstencil_pipeline[j],
 958                                                            state->clear[i].depthstencil_rp);
 959                         if (res != VK_SUCCESS)
 960                                 goto fail;
 961                 }
 962         }
 963         return VK_SUCCESS;
 964
 965 fail:
 966         radv_device_finish_meta_clear_state(device);
 967         return res;
 968 }
 969
 970 static uint32_t
 971 radv_get_cmask_fast_clear_value(const struct radv_image *image)
 972 {
 973         uint32_t value = 0; /* Default value when no DCC. */
 974
 975         /* The fast-clear value is different for images that have both DCC and
 976          * CMASK metadata.
 977          */
 978         if (radv_image_has_dcc(image)) {
 979                 /* DCC fast clear with MSAA should clear CMASK to 0xC. */
 980                 return image->info.samples > 1 ? 0xcccccccc : 0xffffffff;
 981         }
 982
 983         return value;
 984 }
 985
 986 uint32_t
 987 radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer,
 988                  struct radv_image *image, uint32_t value)
 989 {
 990         return radv_fill_buffer(cmd_buffer, image->bo,
 991                                 image->offset + image->cmask.offset,
 992                                 image->cmask.size, value);
 993 }
 994
 995 uint32_t
 996 radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
 997                struct radv_image *image, uint32_t value)
 998 {
 999         return radv_fill_buffer(cmd_buffer, image->bo,
1000                                 image->offset + image->dcc_offset,
1001                                 image->surface.dcc_size, value);
1002 }
1003
1004 static void vi_get_fast_clear_parameters(VkFormat format,
1005                                          const VkClearColorValue *clear_value,
1006                                          uint32_t* reset_value,
1007                                          bool *can_avoid_fast_clear_elim)
1008 {
1009         bool values[4] = {};
1010         int extra_channel;
1011         bool main_value = false;
1012         bool extra_value = false;
1013         int i;
1014         *can_avoid_fast_clear_elim = false;
1015
1016         *reset_value = 0x20202020U;
1017
1018         const struct vk_format_description *desc = vk_format_description(format);
1019         if (format == VK_FORMAT_B10G11R11_UFLOAT_PACK32 ||
1020             format == VK_FORMAT_R5G6B5_UNORM_PACK16 ||
1021             format == VK_FORMAT_B5G6R5_UNORM_PACK16)
1022                 extra_channel = -1;
1023         else if (desc->layout == VK_FORMAT_LAYOUT_PLAIN) {
1024                 if (radv_translate_colorswap(format, false) <= 1)
1025                         extra_channel = desc->nr_channels - 1;
1026                 else
1027                         extra_channel = 0;
1028         } else
1029                 return;
1030
1031         for (i = 0; i < 4; i++) {
1032                 int index = desc->swizzle[i] - VK_SWIZZLE_X;
1033                 if (desc->swizzle[i] < VK_SWIZZLE_X ||
1034                     desc->swizzle[i] > VK_SWIZZLE_W)
1035                         continue;
1036
1037                 if (desc->channel[i].pure_integer &&
1038                     desc->channel[i].type == VK_FORMAT_TYPE_SIGNED) {
1039                         /* Use the maximum value for clamping the clear color. */
1040                         int max = u_bit_consecutive(0, desc->channel[i].size - 1);
1041
1042                         values[i] = clear_value->int32[i] != 0;
1043                         if (clear_value->int32[i] != 0 && MIN2(clear_value->int32[i], max) != max)
1044                                 return;
1045                 } else if (desc->channel[i].pure_integer &&
1046                            desc->channel[i].type == VK_FORMAT_TYPE_UNSIGNED) {
1047                         /* Use the maximum value for clamping the clear color. */
1048                         unsigned max = u_bit_consecutive(0, desc->channel[i].size);
1049
1050                         values[i] = clear_value->uint32[i] != 0U;
1051                         if (clear_value->uint32[i] != 0U && MIN2(clear_value->uint32[i], max) != max)
1052                                 return;
1053                 } else {
1054                         values[i] = clear_value->float32[i] != 0.0F;
1055                         if (clear_value->float32[i] != 0.0F && clear_value->float32[i] != 1.0F)
1056                                 return;
1057                 }
1058
1059                 if (index == extra_channel)
1060                         extra_value = values[i];
1061                 else
1062                         main_value = values[i];
1063         }
1064
1065         for (int i = 0; i < 4; ++i)
1066                 if (values[i] != main_value &&
1067                     desc->swizzle[i] - VK_SWIZZLE_X != extra_channel &&
1068                     desc->swizzle[i] >= VK_SWIZZLE_X &&
1069                     desc->swizzle[i] <= VK_SWIZZLE_W)
1070                         return;
1071
1072         *can_avoid_fast_clear_elim = true;
1073         if (main_value)
1074                 *reset_value |= 0x80808080U;
1075
1076         if (extra_value)
1077                 *reset_value |= 0x40404040U;
1078         return;
1079 }
1080
1081 static bool
1082 emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
1083                       const VkClearAttachment *clear_att,
1084                       const VkClearRect *clear_rect,
1085                       enum radv_cmd_flush_bits *pre_flush,
1086                       enum radv_cmd_flush_bits *post_flush,
1087                       uint32_t view_mask)
1088 {
1089         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1090         const uint32_t subpass_att = clear_att->colorAttachment;
1091         const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment;
1092         VkImageLayout image_layout = subpass->color_attachments[subpass_att].layout;
1093         const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
1094         const struct radv_image_view *iview = fb ? fb->attachments[pass_att].attachment : NULL;
1095         VkClearColorValue clear_value = clear_att->clearValue.color;
1096         uint32_t clear_color[2], flush_bits = 0;
1097         uint32_t cmask_clear_value;
1098         bool ret;
1099
1100         if (!iview)
1101                 return false;
1102
1103         if (!radv_image_has_cmask(iview->image) && !radv_image_has_dcc(iview->image))
1104                 return false;
1105
1106         if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
1107                 return false;
1108
1109         if (!radv_layout_can_fast_clear(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index)))
1110                 goto fail;
1111
1112         /* don't fast clear 3D */
1113         if (iview->image->type == VK_IMAGE_TYPE_3D)
1114                 goto fail;
1115
1116         /* all layers are bound */
1117         if (iview->base_layer > 0)
1118                 goto fail;
1119         if (iview->image->info.array_size != iview->layer_count)
1120                 goto fail;
1121
1122         if (iview->image->info.levels > 1)
1123                 goto fail;
1124
1125         if (!radv_image_extent_compare(iview->image, &iview->extent))
1126                 goto fail;
1127
1128         if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
1129             clear_rect->rect.extent.width != iview->image->info.width ||
1130             clear_rect->rect.extent.height != iview->image->info.height)
1131                 goto fail;
1132
1133         if (view_mask && (iview->image->info.array_size >= 32 ||
1134                          (1u << iview->image->info.array_size) - 1u != view_mask))
1135                 goto fail;
1136         if (!view_mask && clear_rect->baseArrayLayer != 0)
1137                 goto fail;
1138         if (!view_mask && clear_rect->layerCount != iview->image->info.array_size)
1139                 goto fail;
1140
1141         /* RB+ doesn't work with CMASK fast clear on Stoney. */
1142         if (!radv_image_has_dcc(iview->image) &&
1143             cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY)
1144                 goto fail;
1145
1146         /* DCC */
1147         ret = radv_format_pack_clear_color(iview->vk_format,
1148                                            clear_color, &clear_value);
1149         if (ret == false)
1150                 goto fail;
1151
1152         if (pre_flush) {
1153                 cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1154                                                  RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) & ~ *pre_flush;
1155                 *pre_flush |= cmd_buffer->state.flush_bits;
1156         } else
1157                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1158                                                 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1159
1160         cmask_clear_value = radv_get_cmask_fast_clear_value(iview->image);
1161
1162         /* clear cmask buffer */
1163         if (radv_image_has_dcc(iview->image)) {
1164                 uint32_t reset_value;
1165                 bool can_avoid_fast_clear_elim;
1166                 bool need_decompress_pass = false;
1167
1168                 vi_get_fast_clear_parameters(iview->vk_format,
1169                                              &clear_value, &reset_value,
1170                                              &can_avoid_fast_clear_elim);
1171
1172                 if (iview->image->info.samples > 1) {
1173                         /* DCC fast clear with MSAA should clear CMASK. */
1174                         /* FIXME: This doesn't work for now. There is a
1175                          * hardware bug with fast clears and DCC for MSAA
1176                          * textures. AMDVLK has a workaround but it doesn't
1177                          * seem to work here. Note that we might emit useless
1178                          * CB flushes but that shouldn't matter.
1179                          */
1180                         if (!can_avoid_fast_clear_elim)
1181                                 goto fail;
1182
1183                         assert(radv_image_has_cmask(iview->image));
1184
1185                         flush_bits = radv_clear_cmask(cmd_buffer, iview->image,
1186                                                       cmask_clear_value);
1187
1188                         need_decompress_pass = true;
1189                 }
1190
1191                 if (!can_avoid_fast_clear_elim)
1192                         need_decompress_pass = true;
1193
1194                 flush_bits |= radv_clear_dcc(cmd_buffer, iview->image, reset_value);
1195
1196                 radv_set_dcc_need_cmask_elim_pred(cmd_buffer, iview->image,
1197                                                   need_decompress_pass);
1198         } else {
1199                 flush_bits = radv_clear_cmask(cmd_buffer, iview->image,
1200                                               cmask_clear_value);
1201         }
1202
1203         if (post_flush) {
1204                 *post_flush |= flush_bits;
1205         } else {
1206                 cmd_buffer->state.flush_bits |= flush_bits;
1207         }
1208
1209         radv_update_color_clear_metadata(cmd_buffer, iview->image, subpass_att,
1210                                          clear_color);
1211
1212         return true;
1213 fail:
1214         return false;
1215 }
1216
1217 /**
1218  * The parameters mean that same as those in vkCmdClearAttachments.
1219  */
1220 static void
1221 emit_clear(struct radv_cmd_buffer *cmd_buffer,
1222            const VkClearAttachment *clear_att,
1223            const VkClearRect *clear_rect,
1224            enum radv_cmd_flush_bits *pre_flush,
1225            enum radv_cmd_flush_bits *post_flush,
1226            uint32_t view_mask)
1227 {
1228         if (clear_att->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
1229                 if (!emit_fast_color_clear(cmd_buffer, clear_att, clear_rect,
1230                                            pre_flush, post_flush, view_mask))
1231                         emit_color_clear(cmd_buffer, clear_att, clear_rect, view_mask);
1232         } else {
1233                 assert(clear_att->aspectMask & (VK_IMAGE_ASPECT_DEPTH_BIT |
1234                                                 VK_IMAGE_ASPECT_STENCIL_BIT));
1235                 if (!emit_fast_htile_clear(cmd_buffer, clear_att, clear_rect,
1236                                            pre_flush, post_flush))
1237                         emit_depthstencil_clear(cmd_buffer, clear_att, clear_rect);
1238         }
1239 }
1240
1241 static inline bool
1242 radv_attachment_needs_clear(struct radv_cmd_state *cmd_state, uint32_t a)
1243 {
1244         uint32_t view_mask = cmd_state->subpass->view_mask;
1245         return (a != VK_ATTACHMENT_UNUSED &&
1246                 cmd_state->attachments[a].pending_clear_aspects &&
1247                 (!view_mask || (view_mask & ~cmd_state->attachments[a].cleared_views)));
1248 }
1249
1250 static bool
1251 radv_subpass_needs_clear(struct radv_cmd_buffer *cmd_buffer)
1252 {
1253         struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1254         uint32_t a;
1255
1256         if (!cmd_state->subpass)
1257                 return false;
1258
1259         for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1260                 a = cmd_state->subpass->color_attachments[i].attachment;
1261                 if (radv_attachment_needs_clear(cmd_state, a))
1262                         return true;
1263         }
1264
1265         a = cmd_state->subpass->depth_stencil_attachment.attachment;
1266         return radv_attachment_needs_clear(cmd_state, a);
1267 }
1268
1269 static void
1270 radv_subpass_clear_attachment(struct radv_cmd_buffer *cmd_buffer,
1271                               struct radv_attachment_state *attachment,
1272                               const VkClearAttachment *clear_att,
1273                               enum radv_cmd_flush_bits *pre_flush,
1274                               enum radv_cmd_flush_bits *post_flush)
1275 {
1276         struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1277         uint32_t view_mask = cmd_state->subpass->view_mask;
1278
1279         VkClearRect clear_rect = {
1280                 .rect = cmd_state->render_area,
1281                 .baseArrayLayer = 0,
1282                 .layerCount = cmd_state->framebuffer->layers,
1283         };
1284
1285         emit_clear(cmd_buffer, clear_att, &clear_rect, pre_flush, post_flush,
1286                    view_mask & ~attachment->cleared_views);
1287         if (view_mask)
1288                 attachment->cleared_views |= view_mask;
1289         else
1290                 attachment->pending_clear_aspects = 0;
1291 }
1292
1293 /**
1294  * Emit any pending attachment clears for the current subpass.
1295  *
1296  * @see radv_attachment_state::pending_clear_aspects
1297  */
1298 void
1299 radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer)
1300 {
1301         struct radv_cmd_state *cmd_state = &cmd_buffer->state;
1302         struct radv_meta_saved_state saved_state;
1303         enum radv_cmd_flush_bits pre_flush = 0;
1304         enum radv_cmd_flush_bits post_flush = 0;
1305
1306         if (!radv_subpass_needs_clear(cmd_buffer))
1307                 return;
1308
1309         radv_meta_save(&saved_state, cmd_buffer,
1310                        RADV_META_SAVE_GRAPHICS_PIPELINE |
1311                        RADV_META_SAVE_CONSTANTS);
1312
1313         for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1314                 uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
1315
1316                 if (!radv_attachment_needs_clear(cmd_state, a))
1317                         continue;
1318
1319                 assert(cmd_state->attachments[a].pending_clear_aspects ==
1320                        VK_IMAGE_ASPECT_COLOR_BIT);
1321
1322                 VkClearAttachment clear_att = {
1323                         .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
1324                         .colorAttachment = i, /* Use attachment index relative to subpass */
1325                         .clearValue = cmd_state->attachments[a].clear_value,
1326                 };
1327
1328                 radv_subpass_clear_attachment(cmd_buffer,
1329                                               &cmd_state->attachments[a],
1330                                               &clear_att, &pre_flush,
1331                                               &post_flush);
1332         }
1333
1334         uint32_t ds = cmd_state->subpass->depth_stencil_attachment.attachment;
1335         if (radv_attachment_needs_clear(cmd_state, ds)) {
1336                 VkClearAttachment clear_att = {
1337                         .aspectMask = cmd_state->attachments[ds].pending_clear_aspects,
1338                         .clearValue = cmd_state->attachments[ds].clear_value,
1339                 };
1340
1341                 radv_subpass_clear_attachment(cmd_buffer,
1342                                               &cmd_state->attachments[ds],
1343                                               &clear_att, &pre_flush,
1344                                               &post_flush);
1345         }
1346
1347         radv_meta_restore(&saved_state, cmd_buffer);
1348         cmd_buffer->state.flush_bits |= post_flush;
1349 }
1350
1351 static void
1352 radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer,
1353                        struct radv_image *image,
1354                        VkImageLayout image_layout,
1355                        const VkImageSubresourceRange *range,
1356                        VkFormat format, int level, int layer,
1357                        const VkClearValue *clear_val)
1358 {
1359         VkDevice device_h = radv_device_to_handle(cmd_buffer->device);
1360         struct radv_image_view iview;
1361         uint32_t width = radv_minify(image->info.width, range->baseMipLevel + level);
1362         uint32_t height = radv_minify(image->info.height, range->baseMipLevel + level);
1363
1364         radv_image_view_init(&iview, cmd_buffer->device,
1365                              &(VkImageViewCreateInfo) {
1366                                      .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
1367                                              .image = radv_image_to_handle(image),
1368                                              .viewType = radv_meta_get_view_type(image),
1369                                              .format = format,
1370                                              .subresourceRange = {
1371                                              .aspectMask = range->aspectMask,
1372                                              .baseMipLevel = range->baseMipLevel + level,
1373                                              .levelCount = 1,
1374                                              .baseArrayLayer = range->baseArrayLayer + layer,
1375                                              .layerCount = 1
1376                                      },
1377                              });
1378
1379         VkFramebuffer fb;
1380         radv_CreateFramebuffer(device_h,
1381                                &(VkFramebufferCreateInfo) {
1382                                        .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
1383                                                .attachmentCount = 1,
1384                                                .pAttachments = (VkImageView[]) {
1385                                                radv_image_view_to_handle(&iview),
1386                                        },
1387                                                .width = width,
1388                                                .height = height,
1389                                                .layers = 1
1390                                },
1391                                &cmd_buffer->pool->alloc,
1392                                &fb);
1393
1394         VkAttachmentDescription att_desc = {
1395                 .format = iview.vk_format,
1396                 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1397                 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1398                 .stencilLoadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1399                 .stencilStoreOp = VK_ATTACHMENT_STORE_OP_STORE,
1400                 .initialLayout = image_layout,
1401                 .finalLayout = image_layout,
1402         };
1403
1404         VkSubpassDescription subpass_desc = {
1405                 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1406                 .inputAttachmentCount = 0,
1407                 .colorAttachmentCount = 0,
1408                 .pColorAttachments = NULL,
1409                 .pResolveAttachments = NULL,
1410                 .pDepthStencilAttachment = NULL,
1411                 .preserveAttachmentCount = 0,
1412                 .pPreserveAttachments = NULL,
1413         };
1414
1415         const VkAttachmentReference att_ref = {
1416                 .attachment = 0,
1417                 .layout = image_layout,
1418         };
1419
1420         if (range->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) {
1421                 subpass_desc.colorAttachmentCount = 1;
1422                 subpass_desc.pColorAttachments = &att_ref;
1423         } else {
1424                 subpass_desc.pDepthStencilAttachment = &att_ref;
1425         }
1426
1427         VkRenderPass pass;
1428         radv_CreateRenderPass(device_h,
1429                               &(VkRenderPassCreateInfo) {
1430                                       .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1431                                               .attachmentCount = 1,
1432                                               .pAttachments = &att_desc,
1433                                               .subpassCount = 1,
1434                                               .pSubpasses = &subpass_desc,
1435                                               },
1436                               &cmd_buffer->pool->alloc,
1437                               &pass);
1438
1439         radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
1440                                 &(VkRenderPassBeginInfo) {
1441                                         .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
1442                                                 .renderArea = {
1443                                                 .offset = { 0, 0, },
1444                                                 .extent = {
1445                                                         .width = width,
1446                                                         .height = height,
1447                                                 },
1448                                         },
1449                                                 .renderPass = pass,
1450                                                 .framebuffer = fb,
1451                                                 .clearValueCount = 0,
1452                                                 .pClearValues = NULL,
1453                                                 },
1454                                 VK_SUBPASS_CONTENTS_INLINE);
1455
1456         VkClearAttachment clear_att = {
1457                 .aspectMask = range->aspectMask,
1458                 .colorAttachment = 0,
1459                 .clearValue = *clear_val,
1460         };
1461
1462         VkClearRect clear_rect = {
1463                 .rect = {
1464                         .offset = { 0, 0 },
1465                         .extent = { width, height },
1466                 },
1467                 .baseArrayLayer = range->baseArrayLayer,
1468                 .layerCount = 1, /* FINISHME: clear multi-layer framebuffer */
1469         };
1470
1471         emit_clear(cmd_buffer, &clear_att, &clear_rect, NULL, NULL, 0);
1472
1473         radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
1474         radv_DestroyRenderPass(device_h, pass,
1475                                &cmd_buffer->pool->alloc);
1476         radv_DestroyFramebuffer(device_h, fb,
1477                                 &cmd_buffer->pool->alloc);
1478 }
1479 static void
1480 radv_cmd_clear_image(struct radv_cmd_buffer *cmd_buffer,
1481                      struct radv_image *image,
1482                      VkImageLayout image_layout,
1483                      const VkClearValue *clear_value,
1484                      uint32_t range_count,
1485                      const VkImageSubresourceRange *ranges,
1486                      bool cs)
1487 {
1488         VkFormat format = image->vk_format;
1489         VkClearValue internal_clear_value = *clear_value;
1490
1491         if (format == VK_FORMAT_E5B9G9R9_UFLOAT_PACK32) {
1492                 uint32_t value;
1493                 format = VK_FORMAT_R32_UINT;
1494                 value = float3_to_rgb9e5(clear_value->color.float32);
1495                 internal_clear_value.color.uint32[0] = value;
1496         }
1497
1498         if (format == VK_FORMAT_R4G4_UNORM_PACK8) {
1499                 uint8_t r, g;
1500                 format = VK_FORMAT_R8_UINT;
1501                 r = float_to_ubyte(clear_value->color.float32[0]) >> 4;
1502                 g = float_to_ubyte(clear_value->color.float32[1]) >> 4;
1503                 internal_clear_value.color.uint32[0] = (r << 4) | (g & 0xf);
1504         }
1505
1506         for (uint32_t r = 0; r < range_count; r++) {
1507                 const VkImageSubresourceRange *range = &ranges[r];
1508                 for (uint32_t l = 0; l < radv_get_levelCount(image, range); ++l) {
1509                         const uint32_t layer_count = image->type == VK_IMAGE_TYPE_3D ?
1510                                 radv_minify(image->info.depth, range->baseMipLevel + l) :
1511                                 radv_get_layerCount(image, range);
1512                         for (uint32_t s = 0; s < layer_count; ++s) {
1513
1514                                 if (cs ||
1515                                     (format == VK_FORMAT_R32G32B32_UINT ||
1516                                      format == VK_FORMAT_R32G32B32_SINT ||
1517                                      format == VK_FORMAT_R32G32B32_SFLOAT)) {
1518                                         struct radv_meta_blit2d_surf surf;
1519                                         surf.format = format;
1520                                         surf.image = image;
1521                                         surf.level = range->baseMipLevel + l;
1522                                         surf.layer = range->baseArrayLayer + s;
1523                                         surf.aspect_mask = range->aspectMask;
1524                                         radv_meta_clear_image_cs(cmd_buffer, &surf,
1525                                                                  &internal_clear_value.color);
1526                                 } else {
1527                                         radv_clear_image_layer(cmd_buffer, image, image_layout,
1528                                                                range, format, l, s, &internal_clear_value);
1529                                 }
1530                         }
1531                 }
1532         }
1533 }
1534
1535 void radv_CmdClearColorImage(
1536         VkCommandBuffer                             commandBuffer,
1537         VkImage                                     image_h,
1538         VkImageLayout                               imageLayout,
1539         const VkClearColorValue*                    pColor,
1540         uint32_t                                    rangeCount,
1541         const VkImageSubresourceRange*              pRanges)
1542 {
1543         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1544         RADV_FROM_HANDLE(radv_image, image, image_h);
1545         struct radv_meta_saved_state saved_state;
1546         bool cs = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1547
1548         if (cs) {
1549                 radv_meta_save(&saved_state, cmd_buffer,
1550                                RADV_META_SAVE_COMPUTE_PIPELINE |
1551                                RADV_META_SAVE_CONSTANTS |
1552                                RADV_META_SAVE_DESCRIPTORS);
1553         } else {
1554                 radv_meta_save(&saved_state, cmd_buffer,
1555                                RADV_META_SAVE_GRAPHICS_PIPELINE |
1556                                RADV_META_SAVE_CONSTANTS);
1557         }
1558
1559         radv_cmd_clear_image(cmd_buffer, image, imageLayout,
1560                              (const VkClearValue *) pColor,
1561                              rangeCount, pRanges, cs);
1562
1563         radv_meta_restore(&saved_state, cmd_buffer);
1564 }
1565
1566 void radv_CmdClearDepthStencilImage(
1567         VkCommandBuffer                             commandBuffer,
1568         VkImage                                     image_h,
1569         VkImageLayout                               imageLayout,
1570         const VkClearDepthStencilValue*             pDepthStencil,
1571         uint32_t                                    rangeCount,
1572         const VkImageSubresourceRange*              pRanges)
1573 {
1574         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1575         RADV_FROM_HANDLE(radv_image, image, image_h);
1576         struct radv_meta_saved_state saved_state;
1577
1578         radv_meta_save(&saved_state, cmd_buffer,
1579                        RADV_META_SAVE_GRAPHICS_PIPELINE |
1580                        RADV_META_SAVE_CONSTANTS);
1581
1582         radv_cmd_clear_image(cmd_buffer, image, imageLayout,
1583                              (const VkClearValue *) pDepthStencil,
1584                              rangeCount, pRanges, false);
1585
1586         radv_meta_restore(&saved_state, cmd_buffer);
1587 }
1588
1589 void radv_CmdClearAttachments(
1590         VkCommandBuffer                             commandBuffer,
1591         uint32_t                                    attachmentCount,
1592         const VkClearAttachment*                    pAttachments,
1593         uint32_t                                    rectCount,
1594         const VkClearRect*                          pRects)
1595 {
1596         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1597         struct radv_meta_saved_state saved_state;
1598         enum radv_cmd_flush_bits pre_flush = 0;
1599         enum radv_cmd_flush_bits post_flush = 0;
1600
1601         if (!cmd_buffer->state.subpass)
1602                 return;
1603
1604         radv_meta_save(&saved_state, cmd_buffer,
1605                        RADV_META_SAVE_GRAPHICS_PIPELINE |
1606                        RADV_META_SAVE_CONSTANTS);
1607
1608         /* FINISHME: We can do better than this dumb loop. It thrashes too much
1609          * state.
1610          */
1611         for (uint32_t a = 0; a < attachmentCount; ++a) {
1612                 for (uint32_t r = 0; r < rectCount; ++r) {
1613                         emit_clear(cmd_buffer, &pAttachments[a], &pRects[r], &pre_flush, &post_flush,
1614                                    cmd_buffer->state.subpass->view_mask);
1615                 }
1616         }
1617
1618         radv_meta_restore(&saved_state, cmd_buffer);
1619         cmd_buffer->state.flush_bits |= post_flush;
1620 }