src/gallium/drivers/freedreno/a4xx/a4xx.xml.h

   1 #ifndef A4XX_XML
   2 #define A4XX_XML
   3
   4 /* Autogenerated file, DO NOT EDIT manually!
   5
   6 This file was generated by the rules-ng-ng headergen tool in this git repository:
   7 http://github.com/freedreno/envytools/
   8 git clone https://github.com/freedreno/envytools.git
   9
  10 The rules-ng-ng source files this header was generated from are:
  11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    398 bytes, from 2015-09-24 17:25:31)
  12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2016-02-10 17:07:21)
  13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2015-05-20 20:03:14)
  14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  11518 bytes, from 2016-02-10 21:03:25)
  15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  16185 bytes, from 2016-03-05 03:08:05)
  16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  83967 bytes, from 2016-02-10 17:07:21)
  17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          ( 110685 bytes, from 2016-04-25 17:56:43)
  18 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2015-09-24 17:30:00)
  19
  20 Copyright (C) 2013-2016 by the following authors:
  21 - Rob Clark <robdclark@gmail.com> (robclark)
  22 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
  23
  24 Permission is hereby granted, free of charge, to any person obtaining
  25 a copy of this software and associated documentation files (the
  26 "Software"), to deal in the Software without restriction, including
  27 without limitation the rights to use, copy, modify, merge, publish,
  28 distribute, sublicense, and/or sell copies of the Software, and to
  29 permit persons to whom the Software is furnished to do so, subject to
  30 the following conditions:
  31
  32 The above copyright notice and this permission notice (including the
  33 next paragraph) shall be included in all copies or substantial
  34 portions of the Software.
  35
  36 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  37 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  38 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  39 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  40 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  41 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  42 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  43 */
  44
  45
  46 enum a4xx_color_fmt {
  47         RB4_A8_UNORM = 1,
  48         RB4_R8_UNORM = 2,
  49         RB4_R8_SNORM = 3,
  50         RB4_R8_UINT = 4,
  51         RB4_R8_SINT = 5,
  52         RB4_R4G4B4A4_UNORM = 8,
  53         RB4_R5G5B5A1_UNORM = 10,
  54         RB4_R5G6B5_UNORM = 14,
  55         RB4_R8G8_UNORM = 15,
  56         RB4_R8G8_SNORM = 16,
  57         RB4_R8G8_UINT = 17,
  58         RB4_R8G8_SINT = 18,
  59         RB4_R16_UNORM = 19,
  60         RB4_R16_SNORM = 20,
  61         RB4_R16_FLOAT = 21,
  62         RB4_R16_UINT = 22,
  63         RB4_R16_SINT = 23,
  64         RB4_R8G8B8_UNORM = 25,
  65         RB4_R8G8B8A8_UNORM = 26,
  66         RB4_R8G8B8A8_SNORM = 28,
  67         RB4_R8G8B8A8_UINT = 29,
  68         RB4_R8G8B8A8_SINT = 30,
  69         RB4_R10G10B10A2_UNORM = 31,
  70         RB4_R10G10B10A2_UINT = 34,
  71         RB4_R11G11B10_FLOAT = 39,
  72         RB4_R16G16_UNORM = 40,
  73         RB4_R16G16_SNORM = 41,
  74         RB4_R16G16_FLOAT = 42,
  75         RB4_R16G16_UINT = 43,
  76         RB4_R16G16_SINT = 44,
  77         RB4_R32_FLOAT = 45,
  78         RB4_R32_UINT = 46,
  79         RB4_R32_SINT = 47,
  80         RB4_R16G16B16A16_UNORM = 52,
  81         RB4_R16G16B16A16_SNORM = 53,
  82         RB4_R16G16B16A16_FLOAT = 54,
  83         RB4_R16G16B16A16_UINT = 55,
  84         RB4_R16G16B16A16_SINT = 56,
  85         RB4_R32G32_FLOAT = 57,
  86         RB4_R32G32_UINT = 58,
  87         RB4_R32G32_SINT = 59,
  88         RB4_R32G32B32A32_FLOAT = 60,
  89         RB4_R32G32B32A32_UINT = 61,
  90         RB4_R32G32B32A32_SINT = 62,
  91 };
  92
  93 enum a4xx_tile_mode {
  94         TILE4_LINEAR = 0,
  95         TILE4_3 = 3,
  96 };
  97
  98 enum a4xx_rb_blend_opcode {
  99         BLEND_DST_PLUS_SRC = 0,
 100         BLEND_SRC_MINUS_DST = 1,
 101         BLEND_DST_MINUS_SRC = 2,
 102         BLEND_MIN_DST_SRC = 3,
 103         BLEND_MAX_DST_SRC = 4,
 104 };
 105
 106 enum a4xx_vtx_fmt {
 107         VFMT4_32_FLOAT = 1,
 108         VFMT4_32_32_FLOAT = 2,
 109         VFMT4_32_32_32_FLOAT = 3,
 110         VFMT4_32_32_32_32_FLOAT = 4,
 111         VFMT4_16_FLOAT = 5,
 112         VFMT4_16_16_FLOAT = 6,
 113         VFMT4_16_16_16_FLOAT = 7,
 114         VFMT4_16_16_16_16_FLOAT = 8,
 115         VFMT4_32_FIXED = 9,
 116         VFMT4_32_32_FIXED = 10,
 117         VFMT4_32_32_32_FIXED = 11,
 118         VFMT4_32_32_32_32_FIXED = 12,
 119         VFMT4_11_11_10_FLOAT = 13,
 120         VFMT4_16_SINT = 16,
 121         VFMT4_16_16_SINT = 17,
 122         VFMT4_16_16_16_SINT = 18,
 123         VFMT4_16_16_16_16_SINT = 19,
 124         VFMT4_16_UINT = 20,
 125         VFMT4_16_16_UINT = 21,
 126         VFMT4_16_16_16_UINT = 22,
 127         VFMT4_16_16_16_16_UINT = 23,
 128         VFMT4_16_SNORM = 24,
 129         VFMT4_16_16_SNORM = 25,
 130         VFMT4_16_16_16_SNORM = 26,
 131         VFMT4_16_16_16_16_SNORM = 27,
 132         VFMT4_16_UNORM = 28,
 133         VFMT4_16_16_UNORM = 29,
 134         VFMT4_16_16_16_UNORM = 30,
 135         VFMT4_16_16_16_16_UNORM = 31,
 136         VFMT4_32_UINT = 32,
 137         VFMT4_32_32_UINT = 33,
 138         VFMT4_32_32_32_UINT = 34,
 139         VFMT4_32_32_32_32_UINT = 35,
 140         VFMT4_32_SINT = 36,
 141         VFMT4_32_32_SINT = 37,
 142         VFMT4_32_32_32_SINT = 38,
 143         VFMT4_32_32_32_32_SINT = 39,
 144         VFMT4_8_UINT = 40,
 145         VFMT4_8_8_UINT = 41,
 146         VFMT4_8_8_8_UINT = 42,
 147         VFMT4_8_8_8_8_UINT = 43,
 148         VFMT4_8_UNORM = 44,
 149         VFMT4_8_8_UNORM = 45,
 150         VFMT4_8_8_8_UNORM = 46,
 151         VFMT4_8_8_8_8_UNORM = 47,
 152         VFMT4_8_SINT = 48,
 153         VFMT4_8_8_SINT = 49,
 154         VFMT4_8_8_8_SINT = 50,
 155         VFMT4_8_8_8_8_SINT = 51,
 156         VFMT4_8_SNORM = 52,
 157         VFMT4_8_8_SNORM = 53,
 158         VFMT4_8_8_8_SNORM = 54,
 159         VFMT4_8_8_8_8_SNORM = 55,
 160         VFMT4_10_10_10_2_UINT = 56,
 161         VFMT4_10_10_10_2_UNORM = 57,
 162         VFMT4_10_10_10_2_SINT = 58,
 163         VFMT4_10_10_10_2_SNORM = 59,
 164         VFMT4_2_10_10_10_UINT = 60,
 165         VFMT4_2_10_10_10_UNORM = 61,
 166         VFMT4_2_10_10_10_SINT = 62,
 167         VFMT4_2_10_10_10_SNORM = 63,
 168 };
 169
 170 enum a4xx_tex_fmt {
 171         TFMT4_A8_UNORM = 3,
 172         TFMT4_8_UNORM = 4,
 173         TFMT4_8_SNORM = 5,
 174         TFMT4_8_UINT = 6,
 175         TFMT4_8_SINT = 7,
 176         TFMT4_4_4_4_4_UNORM = 8,
 177         TFMT4_5_5_5_1_UNORM = 9,
 178         TFMT4_5_6_5_UNORM = 11,
 179         TFMT4_L8_A8_UNORM = 13,
 180         TFMT4_8_8_UNORM = 14,
 181         TFMT4_8_8_SNORM = 15,
 182         TFMT4_8_8_UINT = 16,
 183         TFMT4_8_8_SINT = 17,
 184         TFMT4_16_UNORM = 18,
 185         TFMT4_16_SNORM = 19,
 186         TFMT4_16_FLOAT = 20,
 187         TFMT4_16_UINT = 21,
 188         TFMT4_16_SINT = 22,
 189         TFMT4_8_8_8_8_UNORM = 28,
 190         TFMT4_8_8_8_8_SNORM = 29,
 191         TFMT4_8_8_8_8_UINT = 30,
 192         TFMT4_8_8_8_8_SINT = 31,
 193         TFMT4_9_9_9_E5_FLOAT = 32,
 194         TFMT4_10_10_10_2_UNORM = 33,
 195         TFMT4_10_10_10_2_UINT = 34,
 196         TFMT4_11_11_10_FLOAT = 37,
 197         TFMT4_16_16_UNORM = 38,
 198         TFMT4_16_16_SNORM = 39,
 199         TFMT4_16_16_FLOAT = 40,
 200         TFMT4_16_16_UINT = 41,
 201         TFMT4_16_16_SINT = 42,
 202         TFMT4_32_FLOAT = 43,
 203         TFMT4_32_UINT = 44,
 204         TFMT4_32_SINT = 45,
 205         TFMT4_16_16_16_16_UNORM = 51,
 206         TFMT4_16_16_16_16_SNORM = 52,
 207         TFMT4_16_16_16_16_FLOAT = 53,
 208         TFMT4_16_16_16_16_UINT = 54,
 209         TFMT4_16_16_16_16_SINT = 55,
 210         TFMT4_32_32_FLOAT = 56,
 211         TFMT4_32_32_UINT = 57,
 212         TFMT4_32_32_SINT = 58,
 213         TFMT4_32_32_32_FLOAT = 59,
 214         TFMT4_32_32_32_UINT = 60,
 215         TFMT4_32_32_32_SINT = 61,
 216         TFMT4_32_32_32_32_FLOAT = 63,
 217         TFMT4_32_32_32_32_UINT = 64,
 218         TFMT4_32_32_32_32_SINT = 65,
 219         TFMT4_X8Z24_UNORM = 71,
 220         TFMT4_DXT1 = 86,
 221         TFMT4_DXT3 = 87,
 222         TFMT4_DXT5 = 88,
 223         TFMT4_RGTC1_UNORM = 90,
 224         TFMT4_RGTC1_SNORM = 91,
 225         TFMT4_RGTC2_UNORM = 94,
 226         TFMT4_RGTC2_SNORM = 95,
 227         TFMT4_BPTC_UFLOAT = 97,
 228         TFMT4_BPTC_FLOAT = 98,
 229         TFMT4_BPTC = 99,
 230         TFMT4_ATC_RGB = 100,
 231         TFMT4_ATC_RGBA_EXPLICIT = 101,
 232         TFMT4_ATC_RGBA_INTERPOLATED = 102,
 233         TFMT4_ETC2_RG11_UNORM = 103,
 234         TFMT4_ETC2_RG11_SNORM = 104,
 235         TFMT4_ETC2_R11_UNORM = 105,
 236         TFMT4_ETC2_R11_SNORM = 106,
 237         TFMT4_ETC1 = 107,
 238         TFMT4_ETC2_RGB8 = 108,
 239         TFMT4_ETC2_RGBA8 = 109,
 240         TFMT4_ETC2_RGB8A1 = 110,
 241         TFMT4_ASTC_4x4 = 111,
 242         TFMT4_ASTC_5x4 = 112,
 243         TFMT4_ASTC_5x5 = 113,
 244         TFMT4_ASTC_6x5 = 114,
 245         TFMT4_ASTC_6x6 = 115,
 246         TFMT4_ASTC_8x5 = 116,
 247         TFMT4_ASTC_8x6 = 117,
 248         TFMT4_ASTC_8x8 = 118,
 249         TFMT4_ASTC_10x5 = 119,
 250         TFMT4_ASTC_10x6 = 120,
 251         TFMT4_ASTC_10x8 = 121,
 252         TFMT4_ASTC_10x10 = 122,
 253         TFMT4_ASTC_12x10 = 123,
 254         TFMT4_ASTC_12x12 = 124,
 255 };
 256
 257 enum a4xx_tex_fetchsize {
 258         TFETCH4_1_BYTE = 0,
 259         TFETCH4_2_BYTE = 1,
 260         TFETCH4_4_BYTE = 2,
 261         TFETCH4_8_BYTE = 3,
 262         TFETCH4_16_BYTE = 4,
 263 };
 264
 265 enum a4xx_depth_format {
 266         DEPTH4_NONE = 0,
 267         DEPTH4_16 = 1,
 268         DEPTH4_24_8 = 2,
 269         DEPTH4_32 = 3,
 270 };
 271
 272 enum a4xx_tess_spacing {
 273         EQUAL_SPACING = 0,
 274         ODD_SPACING = 2,
 275         EVEN_SPACING = 3,
 276 };
 277
 278 enum a4xx_ccu_perfcounter_select {
 279         CCU_BUSY_CYCLES = 0,
 280         CCU_RB_DEPTH_RETURN_STALL = 2,
 281         CCU_RB_COLOR_RETURN_STALL = 3,
 282         CCU_DEPTH_BLOCKS = 6,
 283         CCU_COLOR_BLOCKS = 7,
 284         CCU_DEPTH_BLOCK_HIT = 8,
 285         CCU_COLOR_BLOCK_HIT = 9,
 286         CCU_DEPTH_FLAG1_COUNT = 10,
 287         CCU_DEPTH_FLAG2_COUNT = 11,
 288         CCU_DEPTH_FLAG3_COUNT = 12,
 289         CCU_DEPTH_FLAG4_COUNT = 13,
 290         CCU_COLOR_FLAG1_COUNT = 14,
 291         CCU_COLOR_FLAG2_COUNT = 15,
 292         CCU_COLOR_FLAG3_COUNT = 16,
 293         CCU_COLOR_FLAG4_COUNT = 17,
 294         CCU_PARTIAL_BLOCK_READ = 18,
 295 };
 296
 297 enum a4xx_cp_perfcounter_select {
 298         CP_ALWAYS_COUNT = 0,
 299         CP_BUSY = 1,
 300         CP_PFP_IDLE = 2,
 301         CP_PFP_BUSY_WORKING = 3,
 302         CP_PFP_STALL_CYCLES_ANY = 4,
 303         CP_PFP_STARVE_CYCLES_ANY = 5,
 304         CP_PFP_STARVED_PER_LOAD_ADDR = 6,
 305         CP_PFP_STALLED_PER_STORE_ADDR = 7,
 306         CP_PFP_PC_PROFILE = 8,
 307         CP_PFP_MATCH_PM4_PKT_PROFILE = 9,
 308         CP_PFP_COND_INDIRECT_DISCARDED = 10,
 309         CP_LONG_RESUMPTIONS = 11,
 310         CP_RESUME_CYCLES = 12,
 311         CP_RESUME_TO_BOUNDARY_CYCLES = 13,
 312         CP_LONG_PREEMPTIONS = 14,
 313         CP_PREEMPT_CYCLES = 15,
 314         CP_PREEMPT_TO_BOUNDARY_CYCLES = 16,
 315         CP_ME_FIFO_EMPTY_PFP_IDLE = 17,
 316         CP_ME_FIFO_EMPTY_PFP_BUSY = 18,
 317         CP_ME_FIFO_NOT_EMPTY_NOT_FULL = 19,
 318         CP_ME_FIFO_FULL_ME_BUSY = 20,
 319         CP_ME_FIFO_FULL_ME_NON_WORKING = 21,
 320         CP_ME_WAITING_FOR_PACKETS = 22,
 321         CP_ME_BUSY_WORKING = 23,
 322         CP_ME_STARVE_CYCLES_ANY = 24,
 323         CP_ME_STARVE_CYCLES_PER_PROFILE = 25,
 324         CP_ME_STALL_CYCLES_PER_PROFILE = 26,
 325         CP_ME_PC_PROFILE = 27,
 326         CP_RCIU_FIFO_EMPTY = 28,
 327         CP_RCIU_FIFO_NOT_EMPTY_NOT_FULL = 29,
 328         CP_RCIU_FIFO_FULL = 30,
 329         CP_RCIU_FIFO_FULL_NO_CONTEXT = 31,
 330         CP_RCIU_FIFO_FULL_AHB_MASTER = 32,
 331         CP_RCIU_FIFO_FULL_OTHER = 33,
 332         CP_AHB_IDLE = 34,
 333         CP_AHB_STALL_ON_GRANT_NO_SPLIT = 35,
 334         CP_AHB_STALL_ON_GRANT_SPLIT = 36,
 335         CP_AHB_STALL_ON_GRANT_SPLIT_PROFILE = 37,
 336         CP_AHB_BUSY_WORKING = 38,
 337         CP_AHB_BUSY_STALL_ON_HRDY = 39,
 338         CP_AHB_BUSY_STALL_ON_HRDY_PROFILE = 40,
 339 };
 340
 341 enum a4xx_gras_ras_perfcounter_select {
 342         RAS_SUPER_TILES = 0,
 343         RAS_8X8_TILES = 1,
 344         RAS_4X4_TILES = 2,
 345         RAS_BUSY_CYCLES = 3,
 346         RAS_STALL_CYCLES_BY_RB = 4,
 347         RAS_STALL_CYCLES_BY_VSC = 5,
 348         RAS_STARVE_CYCLES_BY_TSE = 6,
 349         RAS_SUPERTILE_CYCLES = 7,
 350         RAS_TILE_CYCLES = 8,
 351         RAS_FULLY_COVERED_SUPER_TILES = 9,
 352         RAS_FULLY_COVERED_8X8_TILES = 10,
 353         RAS_4X4_PRIM = 11,
 354         RAS_8X4_4X8_PRIM = 12,
 355         RAS_8X8_PRIM = 13,
 356 };
 357
 358 enum a4xx_gras_tse_perfcounter_select {
 359         TSE_INPUT_PRIM = 0,
 360         TSE_INPUT_NULL_PRIM = 1,
 361         TSE_TRIVAL_REJ_PRIM = 2,
 362         TSE_CLIPPED_PRIM = 3,
 363         TSE_NEW_PRIM = 4,
 364         TSE_ZERO_AREA_PRIM = 5,
 365         TSE_FACENESS_CULLED_PRIM = 6,
 366         TSE_ZERO_PIXEL_PRIM = 7,
 367         TSE_OUTPUT_NULL_PRIM = 8,
 368         TSE_OUTPUT_VISIBLE_PRIM = 9,
 369         TSE_PRE_CLIP_PRIM = 10,
 370         TSE_POST_CLIP_PRIM = 11,
 371         TSE_BUSY_CYCLES = 12,
 372         TSE_PC_STARVE = 13,
 373         TSE_RAS_STALL = 14,
 374         TSE_STALL_BARYPLANE_FIFO_FULL = 15,
 375         TSE_STALL_ZPLANE_FIFO_FULL = 16,
 376 };
 377
 378 enum a4xx_hlsq_perfcounter_select {
 379         HLSQ_SP_VS_STAGE_CONSTANT = 0,
 380         HLSQ_SP_VS_STAGE_INSTRUCTIONS = 1,
 381         HLSQ_SP_FS_STAGE_CONSTANT = 2,
 382         HLSQ_SP_FS_STAGE_INSTRUCTIONS = 3,
 383         HLSQ_TP_STATE = 4,
 384         HLSQ_QUADS = 5,
 385         HLSQ_PIXELS = 6,
 386         HLSQ_VERTICES = 7,
 387         HLSQ_SP_VS_STAGE_DATA_BYTES = 13,
 388         HLSQ_SP_FS_STAGE_DATA_BYTES = 14,
 389         HLSQ_BUSY_CYCLES = 15,
 390         HLSQ_STALL_CYCLES_SP_STATE = 16,
 391         HLSQ_STALL_CYCLES_SP_VS_STAGE = 17,
 392         HLSQ_STALL_CYCLES_SP_FS_STAGE = 18,
 393         HLSQ_STALL_CYCLES_UCHE = 19,
 394         HLSQ_RBBM_LOAD_CYCLES = 20,
 395         HLSQ_DI_TO_VS_START_SP = 21,
 396         HLSQ_DI_TO_FS_START_SP = 22,
 397         HLSQ_VS_STAGE_START_TO_DONE_SP = 23,
 398         HLSQ_FS_STAGE_START_TO_DONE_SP = 24,
 399         HLSQ_SP_STATE_COPY_CYCLES_VS_STAGE = 25,
 400         HLSQ_SP_STATE_COPY_CYCLES_FS_STAGE = 26,
 401         HLSQ_UCHE_LATENCY_CYCLES = 27,
 402         HLSQ_UCHE_LATENCY_COUNT = 28,
 403         HLSQ_STARVE_CYCLES_VFD = 29,
 404 };
 405
 406 enum a4xx_pc_perfcounter_select {
 407         PC_VIS_STREAMS_LOADED = 0,
 408         PC_VPC_PRIMITIVES = 2,
 409         PC_DEAD_PRIM = 3,
 410         PC_LIVE_PRIM = 4,
 411         PC_DEAD_DRAWCALLS = 5,
 412         PC_LIVE_DRAWCALLS = 6,
 413         PC_VERTEX_MISSES = 7,
 414         PC_STALL_CYCLES_VFD = 9,
 415         PC_STALL_CYCLES_TSE = 10,
 416         PC_STALL_CYCLES_UCHE = 11,
 417         PC_WORKING_CYCLES = 12,
 418         PC_IA_VERTICES = 13,
 419         PC_GS_PRIMITIVES = 14,
 420         PC_HS_INVOCATIONS = 15,
 421         PC_DS_INVOCATIONS = 16,
 422         PC_DS_PRIMITIVES = 17,
 423         PC_STARVE_CYCLES_FOR_INDEX = 20,
 424         PC_STARVE_CYCLES_FOR_TESS_FACTOR = 21,
 425         PC_STARVE_CYCLES_FOR_VIZ_STREAM = 22,
 426         PC_STALL_CYCLES_TESS = 23,
 427         PC_STARVE_CYCLES_FOR_POSITION = 24,
 428         PC_MODE0_DRAWCALL = 25,
 429         PC_MODE1_DRAWCALL = 26,
 430         PC_MODE2_DRAWCALL = 27,
 431         PC_MODE3_DRAWCALL = 28,
 432         PC_MODE4_DRAWCALL = 29,
 433         PC_PREDICATED_DEAD_DRAWCALL = 30,
 434         PC_STALL_CYCLES_BY_TSE_ONLY = 31,
 435         PC_STALL_CYCLES_BY_VPC_ONLY = 32,
 436         PC_VPC_POS_DATA_TRANSACTION = 33,
 437         PC_BUSY_CYCLES = 34,
 438         PC_STARVE_CYCLES_DI = 35,
 439         PC_STALL_CYCLES_VPC = 36,
 440         TESS_WORKING_CYCLES = 37,
 441         TESS_NUM_CYCLES_SETUP_WORKING = 38,
 442         TESS_NUM_CYCLES_PTGEN_WORKING = 39,
 443         TESS_NUM_CYCLES_CONNGEN_WORKING = 40,
 444         TESS_BUSY_CYCLES = 41,
 445         TESS_STARVE_CYCLES_PC = 42,
 446         TESS_STALL_CYCLES_PC = 43,
 447 };
 448
 449 enum a4xx_pwr_perfcounter_select {
 450         PWR_CORE_CLOCK_CYCLES = 0,
 451         PWR_BUSY_CLOCK_CYCLES = 1,
 452 };
 453
 454 enum a4xx_rb_perfcounter_select {
 455         RB_BUSY_CYCLES = 0,
 456         RB_BUSY_CYCLES_BINNING = 1,
 457         RB_BUSY_CYCLES_RENDERING = 2,
 458         RB_BUSY_CYCLES_RESOLVE = 3,
 459         RB_STARVE_CYCLES_BY_SP = 4,
 460         RB_STARVE_CYCLES_BY_RAS = 5,
 461         RB_STARVE_CYCLES_BY_MARB = 6,
 462         RB_STALL_CYCLES_BY_MARB = 7,
 463         RB_STALL_CYCLES_BY_HLSQ = 8,
 464         RB_RB_RB_MARB_DATA = 9,
 465         RB_SP_RB_QUAD = 10,
 466         RB_RAS_RB_Z_QUADS = 11,
 467         RB_GMEM_CH0_READ = 12,
 468         RB_GMEM_CH1_READ = 13,
 469         RB_GMEM_CH0_WRITE = 14,
 470         RB_GMEM_CH1_WRITE = 15,
 471         RB_CP_CONTEXT_DONE = 16,
 472         RB_CP_CACHE_FLUSH = 17,
 473         RB_CP_ZPASS_DONE = 18,
 474         RB_STALL_FIFO0_FULL = 19,
 475         RB_STALL_FIFO1_FULL = 20,
 476         RB_STALL_FIFO2_FULL = 21,
 477         RB_STALL_FIFO3_FULL = 22,
 478         RB_RB_HLSQ_TRANSACTIONS = 23,
 479         RB_Z_READ = 24,
 480         RB_Z_WRITE = 25,
 481         RB_C_READ = 26,
 482         RB_C_WRITE = 27,
 483         RB_C_READ_LATENCY = 28,
 484         RB_Z_READ_LATENCY = 29,
 485         RB_STALL_BY_UCHE = 30,
 486         RB_MARB_UCHE_TRANSACTIONS = 31,
 487         RB_CACHE_STALL_MISS = 32,
 488         RB_CACHE_STALL_FIFO_FULL = 33,
 489         RB_8BIT_BLENDER_UNITS_ACTIVE = 34,
 490         RB_16BIT_BLENDER_UNITS_ACTIVE = 35,
 491         RB_SAMPLER_UNITS_ACTIVE = 36,
 492         RB_TOTAL_PASS = 38,
 493         RB_Z_PASS = 39,
 494         RB_Z_FAIL = 40,
 495         RB_S_FAIL = 41,
 496         RB_POWER0 = 42,
 497         RB_POWER1 = 43,
 498         RB_POWER2 = 44,
 499         RB_POWER3 = 45,
 500         RB_POWER4 = 46,
 501         RB_POWER5 = 47,
 502         RB_POWER6 = 48,
 503         RB_POWER7 = 49,
 504 };
 505
 506 enum a4xx_rbbm_perfcounter_select {
 507         RBBM_ALWAYS_ON = 0,
 508         RBBM_VBIF_BUSY = 1,
 509         RBBM_TSE_BUSY = 2,
 510         RBBM_RAS_BUSY = 3,
 511         RBBM_PC_DCALL_BUSY = 4,
 512         RBBM_PC_VSD_BUSY = 5,
 513         RBBM_VFD_BUSY = 6,
 514         RBBM_VPC_BUSY = 7,
 515         RBBM_UCHE_BUSY = 8,
 516         RBBM_VSC_BUSY = 9,
 517         RBBM_HLSQ_BUSY = 10,
 518         RBBM_ANY_RB_BUSY = 11,
 519         RBBM_ANY_TPL1_BUSY = 12,
 520         RBBM_ANY_SP_BUSY = 13,
 521         RBBM_ANY_MARB_BUSY = 14,
 522         RBBM_ANY_ARB_BUSY = 15,
 523         RBBM_AHB_STATUS_BUSY = 16,
 524         RBBM_AHB_STATUS_STALLED = 17,
 525         RBBM_AHB_STATUS_TXFR = 18,
 526         RBBM_AHB_STATUS_TXFR_SPLIT = 19,
 527         RBBM_AHB_STATUS_TXFR_ERROR = 20,
 528         RBBM_AHB_STATUS_LONG_STALL = 21,
 529         RBBM_STATUS_MASKED = 22,
 530         RBBM_CP_BUSY_GFX_CORE_IDLE = 23,
 531         RBBM_TESS_BUSY = 24,
 532         RBBM_COM_BUSY = 25,
 533         RBBM_DCOM_BUSY = 32,
 534         RBBM_ANY_CCU_BUSY = 33,
 535         RBBM_DPM_BUSY = 34,
 536 };
 537
 538 enum a4xx_sp_perfcounter_select {
 539         SP_LM_LOAD_INSTRUCTIONS = 0,
 540         SP_LM_STORE_INSTRUCTIONS = 1,
 541         SP_LM_ATOMICS = 2,
 542         SP_GM_LOAD_INSTRUCTIONS = 3,
 543         SP_GM_STORE_INSTRUCTIONS = 4,
 544         SP_GM_ATOMICS = 5,
 545         SP_VS_STAGE_TEX_INSTRUCTIONS = 6,
 546         SP_VS_STAGE_CFLOW_INSTRUCTIONS = 7,
 547         SP_VS_STAGE_EFU_INSTRUCTIONS = 8,
 548         SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 9,
 549         SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 10,
 550         SP_FS_STAGE_TEX_INSTRUCTIONS = 11,
 551         SP_FS_STAGE_CFLOW_INSTRUCTIONS = 12,
 552         SP_FS_STAGE_EFU_INSTRUCTIONS = 13,
 553         SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 14,
 554         SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 15,
 555         SP_VS_INSTRUCTIONS = 17,
 556         SP_FS_INSTRUCTIONS = 18,
 557         SP_ADDR_LOCK_COUNT = 19,
 558         SP_UCHE_READ_TRANS = 20,
 559         SP_UCHE_WRITE_TRANS = 21,
 560         SP_EXPORT_VPC_TRANS = 22,
 561         SP_EXPORT_RB_TRANS = 23,
 562         SP_PIXELS_KILLED = 24,
 563         SP_ICL1_REQUESTS = 25,
 564         SP_ICL1_MISSES = 26,
 565         SP_ICL0_REQUESTS = 27,
 566         SP_ICL0_MISSES = 28,
 567         SP_ALU_WORKING_CYCLES = 29,
 568         SP_EFU_WORKING_CYCLES = 30,
 569         SP_STALL_CYCLES_BY_VPC = 31,
 570         SP_STALL_CYCLES_BY_TP = 32,
 571         SP_STALL_CYCLES_BY_UCHE = 33,
 572         SP_STALL_CYCLES_BY_RB = 34,
 573         SP_BUSY_CYCLES = 35,
 574         SP_HS_INSTRUCTIONS = 36,
 575         SP_DS_INSTRUCTIONS = 37,
 576         SP_GS_INSTRUCTIONS = 38,
 577         SP_CS_INSTRUCTIONS = 39,
 578         SP_SCHEDULER_NON_WORKING = 40,
 579         SP_WAVE_CONTEXTS = 41,
 580         SP_WAVE_CONTEXT_CYCLES = 42,
 581         SP_POWER0 = 43,
 582         SP_POWER1 = 44,
 583         SP_POWER2 = 45,
 584         SP_POWER3 = 46,
 585         SP_POWER4 = 47,
 586         SP_POWER5 = 48,
 587         SP_POWER6 = 49,
 588         SP_POWER7 = 50,
 589         SP_POWER8 = 51,
 590         SP_POWER9 = 52,
 591         SP_POWER10 = 53,
 592         SP_POWER11 = 54,
 593         SP_POWER12 = 55,
 594         SP_POWER13 = 56,
 595         SP_POWER14 = 57,
 596         SP_POWER15 = 58,
 597 };
 598
 599 enum a4xx_tp_perfcounter_select {
 600         TP_L1_REQUESTS = 0,
 601         TP_L1_MISSES = 1,
 602         TP_QUADS_OFFSET = 8,
 603         TP_QUAD_SHADOW = 9,
 604         TP_QUADS_ARRAY = 10,
 605         TP_QUADS_GRADIENT = 11,
 606         TP_QUADS_1D2D = 12,
 607         TP_QUADS_3DCUBE = 13,
 608         TP_BUSY_CYCLES = 16,
 609         TP_STALL_CYCLES_BY_ARB = 17,
 610         TP_STATE_CACHE_REQUESTS = 20,
 611         TP_STATE_CACHE_MISSES = 21,
 612         TP_POWER0 = 22,
 613         TP_POWER1 = 23,
 614         TP_POWER2 = 24,
 615         TP_POWER3 = 25,
 616         TP_POWER4 = 26,
 617         TP_POWER5 = 27,
 618         TP_POWER6 = 28,
 619         TP_POWER7 = 29,
 620 };
 621
 622 enum a4xx_uche_perfcounter_select {
 623         UCHE_VBIF_READ_BEATS_TP = 0,
 624         UCHE_VBIF_READ_BEATS_VFD = 1,
 625         UCHE_VBIF_READ_BEATS_HLSQ = 2,
 626         UCHE_VBIF_READ_BEATS_MARB = 3,
 627         UCHE_VBIF_READ_BEATS_SP = 4,
 628         UCHE_READ_REQUESTS_TP = 5,
 629         UCHE_READ_REQUESTS_VFD = 6,
 630         UCHE_READ_REQUESTS_HLSQ = 7,
 631         UCHE_READ_REQUESTS_MARB = 8,
 632         UCHE_READ_REQUESTS_SP = 9,
 633         UCHE_WRITE_REQUESTS_MARB = 10,
 634         UCHE_WRITE_REQUESTS_SP = 11,
 635         UCHE_TAG_CHECK_FAILS = 12,
 636         UCHE_EVICTS = 13,
 637         UCHE_FLUSHES = 14,
 638         UCHE_VBIF_LATENCY_CYCLES = 15,
 639         UCHE_VBIF_LATENCY_SAMPLES = 16,
 640         UCHE_BUSY_CYCLES = 17,
 641         UCHE_VBIF_READ_BEATS_PC = 18,
 642         UCHE_READ_REQUESTS_PC = 19,
 643         UCHE_WRITE_REQUESTS_VPC = 20,
 644         UCHE_STALL_BY_VBIF = 21,
 645         UCHE_WRITE_REQUESTS_VSC = 22,
 646         UCHE_POWER0 = 23,
 647         UCHE_POWER1 = 24,
 648         UCHE_POWER2 = 25,
 649         UCHE_POWER3 = 26,
 650         UCHE_POWER4 = 27,
 651         UCHE_POWER5 = 28,
 652         UCHE_POWER6 = 29,
 653         UCHE_POWER7 = 30,
 654 };
 655
 656 enum a4xx_vbif_perfcounter_select {
 657         AXI_READ_REQUESTS_ID_0 = 0,
 658         AXI_READ_REQUESTS_ID_1 = 1,
 659         AXI_READ_REQUESTS_ID_2 = 2,
 660         AXI_READ_REQUESTS_ID_3 = 3,
 661         AXI_READ_REQUESTS_ID_4 = 4,
 662         AXI_READ_REQUESTS_ID_5 = 5,
 663         AXI_READ_REQUESTS_ID_6 = 6,
 664         AXI_READ_REQUESTS_ID_7 = 7,
 665         AXI_READ_REQUESTS_ID_8 = 8,
 666         AXI_READ_REQUESTS_ID_9 = 9,
 667         AXI_READ_REQUESTS_ID_10 = 10,
 668         AXI_READ_REQUESTS_ID_11 = 11,
 669         AXI_READ_REQUESTS_ID_12 = 12,
 670         AXI_READ_REQUESTS_ID_13 = 13,
 671         AXI_READ_REQUESTS_ID_14 = 14,
 672         AXI_READ_REQUESTS_ID_15 = 15,
 673         AXI0_READ_REQUESTS_TOTAL = 16,
 674         AXI1_READ_REQUESTS_TOTAL = 17,
 675         AXI2_READ_REQUESTS_TOTAL = 18,
 676         AXI3_READ_REQUESTS_TOTAL = 19,
 677         AXI_READ_REQUESTS_TOTAL = 20,
 678         AXI_WRITE_REQUESTS_ID_0 = 21,
 679         AXI_WRITE_REQUESTS_ID_1 = 22,
 680         AXI_WRITE_REQUESTS_ID_2 = 23,
 681         AXI_WRITE_REQUESTS_ID_3 = 24,
 682         AXI_WRITE_REQUESTS_ID_4 = 25,
 683         AXI_WRITE_REQUESTS_ID_5 = 26,
 684         AXI_WRITE_REQUESTS_ID_6 = 27,
 685         AXI_WRITE_REQUESTS_ID_7 = 28,
 686         AXI_WRITE_REQUESTS_ID_8 = 29,
 687         AXI_WRITE_REQUESTS_ID_9 = 30,
 688         AXI_WRITE_REQUESTS_ID_10 = 31,
 689         AXI_WRITE_REQUESTS_ID_11 = 32,
 690         AXI_WRITE_REQUESTS_ID_12 = 33,
 691         AXI_WRITE_REQUESTS_ID_13 = 34,
 692         AXI_WRITE_REQUESTS_ID_14 = 35,
 693         AXI_WRITE_REQUESTS_ID_15 = 36,
 694         AXI0_WRITE_REQUESTS_TOTAL = 37,
 695         AXI1_WRITE_REQUESTS_TOTAL = 38,
 696         AXI2_WRITE_REQUESTS_TOTAL = 39,
 697         AXI3_WRITE_REQUESTS_TOTAL = 40,
 698         AXI_WRITE_REQUESTS_TOTAL = 41,
 699         AXI_TOTAL_REQUESTS = 42,
 700         AXI_READ_DATA_BEATS_ID_0 = 43,
 701         AXI_READ_DATA_BEATS_ID_1 = 44,
 702         AXI_READ_DATA_BEATS_ID_2 = 45,
 703         AXI_READ_DATA_BEATS_ID_3 = 46,
 704         AXI_READ_DATA_BEATS_ID_4 = 47,
 705         AXI_READ_DATA_BEATS_ID_5 = 48,
 706         AXI_READ_DATA_BEATS_ID_6 = 49,
 707         AXI_READ_DATA_BEATS_ID_7 = 50,
 708         AXI_READ_DATA_BEATS_ID_8 = 51,
 709         AXI_READ_DATA_BEATS_ID_9 = 52,
 710         AXI_READ_DATA_BEATS_ID_10 = 53,
 711         AXI_READ_DATA_BEATS_ID_11 = 54,
 712         AXI_READ_DATA_BEATS_ID_12 = 55,
 713         AXI_READ_DATA_BEATS_ID_13 = 56,
 714         AXI_READ_DATA_BEATS_ID_14 = 57,
 715         AXI_READ_DATA_BEATS_ID_15 = 58,
 716         AXI0_READ_DATA_BEATS_TOTAL = 59,
 717         AXI1_READ_DATA_BEATS_TOTAL = 60,
 718         AXI2_READ_DATA_BEATS_TOTAL = 61,
 719         AXI3_READ_DATA_BEATS_TOTAL = 62,
 720         AXI_READ_DATA_BEATS_TOTAL = 63,
 721         AXI_WRITE_DATA_BEATS_ID_0 = 64,
 722         AXI_WRITE_DATA_BEATS_ID_1 = 65,
 723         AXI_WRITE_DATA_BEATS_ID_2 = 66,
 724         AXI_WRITE_DATA_BEATS_ID_3 = 67,
 725         AXI_WRITE_DATA_BEATS_ID_4 = 68,
 726         AXI_WRITE_DATA_BEATS_ID_5 = 69,
 727         AXI_WRITE_DATA_BEATS_ID_6 = 70,
 728         AXI_WRITE_DATA_BEATS_ID_7 = 71,
 729         AXI_WRITE_DATA_BEATS_ID_8 = 72,
 730         AXI_WRITE_DATA_BEATS_ID_9 = 73,
 731         AXI_WRITE_DATA_BEATS_ID_10 = 74,
 732         AXI_WRITE_DATA_BEATS_ID_11 = 75,
 733         AXI_WRITE_DATA_BEATS_ID_12 = 76,
 734         AXI_WRITE_DATA_BEATS_ID_13 = 77,
 735         AXI_WRITE_DATA_BEATS_ID_14 = 78,
 736         AXI_WRITE_DATA_BEATS_ID_15 = 79,
 737         AXI0_WRITE_DATA_BEATS_TOTAL = 80,
 738         AXI1_WRITE_DATA_BEATS_TOTAL = 81,
 739         AXI2_WRITE_DATA_BEATS_TOTAL = 82,
 740         AXI3_WRITE_DATA_BEATS_TOTAL = 83,
 741         AXI_WRITE_DATA_BEATS_TOTAL = 84,
 742         AXI_DATA_BEATS_TOTAL = 85,
 743         CYCLES_HELD_OFF_ID_0 = 86,
 744         CYCLES_HELD_OFF_ID_1 = 87,
 745         CYCLES_HELD_OFF_ID_2 = 88,
 746         CYCLES_HELD_OFF_ID_3 = 89,
 747         CYCLES_HELD_OFF_ID_4 = 90,
 748         CYCLES_HELD_OFF_ID_5 = 91,
 749         CYCLES_HELD_OFF_ID_6 = 92,
 750         CYCLES_HELD_OFF_ID_7 = 93,
 751         CYCLES_HELD_OFF_ID_8 = 94,
 752         CYCLES_HELD_OFF_ID_9 = 95,
 753         CYCLES_HELD_OFF_ID_10 = 96,
 754         CYCLES_HELD_OFF_ID_11 = 97,
 755         CYCLES_HELD_OFF_ID_12 = 98,
 756         CYCLES_HELD_OFF_ID_13 = 99,
 757         CYCLES_HELD_OFF_ID_14 = 100,
 758         CYCLES_HELD_OFF_ID_15 = 101,
 759         AXI_READ_REQUEST_HELD_OFF = 102,
 760         AXI_WRITE_REQUEST_HELD_OFF = 103,
 761         AXI_REQUEST_HELD_OFF = 104,
 762         AXI_WRITE_DATA_HELD_OFF = 105,
 763         OCMEM_AXI_READ_REQUEST_HELD_OFF = 106,
 764         OCMEM_AXI_WRITE_REQUEST_HELD_OFF = 107,
 765         OCMEM_AXI_REQUEST_HELD_OFF = 108,
 766         OCMEM_AXI_WRITE_DATA_HELD_OFF = 109,
 767         ELAPSED_CYCLES_DDR = 110,
 768         ELAPSED_CYCLES_OCMEM = 111,
 769 };
 770
 771 enum a4xx_vfd_perfcounter_select {
 772         VFD_UCHE_BYTE_FETCHED = 0,
 773         VFD_UCHE_TRANS = 1,
 774         VFD_FETCH_INSTRUCTIONS = 3,
 775         VFD_BUSY_CYCLES = 5,
 776         VFD_STALL_CYCLES_UCHE = 6,
 777         VFD_STALL_CYCLES_HLSQ = 7,
 778         VFD_STALL_CYCLES_VPC_BYPASS = 8,
 779         VFD_STALL_CYCLES_VPC_ALLOC = 9,
 780         VFD_MODE_0_FIBERS = 13,
 781         VFD_MODE_1_FIBERS = 14,
 782         VFD_MODE_2_FIBERS = 15,
 783         VFD_MODE_3_FIBERS = 16,
 784         VFD_MODE_4_FIBERS = 17,
 785         VFD_BFIFO_STALL = 18,
 786         VFD_NUM_VERTICES_TOTAL = 19,
 787         VFD_PACKER_FULL = 20,
 788         VFD_UCHE_REQUEST_FIFO_FULL = 21,
 789         VFD_STARVE_CYCLES_PC = 22,
 790         VFD_STARVE_CYCLES_UCHE = 23,
 791 };
 792
 793 enum a4xx_vpc_perfcounter_select {
 794         VPC_SP_LM_COMPONENTS = 2,
 795         VPC_SP0_LM_BYTES = 3,
 796         VPC_SP1_LM_BYTES = 4,
 797         VPC_SP2_LM_BYTES = 5,
 798         VPC_SP3_LM_BYTES = 6,
 799         VPC_WORKING_CYCLES = 7,
 800         VPC_STALL_CYCLES_LM = 8,
 801         VPC_STARVE_CYCLES_RAS = 9,
 802         VPC_STREAMOUT_CYCLES = 10,
 803         VPC_UCHE_TRANSACTIONS = 12,
 804         VPC_STALL_CYCLES_UCHE = 13,
 805         VPC_BUSY_CYCLES = 14,
 806         VPC_STARVE_CYCLES_SP = 15,
 807 };
 808
 809 enum a4xx_vsc_perfcounter_select {
 810         VSC_BUSY_CYCLES = 0,
 811         VSC_WORKING_CYCLES = 1,
 812         VSC_STALL_CYCLES_UCHE = 2,
 813         VSC_STARVE_CYCLES_RAS = 3,
 814         VSC_EOT_NUM = 4,
 815 };
 816
 817 enum a4xx_tex_filter {
 818         A4XX_TEX_NEAREST = 0,
 819         A4XX_TEX_LINEAR = 1,
 820         A4XX_TEX_ANISO = 2,
 821 };
 822
 823 enum a4xx_tex_clamp {
 824         A4XX_TEX_REPEAT = 0,
 825         A4XX_TEX_CLAMP_TO_EDGE = 1,
 826         A4XX_TEX_MIRROR_REPEAT = 2,
 827         A4XX_TEX_CLAMP_TO_BORDER = 3,
 828         A4XX_TEX_MIRROR_CLAMP = 4,
 829 };
 830
 831 enum a4xx_tex_aniso {
 832         A4XX_TEX_ANISO_1 = 0,
 833         A4XX_TEX_ANISO_2 = 1,
 834         A4XX_TEX_ANISO_4 = 2,
 835         A4XX_TEX_ANISO_8 = 3,
 836         A4XX_TEX_ANISO_16 = 4,
 837 };
 838
 839 enum a4xx_tex_swiz {
 840         A4XX_TEX_X = 0,
 841         A4XX_TEX_Y = 1,
 842         A4XX_TEX_Z = 2,
 843         A4XX_TEX_W = 3,
 844         A4XX_TEX_ZERO = 4,
 845         A4XX_TEX_ONE = 5,
 846 };
 847
 848 enum a4xx_tex_type {
 849         A4XX_TEX_1D = 0,
 850         A4XX_TEX_2D = 1,
 851         A4XX_TEX_CUBE = 2,
 852         A4XX_TEX_3D = 3,
 853 };
 854
 855 #define A4XX_CGC_HLSQ_EARLY_CYC__MASK                           0x00700000
 856 #define A4XX_CGC_HLSQ_EARLY_CYC__SHIFT                          20
 857 static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val)
 858 {
 859         return ((val) << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT) & A4XX_CGC_HLSQ_EARLY_CYC__MASK;
 860 }
 861 #define A4XX_INT0_RBBM_GPU_IDLE                                 0x00000001
 862 #define A4XX_INT0_RBBM_AHB_ERROR                                0x00000002
 863 #define A4XX_INT0_RBBM_REG_TIMEOUT                              0x00000004
 864 #define A4XX_INT0_RBBM_ME_MS_TIMEOUT                            0x00000008
 865 #define A4XX_INT0_RBBM_PFP_MS_TIMEOUT                           0x00000010
 866 #define A4XX_INT0_RBBM_ATB_BUS_OVERFLOW                         0x00000020
 867 #define A4XX_INT0_VFD_ERROR                                     0x00000040
 868 #define A4XX_INT0_CP_SW_INT                                     0x00000080
 869 #define A4XX_INT0_CP_T0_PACKET_IN_IB                            0x00000100
 870 #define A4XX_INT0_CP_OPCODE_ERROR                               0x00000200
 871 #define A4XX_INT0_CP_RESERVED_BIT_ERROR                         0x00000400
 872 #define A4XX_INT0_CP_HW_FAULT                                   0x00000800
 873 #define A4XX_INT0_CP_DMA                                        0x00001000
 874 #define A4XX_INT0_CP_IB2_INT                                    0x00002000
 875 #define A4XX_INT0_CP_IB1_INT                                    0x00004000
 876 #define A4XX_INT0_CP_RB_INT                                     0x00008000
 877 #define A4XX_INT0_CP_REG_PROTECT_FAULT                          0x00010000
 878 #define A4XX_INT0_CP_RB_DONE_TS                                 0x00020000
 879 #define A4XX_INT0_CP_VS_DONE_TS                                 0x00040000
 880 #define A4XX_INT0_CP_PS_DONE_TS                                 0x00080000
 881 #define A4XX_INT0_CACHE_FLUSH_TS                                0x00100000
 882 #define A4XX_INT0_CP_AHB_ERROR_HALT                             0x00200000
 883 #define A4XX_INT0_MISC_HANG_DETECT                              0x01000000
 884 #define A4XX_INT0_UCHE_OOB_ACCESS                               0x02000000
 885 #define REG_A4XX_RB_GMEM_BASE_ADDR                              0x00000cc0
 886
 887 #define REG_A4XX_RB_PERFCTR_RB_SEL_0                            0x00000cc7
 888
 889 #define REG_A4XX_RB_PERFCTR_RB_SEL_1                            0x00000cc8
 890
 891 #define REG_A4XX_RB_PERFCTR_RB_SEL_2                            0x00000cc9
 892
 893 #define REG_A4XX_RB_PERFCTR_RB_SEL_3                            0x00000cca
 894
 895 #define REG_A4XX_RB_PERFCTR_RB_SEL_4                            0x00000ccb
 896
 897 #define REG_A4XX_RB_PERFCTR_RB_SEL_5                            0x00000ccc
 898
 899 #define REG_A4XX_RB_PERFCTR_RB_SEL_6                            0x00000ccd
 900
 901 #define REG_A4XX_RB_PERFCTR_RB_SEL_7                            0x00000cce
 902
 903 #define REG_A4XX_RB_PERFCTR_CCU_SEL_0                           0x00000ccf
 904
 905 #define REG_A4XX_RB_PERFCTR_CCU_SEL_1                           0x00000cd0
 906
 907 #define REG_A4XX_RB_PERFCTR_CCU_SEL_2                           0x00000cd1
 908
 909 #define REG_A4XX_RB_PERFCTR_CCU_SEL_3                           0x00000cd2
 910
 911 #define REG_A4XX_RB_FRAME_BUFFER_DIMENSION                      0x00000ce0
 912 #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK              0x00003fff
 913 #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT             0
 914 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val)
 915 {
 916         return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK;
 917 }
 918 #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK             0x3fff0000
 919 #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT            16
 920 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val)
 921 {
 922         return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK;
 923 }
 924
 925 #define REG_A4XX_RB_CLEAR_COLOR_DW0                             0x000020cc
 926
 927 #define REG_A4XX_RB_CLEAR_COLOR_DW1                             0x000020cd
 928
 929 #define REG_A4XX_RB_CLEAR_COLOR_DW2                             0x000020ce
 930
 931 #define REG_A4XX_RB_CLEAR_COLOR_DW3                             0x000020cf
 932
 933 #define REG_A4XX_RB_MODE_CONTROL                                0x000020a0
 934 #define A4XX_RB_MODE_CONTROL_WIDTH__MASK                        0x0000003f
 935 #define A4XX_RB_MODE_CONTROL_WIDTH__SHIFT                       0
 936 static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val)
 937 {
 938         return ((val >> 5) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK;
 939 }
 940 #define A4XX_RB_MODE_CONTROL_HEIGHT__MASK                       0x00003f00
 941 #define A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT                      8
 942 static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val)
 943 {
 944         return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK;
 945 }
 946 #define A4XX_RB_MODE_CONTROL_ENABLE_GMEM                        0x00010000
 947
 948 #define REG_A4XX_RB_RENDER_CONTROL                              0x000020a1
 949 #define A4XX_RB_RENDER_CONTROL_BINNING_PASS                     0x00000001
 950 #define A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE               0x00000020
 951
 952 #define REG_A4XX_RB_MSAA_CONTROL                                0x000020a2
 953 #define A4XX_RB_MSAA_CONTROL_DISABLE                            0x00001000
 954 #define A4XX_RB_MSAA_CONTROL_SAMPLES__MASK                      0x0000e000
 955 #define A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT                     13
 956 static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val)
 957 {
 958         return ((val) << A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A4XX_RB_MSAA_CONTROL_SAMPLES__MASK;
 959 }
 960
 961 #define REG_A4XX_RB_RENDER_CONTROL2                             0x000020a3
 962 #define A4XX_RB_RENDER_CONTROL2_XCOORD                          0x00000001
 963 #define A4XX_RB_RENDER_CONTROL2_YCOORD                          0x00000002
 964 #define A4XX_RB_RENDER_CONTROL2_ZCOORD                          0x00000004
 965 #define A4XX_RB_RENDER_CONTROL2_WCOORD                          0x00000008
 966 #define A4XX_RB_RENDER_CONTROL2_SAMPLEMASK                      0x00000010
 967 #define A4XX_RB_RENDER_CONTROL2_FACENESS                        0x00000020
 968 #define A4XX_RB_RENDER_CONTROL2_SAMPLEID                        0x00000040
 969 #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK              0x00000380
 970 #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT             7
 971 static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val)
 972 {
 973         return ((val) << A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT) & A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK;
 974 }
 975 #define A4XX_RB_RENDER_CONTROL2_SAMPLEID_HR                     0x00000800
 976 #define A4XX_RB_RENDER_CONTROL2_VARYING                         0x00001000
 977
 978 static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
 979
 980 static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
 981 #define A4XX_RB_MRT_CONTROL_READ_DEST_ENABLE                    0x00000008
 982 #define A4XX_RB_MRT_CONTROL_BLEND                               0x00000010
 983 #define A4XX_RB_MRT_CONTROL_BLEND2                              0x00000020
 984 #define A4XX_RB_MRT_CONTROL_ROP_ENABLE                          0x00000040
 985 #define A4XX_RB_MRT_CONTROL_ROP_CODE__MASK                      0x00000f00
 986 #define A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT                     8
 987 static inline uint32_t A4XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
 988 {
 989         return ((val) << A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A4XX_RB_MRT_CONTROL_ROP_CODE__MASK;
 990 }
 991 #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK              0x0f000000
 992 #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT             24
 993 static inline uint32_t A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
 994 {
 995         return ((val) << A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
 996 }
 997
 998 static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020a5 + 0x5*i0; }
 999 #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK                 0x0000003f
1000 #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT                0
1001 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a4xx_color_fmt val)
1002 {
1003         return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
1004 }
1005 #define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK              0x000000c0
1006 #define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT             6
1007 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a4xx_tile_mode val)
1008 {
1009         return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
1010 }
1011 #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK                  0x00000600
1012 #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT                 9
1013 static inline uint32_t A4XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
1014 {
1015         return ((val) << A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK;
1016 }
1017 #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK                   0x00001800
1018 #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT                  11
1019 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
1020 {
1021         return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
1022 }
1023 #define A4XX_RB_MRT_BUF_INFO_COLOR_SRGB                         0x00002000
1024 #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK              0xffffc000
1025 #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT             14
1026 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val)
1027 {
1028         return ((val >> 4) << A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK;
1029 }
1030
1031 static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; }
1032
1033 static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; }
1034 #define A4XX_RB_MRT_CONTROL3_STRIDE__MASK                       0x03fffff8
1035 #define A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT                      3
1036 static inline uint32_t A4XX_RB_MRT_CONTROL3_STRIDE(uint32_t val)
1037 {
1038         return ((val) << A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT) & A4XX_RB_MRT_CONTROL3_STRIDE__MASK;
1039 }
1040
1041 static inline uint32_t REG_A4XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020a8 + 0x5*i0; }
1042 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK          0x0000001f
1043 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT         0
1044 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
1045 {
1046         return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
1047 }
1048 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK        0x000000e0
1049 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT       5
1050 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a4xx_rb_blend_opcode val)
1051 {
1052         return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
1053 }
1054 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK         0x00001f00
1055 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT        8
1056 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
1057 {
1058         return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
1059 }
1060 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK        0x001f0000
1061 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT       16
1062 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
1063 {
1064         return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
1065 }
1066 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK      0x00e00000
1067 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT     21
1068 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a4xx_rb_blend_opcode val)
1069 {
1070         return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
1071 }
1072 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK       0x1f000000
1073 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT      24
1074 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
1075 {
1076         return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
1077 }
1078
1079 #define REG_A4XX_RB_BLEND_RED                                   0x000020f0
1080 #define A4XX_RB_BLEND_RED_UINT__MASK                            0x000000ff
1081 #define A4XX_RB_BLEND_RED_UINT__SHIFT                           0
1082 static inline uint32_t A4XX_RB_BLEND_RED_UINT(uint32_t val)
1083 {
1084         return ((val) << A4XX_RB_BLEND_RED_UINT__SHIFT) & A4XX_RB_BLEND_RED_UINT__MASK;
1085 }
1086 #define A4XX_RB_BLEND_RED_SINT__MASK                            0x0000ff00
1087 #define A4XX_RB_BLEND_RED_SINT__SHIFT                           8
1088 static inline uint32_t A4XX_RB_BLEND_RED_SINT(uint32_t val)
1089 {
1090         return ((val) << A4XX_RB_BLEND_RED_SINT__SHIFT) & A4XX_RB_BLEND_RED_SINT__MASK;
1091 }
1092 #define A4XX_RB_BLEND_RED_FLOAT__MASK                           0xffff0000
1093 #define A4XX_RB_BLEND_RED_FLOAT__SHIFT                          16
1094 static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val)
1095 {
1096         return ((util_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK;
1097 }
1098
1099 #define REG_A4XX_RB_BLEND_RED_F32                               0x000020f1
1100 #define A4XX_RB_BLEND_RED_F32__MASK                             0xffffffff
1101 #define A4XX_RB_BLEND_RED_F32__SHIFT                            0
1102 static inline uint32_t A4XX_RB_BLEND_RED_F32(float val)
1103 {
1104         return ((fui(val)) << A4XX_RB_BLEND_RED_F32__SHIFT) & A4XX_RB_BLEND_RED_F32__MASK;
1105 }
1106
1107 #define REG_A4XX_RB_BLEND_GREEN                                 0x000020f2
1108 #define A4XX_RB_BLEND_GREEN_UINT__MASK                          0x000000ff
1109 #define A4XX_RB_BLEND_GREEN_UINT__SHIFT                         0
1110 static inline uint32_t A4XX_RB_BLEND_GREEN_UINT(uint32_t val)
1111 {
1112         return ((val) << A4XX_RB_BLEND_GREEN_UINT__SHIFT) & A4XX_RB_BLEND_GREEN_UINT__MASK;
1113 }
1114 #define A4XX_RB_BLEND_GREEN_SINT__MASK                          0x0000ff00
1115 #define A4XX_RB_BLEND_GREEN_SINT__SHIFT                         8
1116 static inline uint32_t A4XX_RB_BLEND_GREEN_SINT(uint32_t val)
1117 {
1118         return ((val) << A4XX_RB_BLEND_GREEN_SINT__SHIFT) & A4XX_RB_BLEND_GREEN_SINT__MASK;
1119 }
1120 #define A4XX_RB_BLEND_GREEN_FLOAT__MASK                         0xffff0000
1121 #define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT                        16
1122 static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val)
1123 {
1124         return ((util_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK;
1125 }
1126
1127 #define REG_A4XX_RB_BLEND_GREEN_F32                             0x000020f3
1128 #define A4XX_RB_BLEND_GREEN_F32__MASK                           0xffffffff
1129 #define A4XX_RB_BLEND_GREEN_F32__SHIFT                          0
1130 static inline uint32_t A4XX_RB_BLEND_GREEN_F32(float val)
1131 {
1132         return ((fui(val)) << A4XX_RB_BLEND_GREEN_F32__SHIFT) & A4XX_RB_BLEND_GREEN_F32__MASK;
1133 }
1134
1135 #define REG_A4XX_RB_BLEND_BLUE                                  0x000020f4
1136 #define A4XX_RB_BLEND_BLUE_UINT__MASK                           0x000000ff
1137 #define A4XX_RB_BLEND_BLUE_UINT__SHIFT                          0
1138 static inline uint32_t A4XX_RB_BLEND_BLUE_UINT(uint32_t val)
1139 {
1140         return ((val) << A4XX_RB_BLEND_BLUE_UINT__SHIFT) & A4XX_RB_BLEND_BLUE_UINT__MASK;
1141 }
1142 #define A4XX_RB_BLEND_BLUE_SINT__MASK                           0x0000ff00
1143 #define A4XX_RB_BLEND_BLUE_SINT__SHIFT                          8
1144 static inline uint32_t A4XX_RB_BLEND_BLUE_SINT(uint32_t val)
1145 {
1146         return ((val) << A4XX_RB_BLEND_BLUE_SINT__SHIFT) & A4XX_RB_BLEND_BLUE_SINT__MASK;
1147 }
1148 #define A4XX_RB_BLEND_BLUE_FLOAT__MASK                          0xffff0000
1149 #define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT                         16
1150 static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val)
1151 {
1152         return ((util_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK;
1153 }
1154
1155 #define REG_A4XX_RB_BLEND_BLUE_F32                              0x000020f5
1156 #define A4XX_RB_BLEND_BLUE_F32__MASK                            0xffffffff
1157 #define A4XX_RB_BLEND_BLUE_F32__SHIFT                           0
1158 static inline uint32_t A4XX_RB_BLEND_BLUE_F32(float val)
1159 {
1160         return ((fui(val)) << A4XX_RB_BLEND_BLUE_F32__SHIFT) & A4XX_RB_BLEND_BLUE_F32__MASK;
1161 }
1162
1163 #define REG_A4XX_RB_BLEND_ALPHA                                 0x000020f6
1164 #define A4XX_RB_BLEND_ALPHA_UINT__MASK                          0x000000ff
1165 #define A4XX_RB_BLEND_ALPHA_UINT__SHIFT                         0
1166 static inline uint32_t A4XX_RB_BLEND_ALPHA_UINT(uint32_t val)
1167 {
1168         return ((val) << A4XX_RB_BLEND_ALPHA_UINT__SHIFT) & A4XX_RB_BLEND_ALPHA_UINT__MASK;
1169 }
1170 #define A4XX_RB_BLEND_ALPHA_SINT__MASK                          0x0000ff00
1171 #define A4XX_RB_BLEND_ALPHA_SINT__SHIFT                         8
1172 static inline uint32_t A4XX_RB_BLEND_ALPHA_SINT(uint32_t val)
1173 {
1174         return ((val) << A4XX_RB_BLEND_ALPHA_SINT__SHIFT) & A4XX_RB_BLEND_ALPHA_SINT__MASK;
1175 }
1176 #define A4XX_RB_BLEND_ALPHA_FLOAT__MASK                         0xffff0000
1177 #define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT                        16
1178 static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val)
1179 {
1180         return ((util_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK;
1181 }
1182
1183 #define REG_A4XX_RB_BLEND_ALPHA_F32                             0x000020f7
1184 #define A4XX_RB_BLEND_ALPHA_F32__MASK                           0xffffffff
1185 #define A4XX_RB_BLEND_ALPHA_F32__SHIFT                          0
1186 static inline uint32_t A4XX_RB_BLEND_ALPHA_F32(float val)
1187 {
1188         return ((fui(val)) << A4XX_RB_BLEND_ALPHA_F32__SHIFT) & A4XX_RB_BLEND_ALPHA_F32__MASK;
1189 }
1190
1191 #define REG_A4XX_RB_ALPHA_CONTROL                               0x000020f8
1192 #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK                   0x000000ff
1193 #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT                  0
1194 static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
1195 {
1196         return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK;
1197 }
1198 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST                        0x00000100
1199 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK             0x00000e00
1200 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT            9
1201 static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
1202 {
1203         return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK;
1204 }
1205
1206 #define REG_A4XX_RB_FS_OUTPUT                                   0x000020f9
1207 #define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK                    0x000000ff
1208 #define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT                   0
1209 static inline uint32_t A4XX_RB_FS_OUTPUT_ENABLE_BLEND(uint32_t val)
1210 {
1211         return ((val) << A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT) & A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK;
1212 }
1213 #define A4XX_RB_FS_OUTPUT_INDEPENDENT_BLEND                     0x00000100
1214 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK                     0xffff0000
1215 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT                    16
1216 static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val)
1217 {
1218         return ((val) << A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT) & A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK;
1219 }
1220
1221 #define REG_A4XX_RB_SAMPLE_COUNT_CONTROL                        0x000020fa
1222 #define A4XX_RB_SAMPLE_COUNT_CONTROL_COPY                       0x00000002
1223 #define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK                 0xfffffffc
1224 #define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT                2
1225 static inline uint32_t A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR(uint32_t val)
1226 {
1227         return ((val >> 2) << A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT) & A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK;
1228 }
1229
1230 #define REG_A4XX_RB_RENDER_COMPONENTS                           0x000020fb
1231 #define A4XX_RB_RENDER_COMPONENTS_RT0__MASK                     0x0000000f
1232 #define A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT                    0
1233 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
1234 {
1235         return ((val) << A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT0__MASK;
1236 }
1237 #define A4XX_RB_RENDER_COMPONENTS_RT1__MASK                     0x000000f0
1238 #define A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT                    4
1239 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
1240 {
1241         return ((val) << A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT1__MASK;
1242 }
1243 #define A4XX_RB_RENDER_COMPONENTS_RT2__MASK                     0x00000f00
1244 #define A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT                    8
1245 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
1246 {
1247         return ((val) << A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT2__MASK;
1248 }
1249 #define A4XX_RB_RENDER_COMPONENTS_RT3__MASK                     0x0000f000
1250 #define A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT                    12
1251 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
1252 {
1253         return ((val) << A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT3__MASK;
1254 }
1255 #define A4XX_RB_RENDER_COMPONENTS_RT4__MASK                     0x000f0000
1256 #define A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT                    16
1257 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
1258 {
1259         return ((val) << A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT4__MASK;
1260 }
1261 #define A4XX_RB_RENDER_COMPONENTS_RT5__MASK                     0x00f00000
1262 #define A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT                    20
1263 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
1264 {
1265         return ((val) << A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT5__MASK;
1266 }
1267 #define A4XX_RB_RENDER_COMPONENTS_RT6__MASK                     0x0f000000
1268 #define A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT                    24
1269 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
1270 {
1271         return ((val) << A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT6__MASK;
1272 }
1273 #define A4XX_RB_RENDER_COMPONENTS_RT7__MASK                     0xf0000000
1274 #define A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT                    28
1275 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
1276 {
1277         return ((val) << A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT7__MASK;
1278 }
1279
1280 #define REG_A4XX_RB_COPY_CONTROL                                0x000020fc
1281 #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK                 0x00000003
1282 #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT                0
1283 static inline uint32_t A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val)
1284 {
1285         return ((val) << A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK;
1286 }
1287 #define A4XX_RB_COPY_CONTROL_MODE__MASK                         0x00000070
1288 #define A4XX_RB_COPY_CONTROL_MODE__SHIFT                        4
1289 static inline uint32_t A4XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val)
1290 {
1291         return ((val) << A4XX_RB_COPY_CONTROL_MODE__SHIFT) & A4XX_RB_COPY_CONTROL_MODE__MASK;
1292 }
1293 #define A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK                    0x00000f00
1294 #define A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT                   8
1295 static inline uint32_t A4XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val)
1296 {
1297         return ((val) << A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK;
1298 }
1299 #define A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK                    0xffffc000
1300 #define A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT                   14
1301 static inline uint32_t A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val)
1302 {
1303         return ((val >> 14) << A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK;
1304 }
1305
1306 #define REG_A4XX_RB_COPY_DEST_BASE                              0x000020fd
1307 #define A4XX_RB_COPY_DEST_BASE_BASE__MASK                       0xffffffe0
1308 #define A4XX_RB_COPY_DEST_BASE_BASE__SHIFT                      5
1309 static inline uint32_t A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val)
1310 {
1311         return ((val >> 5) << A4XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A4XX_RB_COPY_DEST_BASE_BASE__MASK;
1312 }
1313
1314 #define REG_A4XX_RB_COPY_DEST_PITCH                             0x000020fe
1315 #define A4XX_RB_COPY_DEST_PITCH_PITCH__MASK                     0xffffffff
1316 #define A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT                    0
1317 static inline uint32_t A4XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val)
1318 {
1319         return ((val >> 5) << A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A4XX_RB_COPY_DEST_PITCH_PITCH__MASK;
1320 }
1321
1322 #define REG_A4XX_RB_COPY_DEST_INFO                              0x000020ff
1323 #define A4XX_RB_COPY_DEST_INFO_FORMAT__MASK                     0x000000fc
1324 #define A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT                    2
1325 static inline uint32_t A4XX_RB_COPY_DEST_INFO_FORMAT(enum a4xx_color_fmt val)
1326 {
1327         return ((val) << A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A4XX_RB_COPY_DEST_INFO_FORMAT__MASK;
1328 }
1329 #define A4XX_RB_COPY_DEST_INFO_SWAP__MASK                       0x00000300
1330 #define A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT                      8
1331 static inline uint32_t A4XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val)
1332 {
1333         return ((val) << A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A4XX_RB_COPY_DEST_INFO_SWAP__MASK;
1334 }
1335 #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK                0x00000c00
1336 #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT               10
1337 static inline uint32_t A4XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
1338 {
1339         return ((val) << A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK;
1340 }
1341 #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK           0x0003c000
1342 #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT          14
1343 static inline uint32_t A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val)
1344 {
1345         return ((val) << A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK;
1346 }
1347 #define A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK                     0x001c0000
1348 #define A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT                    18
1349 static inline uint32_t A4XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val)
1350 {
1351         return ((val) << A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK;
1352 }
1353 #define A4XX_RB_COPY_DEST_INFO_TILE__MASK                       0x03000000
1354 #define A4XX_RB_COPY_DEST_INFO_TILE__SHIFT                      24
1355 static inline uint32_t A4XX_RB_COPY_DEST_INFO_TILE(enum a4xx_tile_mode val)
1356 {
1357         return ((val) << A4XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A4XX_RB_COPY_DEST_INFO_TILE__MASK;
1358 }
1359
1360 #define REG_A4XX_RB_FS_OUTPUT_REG                               0x00002100
1361 #define A4XX_RB_FS_OUTPUT_REG_MRT__MASK                         0x0000000f
1362 #define A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT                        0
1363 static inline uint32_t A4XX_RB_FS_OUTPUT_REG_MRT(uint32_t val)
1364 {
1365         return ((val) << A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_RB_FS_OUTPUT_REG_MRT__MASK;
1366 }
1367 #define A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z                     0x00000020
1368
1369 #define REG_A4XX_RB_DEPTH_CONTROL                               0x00002101
1370 #define A4XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z                     0x00000001
1371 #define A4XX_RB_DEPTH_CONTROL_Z_ENABLE                          0x00000002
1372 #define A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE                    0x00000004
1373 #define A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK                       0x00000070
1374 #define A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT                      4
1375 static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val)
1376 {
1377         return ((val) << A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK;
1378 }
1379 #define A4XX_RB_DEPTH_CONTROL_BF_ENABLE                         0x00000080
1380 #define A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE                   0x00010000
1381 #define A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS                 0x00020000
1382 #define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE                     0x80000000
1383
1384 #define REG_A4XX_RB_DEPTH_CLEAR                                 0x00002102
1385
1386 #define REG_A4XX_RB_DEPTH_INFO                                  0x00002103
1387 #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK                   0x00000003
1388 #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT                  0
1389 static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum a4xx_depth_format val)
1390 {
1391         return ((val) << A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK;
1392 }
1393 #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK                     0xfffff000
1394 #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT                    12
1395 static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
1396 {
1397         return ((val >> 12) << A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
1398 }
1399
1400 #define REG_A4XX_RB_DEPTH_PITCH                                 0x00002104
1401 #define A4XX_RB_DEPTH_PITCH__MASK                               0xffffffff
1402 #define A4XX_RB_DEPTH_PITCH__SHIFT                              0
1403 static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val)
1404 {
1405         return ((val >> 5) << A4XX_RB_DEPTH_PITCH__SHIFT) & A4XX_RB_DEPTH_PITCH__MASK;
1406 }
1407
1408 #define REG_A4XX_RB_DEPTH_PITCH2                                0x00002105
1409 #define A4XX_RB_DEPTH_PITCH2__MASK                              0xffffffff
1410 #define A4XX_RB_DEPTH_PITCH2__SHIFT                             0
1411 static inline uint32_t A4XX_RB_DEPTH_PITCH2(uint32_t val)
1412 {
1413         return ((val >> 5) << A4XX_RB_DEPTH_PITCH2__SHIFT) & A4XX_RB_DEPTH_PITCH2__MASK;
1414 }
1415
1416 #define REG_A4XX_RB_STENCIL_CONTROL                             0x00002106
1417 #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE                  0x00000001
1418 #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF               0x00000002
1419 #define A4XX_RB_STENCIL_CONTROL_STENCIL_READ                    0x00000004
1420 #define A4XX_RB_STENCIL_CONTROL_FUNC__MASK                      0x00000700
1421 #define A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT                     8
1422 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
1423 {
1424         return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC__MASK;
1425 }
1426 #define A4XX_RB_STENCIL_CONTROL_FAIL__MASK                      0x00003800
1427 #define A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT                     11
1428 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
1429 {
1430         return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL__MASK;
1431 }
1432 #define A4XX_RB_STENCIL_CONTROL_ZPASS__MASK                     0x0001c000
1433 #define A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT                    14
1434 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
1435 {
1436         return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS__MASK;
1437 }
1438 #define A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK                     0x000e0000
1439 #define A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT                    17
1440 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
1441 {
1442         return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
1443 }
1444 #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK                   0x00700000
1445 #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT                  20
1446 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
1447 {
1448         return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
1449 }
1450 #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK                   0x03800000
1451 #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT                  23
1452 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
1453 {
1454         return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
1455 }
1456 #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK                  0x1c000000
1457 #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT                 26
1458 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
1459 {
1460         return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
1461 }
1462 #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK                  0xe0000000
1463 #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT                 29
1464 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
1465 {
1466         return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
1467 }
1468
1469 #define REG_A4XX_RB_STENCIL_CONTROL2                            0x00002107
1470 #define A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER                 0x00000001
1471
1472 #define REG_A4XX_RB_STENCIL_INFO                                0x00002108
1473 #define A4XX_RB_STENCIL_INFO_SEPARATE_STENCIL                   0x00000001
1474 #define A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK                 0xfffff000
1475 #define A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT                12
1476 static inline uint32_t A4XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val)
1477 {
1478         return ((val >> 12) << A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK;
1479 }
1480
1481 #define REG_A4XX_RB_STENCIL_PITCH                               0x00002109
1482 #define A4XX_RB_STENCIL_PITCH__MASK                             0xffffffff
1483 #define A4XX_RB_STENCIL_PITCH__SHIFT                            0
1484 static inline uint32_t A4XX_RB_STENCIL_PITCH(uint32_t val)
1485 {
1486         return ((val >> 5) << A4XX_RB_STENCIL_PITCH__SHIFT) & A4XX_RB_STENCIL_PITCH__MASK;
1487 }
1488
1489 #define REG_A4XX_RB_STENCILREFMASK                              0x0000210b
1490 #define A4XX_RB_STENCILREFMASK_STENCILREF__MASK                 0x000000ff
1491 #define A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT                0
1492 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
1493 {
1494         return ((val) << A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILREF__MASK;
1495 }
1496 #define A4XX_RB_STENCILREFMASK_STENCILMASK__MASK                0x0000ff00
1497 #define A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT               8
1498 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
1499 {
1500         return ((val) << A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILMASK__MASK;
1501 }
1502 #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK           0x00ff0000
1503 #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT          16
1504 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
1505 {
1506         return ((val) << A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
1507 }
1508
1509 #define REG_A4XX_RB_STENCILREFMASK_BF                           0x0000210c
1510 #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK              0x000000ff
1511 #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT             0
1512 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
1513 {
1514         return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK;
1515 }
1516 #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK             0x0000ff00
1517 #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT            8
1518 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
1519 {
1520         return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK;
1521 }
1522 #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK        0x00ff0000
1523 #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT       16
1524 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
1525 {
1526         return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK;
1527 }
1528
1529 #define REG_A4XX_RB_BIN_OFFSET                                  0x0000210d
1530 #define A4XX_RB_BIN_OFFSET_WINDOW_OFFSET_DISABLE                0x80000000
1531 #define A4XX_RB_BIN_OFFSET_X__MASK                              0x00007fff
1532 #define A4XX_RB_BIN_OFFSET_X__SHIFT                             0
1533 static inline uint32_t A4XX_RB_BIN_OFFSET_X(uint32_t val)
1534 {
1535         return ((val) << A4XX_RB_BIN_OFFSET_X__SHIFT) & A4XX_RB_BIN_OFFSET_X__MASK;
1536 }
1537 #define A4XX_RB_BIN_OFFSET_Y__MASK                              0x7fff0000
1538 #define A4XX_RB_BIN_OFFSET_Y__SHIFT                             16
1539 static inline uint32_t A4XX_RB_BIN_OFFSET_Y(uint32_t val)
1540 {
1541         return ((val) << A4XX_RB_BIN_OFFSET_Y__SHIFT) & A4XX_RB_BIN_OFFSET_Y__MASK;
1542 }
1543
1544 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP(uint32_t i0) { return 0x00002120 + 0x2*i0; }
1545
1546 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) { return 0x00002120 + 0x2*i0; }
1547
1548 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0) { return 0x00002121 + 0x2*i0; }
1549
1550 #define REG_A4XX_RBBM_HW_VERSION                                0x00000000
1551
1552 #define REG_A4XX_RBBM_HW_CONFIGURATION                          0x00000002
1553
1554 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP(uint32_t i0) { return 0x00000004 + 0x1*i0; }
1555
1556 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP_REG(uint32_t i0) { return 0x00000004 + 0x1*i0; }
1557
1558 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP(uint32_t i0) { return 0x00000008 + 0x1*i0; }
1559
1560 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP_REG(uint32_t i0) { return 0x00000008 + 0x1*i0; }
1561
1562 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP(uint32_t i0) { return 0x0000000c + 0x1*i0; }
1563
1564 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP_REG(uint32_t i0) { return 0x0000000c + 0x1*i0; }
1565
1566 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP(uint32_t i0) { return 0x00000010 + 0x1*i0; }
1567
1568 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0) { return 0x00000010 + 0x1*i0; }
1569
1570 #define REG_A4XX_RBBM_CLOCK_CTL_UCHE                            0x00000014
1571
1572 #define REG_A4XX_RBBM_CLOCK_CTL2_UCHE                           0x00000015
1573
1574 #define REG_A4XX_RBBM_CLOCK_CTL3_UCHE                           0x00000016
1575
1576 #define REG_A4XX_RBBM_CLOCK_CTL4_UCHE                           0x00000017
1577
1578 #define REG_A4XX_RBBM_CLOCK_HYST_UCHE                           0x00000018
1579
1580 #define REG_A4XX_RBBM_CLOCK_DELAY_UCHE                          0x00000019
1581
1582 #define REG_A4XX_RBBM_CLOCK_MODE_GPC                            0x0000001a
1583
1584 #define REG_A4XX_RBBM_CLOCK_DELAY_GPC                           0x0000001b
1585
1586 #define REG_A4XX_RBBM_CLOCK_HYST_GPC                            0x0000001c
1587
1588 #define REG_A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM                    0x0000001d
1589
1590 #define REG_A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM                   0x0000001e
1591
1592 #define REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM                  0x0000001f
1593
1594 #define REG_A4XX_RBBM_CLOCK_CTL                                 0x00000020
1595
1596 #define REG_A4XX_RBBM_SP_HYST_CNT                               0x00000021
1597
1598 #define REG_A4XX_RBBM_SW_RESET_CMD                              0x00000022
1599
1600 #define REG_A4XX_RBBM_AHB_CTL0                                  0x00000023
1601
1602 #define REG_A4XX_RBBM_AHB_CTL1                                  0x00000024
1603
1604 #define REG_A4XX_RBBM_AHB_CMD                                   0x00000025
1605
1606 #define REG_A4XX_RBBM_RB_SUB_BLOCK_SEL_CTL                      0x00000026
1607
1608 #define REG_A4XX_RBBM_RAM_ACC_63_32                             0x00000028
1609
1610 #define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL                      0x0000002b
1611
1612 #define REG_A4XX_RBBM_INTERFACE_HANG_INT_CTL                    0x0000002f
1613
1614 #define REG_A4XX_RBBM_INTERFACE_HANG_MASK_CTL4                  0x00000034
1615
1616 #define REG_A4XX_RBBM_INT_CLEAR_CMD                             0x00000036
1617
1618 #define REG_A4XX_RBBM_INT_0_MASK                                0x00000037
1619
1620 #define REG_A4XX_RBBM_RBBM_CTL                                  0x0000003e
1621
1622 #define REG_A4XX_RBBM_AHB_DEBUG_CTL                             0x0000003f
1623
1624 #define REG_A4XX_RBBM_VBIF_DEBUG_CTL                            0x00000041
1625
1626 #define REG_A4XX_RBBM_CLOCK_CTL2                                0x00000042
1627
1628 #define REG_A4XX_RBBM_BLOCK_SW_RESET_CMD                        0x00000045
1629
1630 #define REG_A4XX_RBBM_RESET_CYCLES                              0x00000047
1631
1632 #define REG_A4XX_RBBM_EXT_TRACE_BUS_CTL                         0x00000049
1633
1634 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_A                          0x0000004a
1635
1636 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_B                          0x0000004b
1637
1638 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_C                          0x0000004c
1639
1640 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_D                          0x0000004d
1641
1642 #define REG_A4XX_RBBM_POWER_CNTL_IP                             0x00000098
1643 #define A4XX_RBBM_POWER_CNTL_IP_SW_COLLAPSE                     0x00000001
1644 #define A4XX_RBBM_POWER_CNTL_IP_SP_TP_PWR_ON                    0x00100000
1645
1646 #define REG_A4XX_RBBM_PERFCTR_CP_0_LO                           0x0000009c
1647
1648 #define REG_A4XX_RBBM_PERFCTR_CP_0_HI                           0x0000009d
1649
1650 #define REG_A4XX_RBBM_PERFCTR_CP_1_LO                           0x0000009e
1651
1652 #define REG_A4XX_RBBM_PERFCTR_CP_1_HI                           0x0000009f
1653
1654 #define REG_A4XX_RBBM_PERFCTR_CP_2_LO                           0x000000a0
1655
1656 #define REG_A4XX_RBBM_PERFCTR_CP_2_HI                           0x000000a1
1657
1658 #define REG_A4XX_RBBM_PERFCTR_CP_3_LO                           0x000000a2
1659
1660 #define REG_A4XX_RBBM_PERFCTR_CP_3_HI                           0x000000a3
1661
1662 #define REG_A4XX_RBBM_PERFCTR_CP_4_LO                           0x000000a4
1663
1664 #define REG_A4XX_RBBM_PERFCTR_CP_4_HI                           0x000000a5
1665
1666 #define REG_A4XX_RBBM_PERFCTR_CP_5_LO                           0x000000a6
1667
1668 #define REG_A4XX_RBBM_PERFCTR_CP_5_HI                           0x000000a7
1669
1670 #define REG_A4XX_RBBM_PERFCTR_CP_6_LO                           0x000000a8
1671
1672 #define REG_A4XX_RBBM_PERFCTR_CP_6_HI                           0x000000a9
1673
1674 #define REG_A4XX_RBBM_PERFCTR_CP_7_LO                           0x000000aa
1675
1676 #define REG_A4XX_RBBM_PERFCTR_CP_7_HI                           0x000000ab
1677
1678 #define REG_A4XX_RBBM_PERFCTR_RBBM_0_LO                         0x000000ac
1679
1680 #define REG_A4XX_RBBM_PERFCTR_RBBM_0_HI                         0x000000ad
1681
1682 #define REG_A4XX_RBBM_PERFCTR_RBBM_1_LO                         0x000000ae
1683
1684 #define REG_A4XX_RBBM_PERFCTR_RBBM_1_HI                         0x000000af
1685
1686 #define REG_A4XX_RBBM_PERFCTR_RBBM_2_LO                         0x000000b0
1687
1688 #define REG_A4XX_RBBM_PERFCTR_RBBM_2_HI                         0x000000b1
1689
1690 #define REG_A4XX_RBBM_PERFCTR_RBBM_3_LO                         0x000000b2
1691
1692 #define REG_A4XX_RBBM_PERFCTR_RBBM_3_HI                         0x000000b3
1693
1694 #define REG_A4XX_RBBM_PERFCTR_PC_0_LO                           0x000000b4
1695
1696 #define REG_A4XX_RBBM_PERFCTR_PC_0_HI                           0x000000b5
1697
1698 #define REG_A4XX_RBBM_PERFCTR_PC_1_LO                           0x000000b6
1699
1700 #define REG_A4XX_RBBM_PERFCTR_PC_1_HI                           0x000000b7
1701
1702 #define REG_A4XX_RBBM_PERFCTR_PC_2_LO                           0x000000b8
1703
1704 #define REG_A4XX_RBBM_PERFCTR_PC_2_HI                           0x000000b9
1705
1706 #define REG_A4XX_RBBM_PERFCTR_PC_3_LO                           0x000000ba
1707
1708 #define REG_A4XX_RBBM_PERFCTR_PC_3_HI                           0x000000bb
1709
1710 #define REG_A4XX_RBBM_PERFCTR_PC_4_LO                           0x000000bc
1711
1712 #define REG_A4XX_RBBM_PERFCTR_PC_4_HI                           0x000000bd
1713
1714 #define REG_A4XX_RBBM_PERFCTR_PC_5_LO                           0x000000be
1715
1716 #define REG_A4XX_RBBM_PERFCTR_PC_5_HI                           0x000000bf
1717
1718 #define REG_A4XX_RBBM_PERFCTR_PC_6_LO                           0x000000c0
1719
1720 #define REG_A4XX_RBBM_PERFCTR_PC_6_HI                           0x000000c1
1721
1722 #define REG_A4XX_RBBM_PERFCTR_PC_7_LO                           0x000000c2
1723
1724 #define REG_A4XX_RBBM_PERFCTR_PC_7_HI                           0x000000c3
1725
1726 #define REG_A4XX_RBBM_PERFCTR_VFD_0_LO                          0x000000c4
1727
1728 #define REG_A4XX_RBBM_PERFCTR_VFD_0_HI                          0x000000c5
1729
1730 #define REG_A4XX_RBBM_PERFCTR_VFD_1_LO                          0x000000c6
1731
1732 #define REG_A4XX_RBBM_PERFCTR_VFD_1_HI                          0x000000c7
1733
1734 #define REG_A4XX_RBBM_PERFCTR_VFD_2_LO                          0x000000c8
1735
1736 #define REG_A4XX_RBBM_PERFCTR_VFD_2_HI                          0x000000c9
1737
1738 #define REG_A4XX_RBBM_PERFCTR_VFD_3_LO                          0x000000ca
1739
1740 #define REG_A4XX_RBBM_PERFCTR_VFD_3_HI                          0x000000cb
1741
1742 #define REG_A4XX_RBBM_PERFCTR_VFD_4_LO                          0x000000cc
1743
1744 #define REG_A4XX_RBBM_PERFCTR_VFD_4_HI                          0x000000cd
1745
1746 #define REG_A4XX_RBBM_PERFCTR_VFD_5_LO                          0x000000ce
1747
1748 #define REG_A4XX_RBBM_PERFCTR_VFD_5_HI                          0x000000cf
1749
1750 #define REG_A4XX_RBBM_PERFCTR_VFD_6_LO                          0x000000d0
1751
1752 #define REG_A4XX_RBBM_PERFCTR_VFD_6_HI                          0x000000d1
1753
1754 #define REG_A4XX_RBBM_PERFCTR_VFD_7_LO                          0x000000d2
1755
1756 #define REG_A4XX_RBBM_PERFCTR_VFD_7_HI                          0x000000d3
1757
1758 #define REG_A4XX_RBBM_PERFCTR_HLSQ_0_LO                         0x000000d4
1759
1760 #define REG_A4XX_RBBM_PERFCTR_HLSQ_0_HI                         0x000000d5
1761
1762 #define REG_A4XX_RBBM_PERFCTR_HLSQ_1_LO                         0x000000d6
1763
1764 #define REG_A4XX_RBBM_PERFCTR_HLSQ_1_HI                         0x000000d7
1765
1766 #define REG_A4XX_RBBM_PERFCTR_HLSQ_2_LO                         0x000000d8
1767
1768 #define REG_A4XX_RBBM_PERFCTR_HLSQ_2_HI                         0x000000d9
1769
1770 #define REG_A4XX_RBBM_PERFCTR_HLSQ_3_LO                         0x000000da
1771
1772 #define REG_A4XX_RBBM_PERFCTR_HLSQ_3_HI                         0x000000db
1773
1774 #define REG_A4XX_RBBM_PERFCTR_HLSQ_4_LO                         0x000000dc
1775
1776 #define REG_A4XX_RBBM_PERFCTR_HLSQ_4_HI                         0x000000dd
1777
1778 #define REG_A4XX_RBBM_PERFCTR_HLSQ_5_LO                         0x000000de
1779
1780 #define REG_A4XX_RBBM_PERFCTR_HLSQ_5_HI                         0x000000df
1781
1782 #define REG_A4XX_RBBM_PERFCTR_HLSQ_6_LO                         0x000000e0
1783
1784 #define REG_A4XX_RBBM_PERFCTR_HLSQ_6_HI                         0x000000e1
1785
1786 #define REG_A4XX_RBBM_PERFCTR_HLSQ_7_LO                         0x000000e2
1787
1788 #define REG_A4XX_RBBM_PERFCTR_HLSQ_7_HI                         0x000000e3
1789
1790 #define REG_A4XX_RBBM_PERFCTR_VPC_0_LO                          0x000000e4
1791
1792 #define REG_A4XX_RBBM_PERFCTR_VPC_0_HI                          0x000000e5
1793
1794 #define REG_A4XX_RBBM_PERFCTR_VPC_1_LO                          0x000000e6
1795
1796 #define REG_A4XX_RBBM_PERFCTR_VPC_1_HI                          0x000000e7
1797
1798 #define REG_A4XX_RBBM_PERFCTR_VPC_2_LO                          0x000000e8
1799
1800 #define REG_A4XX_RBBM_PERFCTR_VPC_2_HI                          0x000000e9
1801
1802 #define REG_A4XX_RBBM_PERFCTR_VPC_3_LO                          0x000000ea
1803
1804 #define REG_A4XX_RBBM_PERFCTR_VPC_3_HI                          0x000000eb
1805
1806 #define REG_A4XX_RBBM_PERFCTR_CCU_0_LO                          0x000000ec
1807
1808 #define REG_A4XX_RBBM_PERFCTR_CCU_0_HI                          0x000000ed
1809
1810 #define REG_A4XX_RBBM_PERFCTR_CCU_1_LO                          0x000000ee
1811
1812 #define REG_A4XX_RBBM_PERFCTR_CCU_1_HI                          0x000000ef
1813
1814 #define REG_A4XX_RBBM_PERFCTR_CCU_2_LO                          0x000000f0
1815
1816 #define REG_A4XX_RBBM_PERFCTR_CCU_2_HI                          0x000000f1
1817
1818 #define REG_A4XX_RBBM_PERFCTR_CCU_3_LO                          0x000000f2
1819
1820 #define REG_A4XX_RBBM_PERFCTR_CCU_3_HI                          0x000000f3
1821
1822 #define REG_A4XX_RBBM_PERFCTR_TSE_0_LO                          0x000000f4
1823
1824 #define REG_A4XX_RBBM_PERFCTR_TSE_0_HI                          0x000000f5
1825
1826 #define REG_A4XX_RBBM_PERFCTR_TSE_1_LO                          0x000000f6
1827
1828 #define REG_A4XX_RBBM_PERFCTR_TSE_1_HI                          0x000000f7
1829
1830 #define REG_A4XX_RBBM_PERFCTR_TSE_2_LO                          0x000000f8
1831
1832 #define REG_A4XX_RBBM_PERFCTR_TSE_2_HI                          0x000000f9
1833
1834 #define REG_A4XX_RBBM_PERFCTR_TSE_3_LO                          0x000000fa
1835
1836 #define REG_A4XX_RBBM_PERFCTR_TSE_3_HI                          0x000000fb
1837
1838 #define REG_A4XX_RBBM_PERFCTR_RAS_0_LO                          0x000000fc
1839
1840 #define REG_A4XX_RBBM_PERFCTR_RAS_0_HI                          0x000000fd
1841
1842 #define REG_A4XX_RBBM_PERFCTR_RAS_1_LO                          0x000000fe
1843
1844 #define REG_A4XX_RBBM_PERFCTR_RAS_1_HI                          0x000000ff
1845
1846 #define REG_A4XX_RBBM_PERFCTR_RAS_2_LO                          0x00000100
1847
1848 #define REG_A4XX_RBBM_PERFCTR_RAS_2_HI                          0x00000101
1849
1850 #define REG_A4XX_RBBM_PERFCTR_RAS_3_LO                          0x00000102
1851
1852 #define REG_A4XX_RBBM_PERFCTR_RAS_3_HI                          0x00000103
1853
1854 #define REG_A4XX_RBBM_PERFCTR_UCHE_0_LO                         0x00000104
1855
1856 #define REG_A4XX_RBBM_PERFCTR_UCHE_0_HI                         0x00000105
1857
1858 #define REG_A4XX_RBBM_PERFCTR_UCHE_1_LO                         0x00000106
1859
1860 #define REG_A4XX_RBBM_PERFCTR_UCHE_1_HI                         0x00000107
1861
1862 #define REG_A4XX_RBBM_PERFCTR_UCHE_2_LO                         0x00000108
1863
1864 #define REG_A4XX_RBBM_PERFCTR_UCHE_2_HI                         0x00000109
1865
1866 #define REG_A4XX_RBBM_PERFCTR_UCHE_3_LO                         0x0000010a
1867
1868 #define REG_A4XX_RBBM_PERFCTR_UCHE_3_HI                         0x0000010b
1869
1870 #define REG_A4XX_RBBM_PERFCTR_UCHE_4_LO                         0x0000010c
1871
1872 #define REG_A4XX_RBBM_PERFCTR_UCHE_4_HI                         0x0000010d
1873
1874 #define REG_A4XX_RBBM_PERFCTR_UCHE_5_LO                         0x0000010e
1875
1876 #define REG_A4XX_RBBM_PERFCTR_UCHE_5_HI                         0x0000010f
1877
1878 #define REG_A4XX_RBBM_PERFCTR_UCHE_6_LO                         0x00000110
1879
1880 #define REG_A4XX_RBBM_PERFCTR_UCHE_6_HI                         0x00000111
1881
1882 #define REG_A4XX_RBBM_PERFCTR_UCHE_7_LO                         0x00000112
1883
1884 #define REG_A4XX_RBBM_PERFCTR_UCHE_7_HI                         0x00000113
1885
1886 #define REG_A4XX_RBBM_PERFCTR_TP_0_LO                           0x00000114
1887
1888 #define REG_A4XX_RBBM_PERFCTR_TP_0_HI                           0x00000115
1889
1890 #define REG_A4XX_RBBM_PERFCTR_TP_0_LO                           0x00000114
1891
1892 #define REG_A4XX_RBBM_PERFCTR_TP_0_HI                           0x00000115
1893
1894 #define REG_A4XX_RBBM_PERFCTR_TP_1_LO                           0x00000116
1895
1896 #define REG_A4XX_RBBM_PERFCTR_TP_1_HI                           0x00000117
1897
1898 #define REG_A4XX_RBBM_PERFCTR_TP_2_LO                           0x00000118
1899
1900 #define REG_A4XX_RBBM_PERFCTR_TP_2_HI                           0x00000119
1901
1902 #define REG_A4XX_RBBM_PERFCTR_TP_3_LO                           0x0000011a
1903
1904 #define REG_A4XX_RBBM_PERFCTR_TP_3_HI                           0x0000011b
1905
1906 #define REG_A4XX_RBBM_PERFCTR_TP_4_LO                           0x0000011c
1907
1908 #define REG_A4XX_RBBM_PERFCTR_TP_4_HI                           0x0000011d
1909
1910 #define REG_A4XX_RBBM_PERFCTR_TP_5_LO                           0x0000011e
1911
1912 #define REG_A4XX_RBBM_PERFCTR_TP_5_HI                           0x0000011f
1913
1914 #define REG_A4XX_RBBM_PERFCTR_TP_6_LO                           0x00000120
1915
1916 #define REG_A4XX_RBBM_PERFCTR_TP_6_HI                           0x00000121
1917
1918 #define REG_A4XX_RBBM_PERFCTR_TP_7_LO                           0x00000122
1919
1920 #define REG_A4XX_RBBM_PERFCTR_TP_7_HI                           0x00000123
1921
1922 #define REG_A4XX_RBBM_PERFCTR_SP_0_LO                           0x00000124
1923
1924 #define REG_A4XX_RBBM_PERFCTR_SP_0_HI                           0x00000125
1925
1926 #define REG_A4XX_RBBM_PERFCTR_SP_1_LO                           0x00000126
1927
1928 #define REG_A4XX_RBBM_PERFCTR_SP_1_HI                           0x00000127
1929
1930 #define REG_A4XX_RBBM_PERFCTR_SP_2_LO                           0x00000128
1931
1932 #define REG_A4XX_RBBM_PERFCTR_SP_2_HI                           0x00000129
1933
1934 #define REG_A4XX_RBBM_PERFCTR_SP_3_LO                           0x0000012a
1935
1936 #define REG_A4XX_RBBM_PERFCTR_SP_3_HI                           0x0000012b
1937
1938 #define REG_A4XX_RBBM_PERFCTR_SP_4_LO                           0x0000012c
1939
1940 #define REG_A4XX_RBBM_PERFCTR_SP_4_HI                           0x0000012d
1941
1942 #define REG_A4XX_RBBM_PERFCTR_SP_5_LO                           0x0000012e
1943
1944 #define REG_A4XX_RBBM_PERFCTR_SP_5_HI                           0x0000012f
1945
1946 #define REG_A4XX_RBBM_PERFCTR_SP_6_LO                           0x00000130
1947
1948 #define REG_A4XX_RBBM_PERFCTR_SP_6_HI                           0x00000131
1949
1950 #define REG_A4XX_RBBM_PERFCTR_SP_7_LO                           0x00000132
1951
1952 #define REG_A4XX_RBBM_PERFCTR_SP_7_HI                           0x00000133
1953
1954 #define REG_A4XX_RBBM_PERFCTR_SP_8_LO                           0x00000134
1955
1956 #define REG_A4XX_RBBM_PERFCTR_SP_8_HI                           0x00000135
1957
1958 #define REG_A4XX_RBBM_PERFCTR_SP_9_LO                           0x00000136
1959
1960 #define REG_A4XX_RBBM_PERFCTR_SP_9_HI                           0x00000137
1961
1962 #define REG_A4XX_RBBM_PERFCTR_SP_10_LO                          0x00000138
1963
1964 #define REG_A4XX_RBBM_PERFCTR_SP_10_HI                          0x00000139
1965
1966 #define REG_A4XX_RBBM_PERFCTR_SP_11_LO                          0x0000013a
1967
1968 #define REG_A4XX_RBBM_PERFCTR_SP_11_HI                          0x0000013b
1969
1970 #define REG_A4XX_RBBM_PERFCTR_RB_0_LO                           0x0000013c
1971
1972 #define REG_A4XX_RBBM_PERFCTR_RB_0_HI                           0x0000013d
1973
1974 #define REG_A4XX_RBBM_PERFCTR_RB_1_LO                           0x0000013e
1975
1976 #define REG_A4XX_RBBM_PERFCTR_RB_1_HI                           0x0000013f
1977
1978 #define REG_A4XX_RBBM_PERFCTR_RB_2_LO                           0x00000140
1979
1980 #define REG_A4XX_RBBM_PERFCTR_RB_2_HI                           0x00000141
1981
1982 #define REG_A4XX_RBBM_PERFCTR_RB_3_LO                           0x00000142
1983
1984 #define REG_A4XX_RBBM_PERFCTR_RB_3_HI                           0x00000143
1985
1986 #define REG_A4XX_RBBM_PERFCTR_RB_4_LO                           0x00000144
1987
1988 #define REG_A4XX_RBBM_PERFCTR_RB_4_HI                           0x00000145
1989
1990 #define REG_A4XX_RBBM_PERFCTR_RB_5_LO                           0x00000146
1991
1992 #define REG_A4XX_RBBM_PERFCTR_RB_5_HI                           0x00000147
1993
1994 #define REG_A4XX_RBBM_PERFCTR_RB_6_LO                           0x00000148
1995
1996 #define REG_A4XX_RBBM_PERFCTR_RB_6_HI                           0x00000149
1997
1998 #define REG_A4XX_RBBM_PERFCTR_RB_7_LO                           0x0000014a
1999
2000 #define REG_A4XX_RBBM_PERFCTR_RB_7_HI                           0x0000014b
2001
2002 #define REG_A4XX_RBBM_PERFCTR_VSC_0_LO                          0x0000014c
2003
2004 #define REG_A4XX_RBBM_PERFCTR_VSC_0_HI                          0x0000014d
2005
2006 #define REG_A4XX_RBBM_PERFCTR_VSC_1_LO                          0x0000014e
2007
2008 #define REG_A4XX_RBBM_PERFCTR_VSC_1_HI                          0x0000014f
2009
2010 #define REG_A4XX_RBBM_PERFCTR_PWR_0_LO                          0x00000166
2011
2012 #define REG_A4XX_RBBM_PERFCTR_PWR_0_HI                          0x00000167
2013
2014 #define REG_A4XX_RBBM_PERFCTR_PWR_1_LO                          0x00000168
2015
2016 #define REG_A4XX_RBBM_PERFCTR_PWR_1_HI                          0x00000169
2017
2018 #define REG_A4XX_RBBM_ALWAYSON_COUNTER_LO                       0x0000016e
2019
2020 #define REG_A4XX_RBBM_ALWAYSON_COUNTER_HI                       0x0000016f
2021
2022 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP(uint32_t i0) { return 0x00000068 + 0x1*i0; }
2023
2024 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0) { return 0x00000068 + 0x1*i0; }
2025
2026 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP(uint32_t i0) { return 0x0000006c + 0x1*i0; }
2027
2028 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP_REG(uint32_t i0) { return 0x0000006c + 0x1*i0; }
2029
2030 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP(uint32_t i0) { return 0x00000070 + 0x1*i0; }
2031
2032 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP_REG(uint32_t i0) { return 0x00000070 + 0x1*i0; }
2033
2034 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP(uint32_t i0) { return 0x00000074 + 0x1*i0; }
2035
2036 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP_REG(uint32_t i0) { return 0x00000074 + 0x1*i0; }
2037
2038 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB(uint32_t i0) { return 0x00000078 + 0x1*i0; }
2039
2040 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB_REG(uint32_t i0) { return 0x00000078 + 0x1*i0; }
2041
2042 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB(uint32_t i0) { return 0x0000007c + 0x1*i0; }
2043
2044 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB_REG(uint32_t i0) { return 0x0000007c + 0x1*i0; }
2045
2046 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(uint32_t i0) { return 0x00000082 + 0x1*i0; }
2047
2048 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG(uint32_t i0) { return 0x00000082 + 0x1*i0; }
2049
2050 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(uint32_t i0) { return 0x00000086 + 0x1*i0; }
2051
2052 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG(uint32_t i0) { return 0x00000086 + 0x1*i0; }
2053
2054 #define REG_A4XX_RBBM_CLOCK_HYST_COM_DCOM                       0x00000080
2055
2056 #define REG_A4XX_RBBM_CLOCK_CTL_COM_DCOM                        0x00000081
2057
2058 #define REG_A4XX_RBBM_CLOCK_CTL_HLSQ                            0x0000008a
2059
2060 #define REG_A4XX_RBBM_CLOCK_HYST_HLSQ                           0x0000008b
2061
2062 #define REG_A4XX_RBBM_CLOCK_DELAY_HLSQ                          0x0000008c
2063
2064 #define REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM                      0x0000008d
2065
2066 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(uint32_t i0) { return 0x0000008e + 0x1*i0; }
2067
2068 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) { return 0x0000008e + 0x1*i0; }
2069
2070 #define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0                   0x00000099
2071
2072 #define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1                   0x0000009a
2073
2074 #define REG_A4XX_RBBM_PERFCTR_PWR_1_LO                          0x00000168
2075
2076 #define REG_A4XX_RBBM_PERFCTR_CTL                               0x00000170
2077
2078 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD0                         0x00000171
2079
2080 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD1                         0x00000172
2081
2082 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD2                         0x00000173
2083
2084 #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_LO                     0x00000174
2085
2086 #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_HI                     0x00000175
2087
2088 #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_0                        0x00000176
2089
2090 #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_1                        0x00000177
2091
2092 #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_2                        0x00000178
2093
2094 #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_3                        0x00000179
2095
2096 #define REG_A4XX_RBBM_GPU_BUSY_MASKED                           0x0000017a
2097
2098 #define REG_A4XX_RBBM_INT_0_STATUS                              0x0000017d
2099
2100 #define REG_A4XX_RBBM_CLOCK_STATUS                              0x00000182
2101
2102 #define REG_A4XX_RBBM_AHB_STATUS                                0x00000189
2103
2104 #define REG_A4XX_RBBM_AHB_ME_SPLIT_STATUS                       0x0000018c
2105
2106 #define REG_A4XX_RBBM_AHB_PFP_SPLIT_STATUS                      0x0000018d
2107
2108 #define REG_A4XX_RBBM_AHB_ERROR_STATUS                          0x0000018f
2109
2110 #define REG_A4XX_RBBM_STATUS                                    0x00000191
2111 #define A4XX_RBBM_STATUS_HI_BUSY                                0x00000001
2112 #define A4XX_RBBM_STATUS_CP_ME_BUSY                             0x00000002
2113 #define A4XX_RBBM_STATUS_CP_PFP_BUSY                            0x00000004
2114 #define A4XX_RBBM_STATUS_CP_NRT_BUSY                            0x00004000
2115 #define A4XX_RBBM_STATUS_VBIF_BUSY                              0x00008000
2116 #define A4XX_RBBM_STATUS_TSE_BUSY                               0x00010000
2117 #define A4XX_RBBM_STATUS_RAS_BUSY                               0x00020000
2118 #define A4XX_RBBM_STATUS_RB_BUSY                                0x00040000
2119 #define A4XX_RBBM_STATUS_PC_DCALL_BUSY                          0x00080000
2120 #define A4XX_RBBM_STATUS_PC_VSD_BUSY                            0x00100000
2121 #define A4XX_RBBM_STATUS_VFD_BUSY                               0x00200000
2122 #define A4XX_RBBM_STATUS_VPC_BUSY                               0x00400000
2123 #define A4XX_RBBM_STATUS_UCHE_BUSY                              0x00800000
2124 #define A4XX_RBBM_STATUS_SP_BUSY                                0x01000000
2125 #define A4XX_RBBM_STATUS_TPL1_BUSY                              0x02000000
2126 #define A4XX_RBBM_STATUS_MARB_BUSY                              0x04000000
2127 #define A4XX_RBBM_STATUS_VSC_BUSY                               0x08000000
2128 #define A4XX_RBBM_STATUS_ARB_BUSY                               0x10000000
2129 #define A4XX_RBBM_STATUS_HLSQ_BUSY                              0x20000000
2130 #define A4XX_RBBM_STATUS_GPU_BUSY_NOHC                          0x40000000
2131 #define A4XX_RBBM_STATUS_GPU_BUSY                               0x80000000
2132
2133 #define REG_A4XX_RBBM_INTERFACE_RRDY_STATUS5                    0x0000019f
2134
2135 #define REG_A4XX_RBBM_POWER_STATUS                              0x000001b0
2136 #define A4XX_RBBM_POWER_STATUS_SP_TP_PWR_ON                     0x00100000
2137
2138 #define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2                     0x000001b8
2139
2140 #define REG_A4XX_CP_SCRATCH_UMASK                               0x00000228
2141
2142 #define REG_A4XX_CP_SCRATCH_ADDR                                0x00000229
2143
2144 #define REG_A4XX_CP_RB_BASE                                     0x00000200
2145
2146 #define REG_A4XX_CP_RB_CNTL                                     0x00000201
2147
2148 #define REG_A4XX_CP_RB_WPTR                                     0x00000205
2149
2150 #define REG_A4XX_CP_RB_RPTR_ADDR                                0x00000203
2151
2152 #define REG_A4XX_CP_RB_RPTR                                     0x00000204
2153
2154 #define REG_A4XX_CP_IB1_BASE                                    0x00000206
2155
2156 #define REG_A4XX_CP_IB1_BUFSZ                                   0x00000207
2157
2158 #define REG_A4XX_CP_IB2_BASE                                    0x00000208
2159
2160 #define REG_A4XX_CP_IB2_BUFSZ                                   0x00000209
2161
2162 #define REG_A4XX_CP_ME_NRT_ADDR                                 0x0000020c
2163
2164 #define REG_A4XX_CP_ME_NRT_DATA                                 0x0000020d
2165
2166 #define REG_A4XX_CP_ME_RB_DONE_DATA                             0x00000217
2167
2168 #define REG_A4XX_CP_QUEUE_THRESH2                               0x00000219
2169
2170 #define REG_A4XX_CP_MERCIU_SIZE                                 0x0000021b
2171
2172 #define REG_A4XX_CP_ROQ_ADDR                                    0x0000021c
2173
2174 #define REG_A4XX_CP_ROQ_DATA                                    0x0000021d
2175
2176 #define REG_A4XX_CP_MEQ_ADDR                                    0x0000021e
2177
2178 #define REG_A4XX_CP_MEQ_DATA                                    0x0000021f
2179
2180 #define REG_A4XX_CP_MERCIU_ADDR                                 0x00000220
2181
2182 #define REG_A4XX_CP_MERCIU_DATA                                 0x00000221
2183
2184 #define REG_A4XX_CP_MERCIU_DATA2                                0x00000222
2185
2186 #define REG_A4XX_CP_PFP_UCODE_ADDR                              0x00000223
2187
2188 #define REG_A4XX_CP_PFP_UCODE_DATA                              0x00000224
2189
2190 #define REG_A4XX_CP_ME_RAM_WADDR                                0x00000225
2191
2192 #define REG_A4XX_CP_ME_RAM_RADDR                                0x00000226
2193
2194 #define REG_A4XX_CP_ME_RAM_DATA                                 0x00000227
2195
2196 #define REG_A4XX_CP_PREEMPT                                     0x0000022a
2197
2198 #define REG_A4XX_CP_CNTL                                        0x0000022c
2199
2200 #define REG_A4XX_CP_ME_CNTL                                     0x0000022d
2201
2202 #define REG_A4XX_CP_DEBUG                                       0x0000022e
2203
2204 #define REG_A4XX_CP_DEBUG_ECO_CONTROL                           0x00000231
2205
2206 #define REG_A4XX_CP_DRAW_STATE_ADDR                             0x00000232
2207
2208 #define REG_A4XX_CP_PROTECT_REG_0                               0x00000240
2209
2210 static inline uint32_t REG_A4XX_CP_PROTECT(uint32_t i0) { return 0x00000240 + 0x1*i0; }
2211
2212 static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240 + 0x1*i0; }
2213
2214 #define REG_A4XX_CP_PROTECT_CTRL                                0x00000250
2215
2216 #define REG_A4XX_CP_ST_BASE                                     0x000004c0
2217
2218 #define REG_A4XX_CP_STQ_AVAIL                                   0x000004ce
2219
2220 #define REG_A4XX_CP_MERCIU_STAT                                 0x000004d0
2221
2222 #define REG_A4XX_CP_WFI_PEND_CTR                                0x000004d2
2223
2224 #define REG_A4XX_CP_HW_FAULT                                    0x000004d8
2225
2226 #define REG_A4XX_CP_PROTECT_STATUS                              0x000004da
2227
2228 #define REG_A4XX_CP_EVENTS_IN_FLIGHT                            0x000004dd
2229
2230 #define REG_A4XX_CP_PERFCTR_CP_SEL_0                            0x00000500
2231
2232 #define REG_A4XX_CP_PERFCTR_CP_SEL_1                            0x00000501
2233
2234 #define REG_A4XX_CP_PERFCTR_CP_SEL_2                            0x00000502
2235
2236 #define REG_A4XX_CP_PERFCTR_CP_SEL_3                            0x00000503
2237
2238 #define REG_A4XX_CP_PERFCTR_CP_SEL_4                            0x00000504
2239
2240 #define REG_A4XX_CP_PERFCTR_CP_SEL_5                            0x00000505
2241
2242 #define REG_A4XX_CP_PERFCTR_CP_SEL_6                            0x00000506
2243
2244 #define REG_A4XX_CP_PERFCTR_CP_SEL_7                            0x00000507
2245
2246 #define REG_A4XX_CP_PERFCOMBINER_SELECT                         0x0000050b
2247
2248 static inline uint32_t REG_A4XX_CP_SCRATCH(uint32_t i0) { return 0x00000578 + 0x1*i0; }
2249
2250 static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578 + 0x1*i0; }
2251
2252 #define REG_A4XX_SP_VS_STATUS                                   0x00000ec0
2253
2254 #define REG_A4XX_SP_MODE_CONTROL                                0x00000ec3
2255
2256 #define REG_A4XX_SP_PERFCTR_SP_SEL_0                            0x00000ec4
2257
2258 #define REG_A4XX_SP_PERFCTR_SP_SEL_1                            0x00000ec5
2259
2260 #define REG_A4XX_SP_PERFCTR_SP_SEL_2                            0x00000ec6
2261
2262 #define REG_A4XX_SP_PERFCTR_SP_SEL_3                            0x00000ec7
2263
2264 #define REG_A4XX_SP_PERFCTR_SP_SEL_4                            0x00000ec8
2265
2266 #define REG_A4XX_SP_PERFCTR_SP_SEL_5                            0x00000ec9
2267
2268 #define REG_A4XX_SP_PERFCTR_SP_SEL_6                            0x00000eca
2269
2270 #define REG_A4XX_SP_PERFCTR_SP_SEL_7                            0x00000ecb
2271
2272 #define REG_A4XX_SP_PERFCTR_SP_SEL_8                            0x00000ecc
2273
2274 #define REG_A4XX_SP_PERFCTR_SP_SEL_9                            0x00000ecd
2275
2276 #define REG_A4XX_SP_PERFCTR_SP_SEL_10                           0x00000ece
2277
2278 #define REG_A4XX_SP_PERFCTR_SP_SEL_11                           0x00000ecf
2279
2280 #define REG_A4XX_SP_SP_CTRL_REG                                 0x000022c0
2281 #define A4XX_SP_SP_CTRL_REG_BINNING_PASS                        0x00080000
2282
2283 #define REG_A4XX_SP_INSTR_CACHE_CTRL                            0x000022c1
2284 #define A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER                      0x00000080
2285 #define A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER                      0x00000100
2286 #define A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER                   0x00000400
2287
2288 #define REG_A4XX_SP_VS_CTRL_REG0                                0x000022c4
2289 #define A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK                   0x00000001
2290 #define A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT                  0
2291 static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
2292 {
2293         return ((val) << A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK;
2294 }
2295 #define A4XX_SP_VS_CTRL_REG0_VARYING                            0x00000002
2296 #define A4XX_SP_VS_CTRL_REG0_CACHEINVALID                       0x00000004
2297 #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK             0x000003f0
2298 #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT            4
2299 static inline uint32_t A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
2300 {
2301         return ((val) << A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
2302 }
2303 #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK             0x0003fc00
2304 #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT            10
2305 static inline uint32_t A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
2306 {
2307         return ((val) << A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
2308 }
2309 #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK              0x000c0000
2310 #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT             18
2311 static inline uint32_t A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
2312 {
2313         return ((val) << A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK;
2314 }
2315 #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK                   0x00100000
2316 #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT                  20
2317 static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
2318 {
2319         return ((val) << A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
2320 }
2321 #define A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE                    0x00200000
2322 #define A4XX_SP_VS_CTRL_REG0_PIXLODENABLE                       0x00400000
2323
2324 #define REG_A4XX_SP_VS_CTRL_REG1                                0x000022c5
2325 #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK                  0x000000ff
2326 #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT                 0
2327 static inline uint32_t A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val)
2328 {
2329         return ((val) << A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK;
2330 }
2331 #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK           0x7f000000
2332 #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT          24
2333 static inline uint32_t A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val)
2334 {
2335         return ((val) << A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK;
2336 }
2337
2338 #define REG_A4XX_SP_VS_PARAM_REG                                0x000022c6
2339 #define A4XX_SP_VS_PARAM_REG_POSREGID__MASK                     0x000000ff
2340 #define A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT                    0
2341 static inline uint32_t A4XX_SP_VS_PARAM_REG_POSREGID(uint32_t val)
2342 {
2343         return ((val) << A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_POSREGID__MASK;
2344 }
2345 #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK                   0x0000ff00
2346 #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT                  8
2347 static inline uint32_t A4XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val)
2348 {
2349         return ((val) << A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK;
2350 }
2351 #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK                0xfff00000
2352 #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT               20
2353 static inline uint32_t A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val)
2354 {
2355         return ((val) << A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK;
2356 }
2357
2358 static inline uint32_t REG_A4XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
2359
2360 static inline uint32_t REG_A4XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
2361 #define A4XX_SP_VS_OUT_REG_A_REGID__MASK                        0x000001ff
2362 #define A4XX_SP_VS_OUT_REG_A_REGID__SHIFT                       0
2363 static inline uint32_t A4XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
2364 {
2365         return ((val) << A4XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_A_REGID__MASK;
2366 }
2367 #define A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK                     0x00001e00
2368 #define A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT                    9
2369 static inline uint32_t A4XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
2370 {
2371         return ((val) << A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
2372 }
2373 #define A4XX_SP_VS_OUT_REG_B_REGID__MASK                        0x01ff0000
2374 #define A4XX_SP_VS_OUT_REG_B_REGID__SHIFT                       16
2375 static inline uint32_t A4XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
2376 {
2377         return ((val) << A4XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_B_REGID__MASK;
2378 }
2379 #define A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK                     0x1e000000
2380 #define A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT                    25
2381 static inline uint32_t A4XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
2382 {
2383         return ((val) << A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
2384 }
2385
2386 static inline uint32_t REG_A4XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d8 + 0x1*i0; }
2387
2388 static inline uint32_t REG_A4XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d8 + 0x1*i0; }
2389 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK                    0x000000ff
2390 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT                   0
2391 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
2392 {
2393         return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
2394 }
2395 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK                    0x0000ff00
2396 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT                   8
2397 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
2398 {
2399         return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
2400 }
2401 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK                    0x00ff0000
2402 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT                   16
2403 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
2404 {
2405         return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
2406 }
2407 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK                    0xff000000
2408 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT                   24
2409 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
2410 {
2411         return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
2412 }
2413
2414 #define REG_A4XX_SP_VS_OBJ_OFFSET_REG                           0x000022e0
2415 #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK       0x01ff0000
2416 #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT      16
2417 static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
2418 {
2419         return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
2420 }
2421 #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK         0xfe000000
2422 #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT        25
2423 static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
2424 {
2425         return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
2426 }
2427
2428 #define REG_A4XX_SP_VS_OBJ_START                                0x000022e1
2429
2430 #define REG_A4XX_SP_VS_PVT_MEM_PARAM                            0x000022e2
2431
2432 #define REG_A4XX_SP_VS_PVT_MEM_ADDR                             0x000022e3
2433
2434 #define REG_A4XX_SP_VS_LENGTH_REG                               0x000022e5
2435
2436 #define REG_A4XX_SP_FS_CTRL_REG0                                0x000022e8
2437 #define A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK                   0x00000001
2438 #define A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT                  0
2439 static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
2440 {
2441         return ((val) << A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK;
2442 }
2443 #define A4XX_SP_FS_CTRL_REG0_VARYING                            0x00000002
2444 #define A4XX_SP_FS_CTRL_REG0_CACHEINVALID                       0x00000004
2445 #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK             0x000003f0
2446 #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT            4
2447 static inline uint32_t A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
2448 {
2449         return ((val) << A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
2450 }
2451 #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK             0x0003fc00
2452 #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT            10
2453 static inline uint32_t A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
2454 {
2455         return ((val) << A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
2456 }
2457 #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK              0x000c0000
2458 #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT             18
2459 static inline uint32_t A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
2460 {
2461         return ((val) << A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK;
2462 }
2463 #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK                   0x00100000
2464 #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT                  20
2465 static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
2466 {
2467         return ((val) << A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
2468 }
2469 #define A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE                    0x00200000
2470 #define A4XX_SP_FS_CTRL_REG0_PIXLODENABLE                       0x00400000
2471
2472 #define REG_A4XX_SP_FS_CTRL_REG1                                0x000022e9
2473 #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK                  0x000000ff
2474 #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT                 0
2475 static inline uint32_t A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val)
2476 {
2477         return ((val) << A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK;
2478 }
2479 #define A4XX_SP_FS_CTRL_REG1_FACENESS                           0x00080000
2480 #define A4XX_SP_FS_CTRL_REG1_VARYING                            0x00100000
2481 #define A4XX_SP_FS_CTRL_REG1_FRAGCOORD                          0x00200000
2482
2483 #define REG_A4XX_SP_FS_OBJ_OFFSET_REG                           0x000022ea
2484 #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK       0x01ff0000
2485 #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT      16
2486 static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
2487 {
2488         return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
2489 }
2490 #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK         0xfe000000
2491 #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT        25
2492 static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
2493 {
2494         return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
2495 }
2496
2497 #define REG_A4XX_SP_FS_OBJ_START                                0x000022eb
2498
2499 #define REG_A4XX_SP_FS_PVT_MEM_PARAM                            0x000022ec
2500
2501 #define REG_A4XX_SP_FS_PVT_MEM_ADDR                             0x000022ed
2502
2503 #define REG_A4XX_SP_FS_LENGTH_REG                               0x000022ef
2504
2505 #define REG_A4XX_SP_FS_OUTPUT_REG                               0x000022f0
2506 #define A4XX_SP_FS_OUTPUT_REG_MRT__MASK                         0x0000000f
2507 #define A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT                        0
2508 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_MRT(uint32_t val)
2509 {
2510         return ((val) << A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_SP_FS_OUTPUT_REG_MRT__MASK;
2511 }
2512 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE                      0x00000080
2513 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK                 0x0000ff00
2514 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT                8
2515 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val)
2516 {
2517         return ((val) << A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK;
2518 }
2519 #define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK            0xff000000
2520 #define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT           24
2521 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID(uint32_t val)
2522 {
2523         return ((val) << A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK;
2524 }
2525
2526 static inline uint32_t REG_A4XX_SP_FS_MRT(uint32_t i0) { return 0x000022f1 + 0x1*i0; }
2527
2528 static inline uint32_t REG_A4XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f1 + 0x1*i0; }
2529 #define A4XX_SP_FS_MRT_REG_REGID__MASK                          0x000000ff
2530 #define A4XX_SP_FS_MRT_REG_REGID__SHIFT                         0
2531 static inline uint32_t A4XX_SP_FS_MRT_REG_REGID(uint32_t val)
2532 {
2533         return ((val) << A4XX_SP_FS_MRT_REG_REGID__SHIFT) & A4XX_SP_FS_MRT_REG_REGID__MASK;
2534 }
2535 #define A4XX_SP_FS_MRT_REG_HALF_PRECISION                       0x00000100
2536 #define A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK                      0x0003f000
2537 #define A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT                     12
2538 static inline uint32_t A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val)
2539 {
2540         return ((val) << A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT) & A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK;
2541 }
2542 #define A4XX_SP_FS_MRT_REG_COLOR_SRGB                           0x00040000
2543
2544 #define REG_A4XX_SP_CS_CTRL_REG0                                0x00002300
2545
2546 #define REG_A4XX_SP_CS_OBJ_OFFSET_REG                           0x00002301
2547
2548 #define REG_A4XX_SP_CS_OBJ_START                                0x00002302
2549
2550 #define REG_A4XX_SP_CS_PVT_MEM_PARAM                            0x00002303
2551
2552 #define REG_A4XX_SP_CS_PVT_MEM_ADDR                             0x00002304
2553
2554 #define REG_A4XX_SP_CS_PVT_MEM_SIZE                             0x00002305
2555
2556 #define REG_A4XX_SP_CS_LENGTH_REG                               0x00002306
2557
2558 #define REG_A4XX_SP_HS_OBJ_OFFSET_REG                           0x0000230d
2559 #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK       0x01ff0000
2560 #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT      16
2561 static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
2562 {
2563         return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
2564 }
2565 #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK         0xfe000000
2566 #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT        25
2567 static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
2568 {
2569         return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
2570 }
2571
2572 #define REG_A4XX_SP_HS_OBJ_START                                0x0000230e
2573
2574 #define REG_A4XX_SP_HS_PVT_MEM_PARAM                            0x0000230f
2575
2576 #define REG_A4XX_SP_HS_PVT_MEM_ADDR                             0x00002310
2577
2578 #define REG_A4XX_SP_HS_LENGTH_REG                               0x00002312
2579
2580 #define REG_A4XX_SP_DS_PARAM_REG                                0x0000231a
2581 #define A4XX_SP_DS_PARAM_REG_POSREGID__MASK                     0x000000ff
2582 #define A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT                    0
2583 static inline uint32_t A4XX_SP_DS_PARAM_REG_POSREGID(uint32_t val)
2584 {
2585         return ((val) << A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_DS_PARAM_REG_POSREGID__MASK;
2586 }
2587 #define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK                0xfff00000
2588 #define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT               20
2589 static inline uint32_t A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR(uint32_t val)
2590 {
2591         return ((val) << A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK;
2592 }
2593
2594 static inline uint32_t REG_A4XX_SP_DS_OUT(uint32_t i0) { return 0x0000231b + 0x1*i0; }
2595
2596 static inline uint32_t REG_A4XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000231b + 0x1*i0; }
2597 #define A4XX_SP_DS_OUT_REG_A_REGID__MASK                        0x000001ff
2598 #define A4XX_SP_DS_OUT_REG_A_REGID__SHIFT                       0
2599 static inline uint32_t A4XX_SP_DS_OUT_REG_A_REGID(uint32_t val)
2600 {
2601         return ((val) << A4XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_A_REGID__MASK;
2602 }
2603 #define A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK                     0x00001e00
2604 #define A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT                    9
2605 static inline uint32_t A4XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val)
2606 {
2607         return ((val) << A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK;
2608 }
2609 #define A4XX_SP_DS_OUT_REG_B_REGID__MASK                        0x01ff0000
2610 #define A4XX_SP_DS_OUT_REG_B_REGID__SHIFT                       16
2611 static inline uint32_t A4XX_SP_DS_OUT_REG_B_REGID(uint32_t val)
2612 {
2613         return ((val) << A4XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_B_REGID__MASK;
2614 }
2615 #define A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK                     0x1e000000
2616 #define A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT                    25
2617 static inline uint32_t A4XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val)
2618 {
2619         return ((val) << A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK;
2620 }
2621
2622 static inline uint32_t REG_A4XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000232c + 0x1*i0; }
2623
2624 static inline uint32_t REG_A4XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000232c + 0x1*i0; }
2625 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK                    0x000000ff
2626 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT                   0
2627 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val)
2628 {
2629         return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK;
2630 }
2631 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK                    0x0000ff00
2632 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT                   8
2633 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val)
2634 {
2635         return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK;
2636 }
2637 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK                    0x00ff0000
2638 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT                   16
2639 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val)
2640 {
2641         return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK;
2642 }
2643 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK                    0xff000000
2644 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT                   24
2645 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val)
2646 {
2647         return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK;
2648 }
2649
2650 #define REG_A4XX_SP_DS_OBJ_OFFSET_REG                           0x00002334
2651 #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK       0x01ff0000
2652 #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT      16
2653 static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
2654 {
2655         return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
2656 }
2657 #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK         0xfe000000
2658 #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT        25
2659 static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
2660 {
2661         return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
2662 }
2663
2664 #define REG_A4XX_SP_DS_OBJ_START                                0x00002335
2665
2666 #define REG_A4XX_SP_DS_PVT_MEM_PARAM                            0x00002336
2667
2668 #define REG_A4XX_SP_DS_PVT_MEM_ADDR                             0x00002337
2669
2670 #define REG_A4XX_SP_DS_LENGTH_REG                               0x00002339
2671
2672 #define REG_A4XX_SP_GS_PARAM_REG                                0x00002341
2673 #define A4XX_SP_GS_PARAM_REG_POSREGID__MASK                     0x000000ff
2674 #define A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT                    0
2675 static inline uint32_t A4XX_SP_GS_PARAM_REG_POSREGID(uint32_t val)
2676 {
2677         return ((val) << A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_POSREGID__MASK;
2678 }
2679 #define A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK                    0x0000ff00
2680 #define A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT                   8
2681 static inline uint32_t A4XX_SP_GS_PARAM_REG_PRIMREGID(uint32_t val)
2682 {
2683         return ((val) << A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK;
2684 }
2685 #define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK                0xfff00000
2686 #define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT               20
2687 static inline uint32_t A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR(uint32_t val)
2688 {
2689         return ((val) << A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK;
2690 }
2691
2692 static inline uint32_t REG_A4XX_SP_GS_OUT(uint32_t i0) { return 0x00002342 + 0x1*i0; }
2693
2694 static inline uint32_t REG_A4XX_SP_GS_OUT_REG(uint32_t i0) { return 0x00002342 + 0x1*i0; }
2695 #define A4XX_SP_GS_OUT_REG_A_REGID__MASK                        0x000001ff
2696 #define A4XX_SP_GS_OUT_REG_A_REGID__SHIFT                       0
2697 static inline uint32_t A4XX_SP_GS_OUT_REG_A_REGID(uint32_t val)
2698 {
2699         return ((val) << A4XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_A_REGID__MASK;
2700 }
2701 #define A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK                     0x00001e00
2702 #define A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT                    9
2703 static inline uint32_t A4XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val)
2704 {
2705         return ((val) << A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK;
2706 }
2707 #define A4XX_SP_GS_OUT_REG_B_REGID__MASK                        0x01ff0000
2708 #define A4XX_SP_GS_OUT_REG_B_REGID__SHIFT                       16
2709 static inline uint32_t A4XX_SP_GS_OUT_REG_B_REGID(uint32_t val)
2710 {
2711         return ((val) << A4XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_B_REGID__MASK;
2712 }
2713 #define A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK                     0x1e000000
2714 #define A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT                    25
2715 static inline uint32_t A4XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val)
2716 {
2717         return ((val) << A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK;
2718 }
2719
2720 static inline uint32_t REG_A4XX_SP_GS_VPC_DST(uint32_t i0) { return 0x00002353 + 0x1*i0; }
2721
2722 static inline uint32_t REG_A4XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x00002353 + 0x1*i0; }
2723 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK                    0x000000ff
2724 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT                   0
2725 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val)
2726 {
2727         return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK;
2728 }
2729 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK                    0x0000ff00
2730 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT                   8
2731 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val)
2732 {
2733         return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK;
2734 }
2735 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK                    0x00ff0000
2736 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT                   16
2737 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val)
2738 {
2739         return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK;
2740 }
2741 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK                    0xff000000
2742 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT                   24
2743 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val)
2744 {
2745         return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK;
2746 }
2747
2748 #define REG_A4XX_SP_GS_OBJ_OFFSET_REG                           0x0000235b
2749 #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK       0x01ff0000
2750 #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT      16
2751 static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
2752 {
2753         return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
2754 }
2755 #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK         0xfe000000
2756 #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT        25
2757 static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
2758 {
2759         return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
2760 }
2761
2762 #define REG_A4XX_SP_GS_OBJ_START                                0x0000235c
2763
2764 #define REG_A4XX_SP_GS_PVT_MEM_PARAM                            0x0000235d
2765
2766 #define REG_A4XX_SP_GS_PVT_MEM_ADDR                             0x0000235e
2767
2768 #define REG_A4XX_SP_GS_LENGTH_REG                               0x00002360
2769
2770 #define REG_A4XX_VPC_DEBUG_RAM_SEL                              0x00000e60
2771
2772 #define REG_A4XX_VPC_DEBUG_RAM_READ                             0x00000e61
2773
2774 #define REG_A4XX_VPC_DEBUG_ECO_CONTROL                          0x00000e64
2775
2776 #define REG_A4XX_VPC_PERFCTR_VPC_SEL_0                          0x00000e65
2777
2778 #define REG_A4XX_VPC_PERFCTR_VPC_SEL_1                          0x00000e66
2779
2780 #define REG_A4XX_VPC_PERFCTR_VPC_SEL_2                          0x00000e67
2781
2782 #define REG_A4XX_VPC_PERFCTR_VPC_SEL_3                          0x00000e68
2783
2784 #define REG_A4XX_VPC_ATTR                                       0x00002140
2785 #define A4XX_VPC_ATTR_TOTALATTR__MASK                           0x000001ff
2786 #define A4XX_VPC_ATTR_TOTALATTR__SHIFT                          0
2787 static inline uint32_t A4XX_VPC_ATTR_TOTALATTR(uint32_t val)
2788 {
2789         return ((val) << A4XX_VPC_ATTR_TOTALATTR__SHIFT) & A4XX_VPC_ATTR_TOTALATTR__MASK;
2790 }
2791 #define A4XX_VPC_ATTR_PSIZE                                     0x00000200
2792 #define A4XX_VPC_ATTR_THRDASSIGN__MASK                          0x00003000
2793 #define A4XX_VPC_ATTR_THRDASSIGN__SHIFT                         12
2794 static inline uint32_t A4XX_VPC_ATTR_THRDASSIGN(uint32_t val)
2795 {
2796         return ((val) << A4XX_VPC_ATTR_THRDASSIGN__SHIFT) & A4XX_VPC_ATTR_THRDASSIGN__MASK;
2797 }
2798 #define A4XX_VPC_ATTR_ENABLE                                    0x02000000
2799
2800 #define REG_A4XX_VPC_PACK                                       0x00002141
2801 #define A4XX_VPC_PACK_NUMBYPASSVAR__MASK                        0x000000ff
2802 #define A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT                       0
2803 static inline uint32_t A4XX_VPC_PACK_NUMBYPASSVAR(uint32_t val)
2804 {
2805         return ((val) << A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT) & A4XX_VPC_PACK_NUMBYPASSVAR__MASK;
2806 }
2807 #define A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK                      0x0000ff00
2808 #define A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT                     8
2809 static inline uint32_t A4XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val)
2810 {
2811         return ((val) << A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK;
2812 }
2813 #define A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK                      0x00ff0000
2814 #define A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT                     16
2815 static inline uint32_t A4XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val)
2816 {
2817         return ((val) << A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK;
2818 }
2819
2820 static inline uint32_t REG_A4XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002142 + 0x1*i0; }
2821
2822 static inline uint32_t REG_A4XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002142 + 0x1*i0; }
2823
2824 static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000214a + 0x1*i0; }
2825
2826 static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000214a + 0x1*i0; }
2827
2828 #define REG_A4XX_VPC_SO_FLUSH_WADDR_3                           0x0000216e
2829
2830 #define REG_A4XX_VSC_BIN_SIZE                                   0x00000c00
2831 #define A4XX_VSC_BIN_SIZE_WIDTH__MASK                           0x0000001f
2832 #define A4XX_VSC_BIN_SIZE_WIDTH__SHIFT                          0
2833 static inline uint32_t A4XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
2834 {
2835         return ((val >> 5) << A4XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A4XX_VSC_BIN_SIZE_WIDTH__MASK;
2836 }
2837 #define A4XX_VSC_BIN_SIZE_HEIGHT__MASK                          0x000003e0
2838 #define A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT                         5
2839 static inline uint32_t A4XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
2840 {
2841         return ((val >> 5) << A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A4XX_VSC_BIN_SIZE_HEIGHT__MASK;
2842 }
2843
2844 #define REG_A4XX_VSC_SIZE_ADDRESS                               0x00000c01
2845
2846 #define REG_A4XX_VSC_SIZE_ADDRESS2                              0x00000c02
2847
2848 #define REG_A4XX_VSC_DEBUG_ECO_CONTROL                          0x00000c03
2849
2850 static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c08 + 0x1*i0; }
2851
2852 static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c08 + 0x1*i0; }
2853 #define A4XX_VSC_PIPE_CONFIG_REG_X__MASK                        0x000003ff
2854 #define A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT                       0
2855 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
2856 {
2857         return ((val) << A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_X__MASK;
2858 }
2859 #define A4XX_VSC_PIPE_CONFIG_REG_Y__MASK                        0x000ffc00
2860 #define A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT                       10
2861 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
2862 {
2863         return ((val) << A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_Y__MASK;
2864 }
2865 #define A4XX_VSC_PIPE_CONFIG_REG_W__MASK                        0x00f00000
2866 #define A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT                       20
2867 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
2868 {
2869         return ((val) << A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_W__MASK;
2870 }
2871 #define A4XX_VSC_PIPE_CONFIG_REG_H__MASK                        0x0f000000
2872 #define A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT                       24
2873 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
2874 {
2875         return ((val) << A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_H__MASK;
2876 }
2877
2878 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
2879
2880 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
2881
2882 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c18 + 0x1*i0; }
2883
2884 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c18 + 0x1*i0; }
2885
2886 #define REG_A4XX_VSC_PIPE_PARTIAL_POSN_1                        0x00000c41
2887
2888 #define REG_A4XX_VSC_PERFCTR_VSC_SEL_0                          0x00000c50
2889
2890 #define REG_A4XX_VSC_PERFCTR_VSC_SEL_1                          0x00000c51
2891
2892 #define REG_A4XX_VFD_DEBUG_CONTROL                              0x00000e40
2893
2894 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_0                          0x00000e43
2895
2896 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_1                          0x00000e44
2897
2898 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_2                          0x00000e45
2899
2900 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_3                          0x00000e46
2901
2902 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_4                          0x00000e47
2903
2904 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_5                          0x00000e48
2905
2906 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_6                          0x00000e49
2907
2908 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_7                          0x00000e4a
2909
2910 #define REG_A4XX_VGT_CL_INITIATOR                               0x000021d0
2911
2912 #define REG_A4XX_VGT_EVENT_INITIATOR                            0x000021d9
2913
2914 #define REG_A4XX_VFD_CONTROL_0                                  0x00002200
2915 #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK                  0x000000ff
2916 #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT                 0
2917 static inline uint32_t A4XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val)
2918 {
2919         return ((val) << A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK;
2920 }
2921 #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK                  0x0001fe00
2922 #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT                 9
2923 static inline uint32_t A4XX_VFD_CONTROL_0_BYPASSATTROVS(uint32_t val)
2924 {
2925         return ((val) << A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT) & A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK;
2926 }
2927 #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK                0x03f00000
2928 #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT               20
2929 static inline uint32_t A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val)
2930 {
2931         return ((val) << A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK;
2932 }
2933 #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK              0xfc000000
2934 #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT             26
2935 static inline uint32_t A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val)
2936 {
2937         return ((val) << A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK;
2938 }
2939
2940 #define REG_A4XX_VFD_CONTROL_1                                  0x00002201
2941 #define A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK                     0x0000ffff
2942 #define A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT                    0
2943 static inline uint32_t A4XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val)
2944 {
2945         return ((val) << A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK;
2946 }
2947 #define A4XX_VFD_CONTROL_1_REGID4VTX__MASK                      0x00ff0000
2948 #define A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT                     16
2949 static inline uint32_t A4XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
2950 {
2951         return ((val) << A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A4XX_VFD_CONTROL_1_REGID4VTX__MASK;
2952 }
2953 #define A4XX_VFD_CONTROL_1_REGID4INST__MASK                     0xff000000
2954 #define A4XX_VFD_CONTROL_1_REGID4INST__SHIFT                    24
2955 static inline uint32_t A4XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
2956 {
2957         return ((val) << A4XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A4XX_VFD_CONTROL_1_REGID4INST__MASK;
2958 }
2959
2960 #define REG_A4XX_VFD_CONTROL_2                                  0x00002202
2961
2962 #define REG_A4XX_VFD_CONTROL_3                                  0x00002203
2963 #define A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK                   0x0000ff00
2964 #define A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT                  8
2965 static inline uint32_t A4XX_VFD_CONTROL_3_REGID_VTXCNT(uint32_t val)
2966 {
2967         return ((val) << A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT) & A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK;
2968 }
2969 #define A4XX_VFD_CONTROL_3_REGID_TESSX__MASK                    0x00ff0000
2970 #define A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT                   16
2971 static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)
2972 {
2973         return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSX__MASK;
2974 }
2975 #define A4XX_VFD_CONTROL_3_REGID_TESSY__MASK                    0xff000000
2976 #define A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT                   24
2977 static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
2978 {
2979         return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSY__MASK;
2980 }
2981
2982 #define REG_A4XX_VFD_CONTROL_4                                  0x00002204
2983
2984 #define REG_A4XX_VFD_INDEX_OFFSET                               0x00002208
2985
2986 static inline uint32_t REG_A4XX_VFD_FETCH(uint32_t i0) { return 0x0000220a + 0x4*i0; }
2987
2988 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x0000220a + 0x4*i0; }
2989 #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK                  0x0000007f
2990 #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT                 0
2991 static inline uint32_t A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val)
2992 {
2993         return ((val) << A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK;
2994 }
2995 #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK                  0x0001ff80
2996 #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT                 7
2997 static inline uint32_t A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val)
2998 {
2999         return ((val) << A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK;
3000 }
3001 #define A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT                       0x00080000
3002 #define A4XX_VFD_FETCH_INSTR_0_INSTANCED                        0x00100000
3003
3004 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x0000220b + 0x4*i0; }
3005
3006 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_2(uint32_t i0) { return 0x0000220c + 0x4*i0; }
3007 #define A4XX_VFD_FETCH_INSTR_2_SIZE__MASK                       0xfffffff0
3008 #define A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT                      4
3009 static inline uint32_t A4XX_VFD_FETCH_INSTR_2_SIZE(uint32_t val)
3010 {
3011         return ((val >> 4) << A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_2_SIZE__MASK;
3012 }
3013
3014 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_3(uint32_t i0) { return 0x0000220d + 0x4*i0; }
3015 #define A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK                   0x000001ff
3016 #define A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT                  0
3017 static inline uint32_t A4XX_VFD_FETCH_INSTR_3_STEPRATE(uint32_t val)
3018 {
3019         return ((val) << A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT) & A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK;
3020 }
3021
3022 static inline uint32_t REG_A4XX_VFD_DECODE(uint32_t i0) { return 0x0000228a + 0x1*i0; }
3023
3024 static inline uint32_t REG_A4XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000228a + 0x1*i0; }
3025 #define A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK                   0x0000000f
3026 #define A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT                  0
3027 static inline uint32_t A4XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val)
3028 {
3029         return ((val) << A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK;
3030 }
3031 #define A4XX_VFD_DECODE_INSTR_CONSTFILL                         0x00000010
3032 #define A4XX_VFD_DECODE_INSTR_FORMAT__MASK                      0x00000fc0
3033 #define A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT                     6
3034 static inline uint32_t A4XX_VFD_DECODE_INSTR_FORMAT(enum a4xx_vtx_fmt val)
3035 {
3036         return ((val) << A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A4XX_VFD_DECODE_INSTR_FORMAT__MASK;
3037 }
3038 #define A4XX_VFD_DECODE_INSTR_REGID__MASK                       0x000ff000
3039 #define A4XX_VFD_DECODE_INSTR_REGID__SHIFT                      12
3040 static inline uint32_t A4XX_VFD_DECODE_INSTR_REGID(uint32_t val)
3041 {
3042         return ((val) << A4XX_VFD_DECODE_INSTR_REGID__SHIFT) & A4XX_VFD_DECODE_INSTR_REGID__MASK;
3043 }
3044 #define A4XX_VFD_DECODE_INSTR_INT                               0x00100000
3045 #define A4XX_VFD_DECODE_INSTR_SWAP__MASK                        0x00c00000
3046 #define A4XX_VFD_DECODE_INSTR_SWAP__SHIFT                       22
3047 static inline uint32_t A4XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
3048 {
3049         return ((val) << A4XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A4XX_VFD_DECODE_INSTR_SWAP__MASK;
3050 }
3051 #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK                    0x1f000000
3052 #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT                   24
3053 static inline uint32_t A4XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val)
3054 {
3055         return ((val) << A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK;
3056 }
3057 #define A4XX_VFD_DECODE_INSTR_LASTCOMPVALID                     0x20000000
3058 #define A4XX_VFD_DECODE_INSTR_SWITCHNEXT                        0x40000000
3059
3060 #define REG_A4XX_TPL1_DEBUG_ECO_CONTROL                         0x00000f00
3061
3062 #define REG_A4XX_TPL1_TP_MODE_CONTROL                           0x00000f03
3063
3064 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_0                          0x00000f04
3065
3066 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_1                          0x00000f05
3067
3068 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_2                          0x00000f06
3069
3070 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_3                          0x00000f07
3071
3072 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_4                          0x00000f08
3073
3074 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_5                          0x00000f09
3075
3076 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_6                          0x00000f0a
3077
3078 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_7                          0x00000f0b
3079
3080 #define REG_A4XX_TPL1_TP_TEX_OFFSET                             0x00002380
3081
3082 #define REG_A4XX_TPL1_TP_TEX_COUNT                              0x00002381
3083 #define A4XX_TPL1_TP_TEX_COUNT_VS__MASK                         0x000000ff
3084 #define A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT                        0
3085 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_VS(uint32_t val)
3086 {
3087         return ((val) << A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_VS__MASK;
3088 }
3089 #define A4XX_TPL1_TP_TEX_COUNT_HS__MASK                         0x0000ff00
3090 #define A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT                        8
3091 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_HS(uint32_t val)
3092 {
3093         return ((val) << A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_HS__MASK;
3094 }
3095 #define A4XX_TPL1_TP_TEX_COUNT_DS__MASK                         0x00ff0000
3096 #define A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT                        16
3097 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_DS(uint32_t val)
3098 {
3099         return ((val) << A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_DS__MASK;
3100 }
3101 #define A4XX_TPL1_TP_TEX_COUNT_GS__MASK                         0xff000000
3102 #define A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT                        24
3103 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_GS(uint32_t val)
3104 {
3105         return ((val) << A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_GS__MASK;
3106 }
3107
3108 #define REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR              0x00002384
3109
3110 #define REG_A4XX_TPL1_TP_HS_BORDER_COLOR_BASE_ADDR              0x00002387
3111
3112 #define REG_A4XX_TPL1_TP_DS_BORDER_COLOR_BASE_ADDR              0x0000238a
3113
3114 #define REG_A4XX_TPL1_TP_GS_BORDER_COLOR_BASE_ADDR              0x0000238d
3115
3116 #define REG_A4XX_TPL1_TP_FS_TEX_COUNT                           0x000023a0
3117
3118 #define REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR              0x000023a1
3119
3120 #define REG_A4XX_TPL1_TP_CS_BORDER_COLOR_BASE_ADDR              0x000023a4
3121
3122 #define REG_A4XX_TPL1_TP_CS_SAMPLER_BASE_ADDR                   0x000023a5
3123
3124 #define REG_A4XX_TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR                 0x000023a6
3125
3126 #define REG_A4XX_GRAS_TSE_STATUS                                0x00000c80
3127
3128 #define REG_A4XX_GRAS_DEBUG_ECO_CONTROL                         0x00000c81
3129
3130 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_0                         0x00000c88
3131
3132 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_1                         0x00000c89
3133
3134 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_2                         0x00000c8a
3135
3136 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_3                         0x00000c8b
3137
3138 #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_0                         0x00000c8c
3139
3140 #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_1                         0x00000c8d
3141
3142 #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_2                         0x00000c8e
3143
3144 #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_3                         0x00000c8f
3145
3146 #define REG_A4XX_GRAS_CL_CLIP_CNTL                              0x00002000
3147 #define A4XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE                     0x00008000
3148 #define A4XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z                  0x00400000
3149
3150 #define REG_A4XX_GRAS_CLEAR_CNTL                                0x00002003
3151 #define A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR                      0x00000001
3152
3153 #define REG_A4XX_GRAS_CL_GB_CLIP_ADJ                            0x00002004
3154 #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK                     0x000003ff
3155 #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT                    0
3156 static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val)
3157 {
3158         return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK;
3159 }
3160 #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK                     0x000ffc00
3161 #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT                    10
3162 static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val)
3163 {
3164         return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK;
3165 }
3166
3167 #define REG_A4XX_GRAS_CL_VPORT_XOFFSET_0                        0x00002008
3168 #define A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK                      0xffffffff
3169 #define A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT                     0
3170 static inline uint32_t A4XX_GRAS_CL_VPORT_XOFFSET_0(float val)
3171 {
3172         return ((fui(val)) << A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK;
3173 }
3174
3175 #define REG_A4XX_GRAS_CL_VPORT_XSCALE_0                         0x00002009
3176 #define A4XX_GRAS_CL_VPORT_XSCALE_0__MASK                       0xffffffff
3177 #define A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT                      0
3178 static inline uint32_t A4XX_GRAS_CL_VPORT_XSCALE_0(float val)
3179 {
3180         return ((fui(val)) << A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_XSCALE_0__MASK;
3181 }
3182
3183 #define REG_A4XX_GRAS_CL_VPORT_YOFFSET_0                        0x0000200a
3184 #define A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK                      0xffffffff
3185 #define A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT                     0
3186 static inline uint32_t A4XX_GRAS_CL_VPORT_YOFFSET_0(float val)
3187 {
3188         return ((fui(val)) << A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK;
3189 }
3190
3191 #define REG_A4XX_GRAS_CL_VPORT_YSCALE_0                         0x0000200b
3192 #define A4XX_GRAS_CL_VPORT_YSCALE_0__MASK                       0xffffffff
3193 #define A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT                      0
3194 static inline uint32_t A4XX_GRAS_CL_VPORT_YSCALE_0(float val)
3195 {
3196         return ((fui(val)) << A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_YSCALE_0__MASK;
3197 }
3198
3199 #define REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0                        0x0000200c
3200 #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK                      0xffffffff
3201 #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT                     0
3202 static inline uint32_t A4XX_GRAS_CL_VPORT_ZOFFSET_0(float val)
3203 {
3204         return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK;
3205 }
3206
3207 #define REG_A4XX_GRAS_CL_VPORT_ZSCALE_0                         0x0000200d
3208 #define A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK                       0xffffffff
3209 #define A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT                      0
3210 static inline uint32_t A4XX_GRAS_CL_VPORT_ZSCALE_0(float val)
3211 {
3212         return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK;
3213 }
3214
3215 #define REG_A4XX_GRAS_SU_POINT_MINMAX                           0x00002070
3216 #define A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK                     0x0000ffff
3217 #define A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT                    0
3218 static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MIN(float val)
3219 {
3220         return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
3221 }
3222 #define A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK                     0xffff0000
3223 #define A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT                    16
3224 static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MAX(float val)
3225 {
3226         return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
3227 }
3228
3229 #define REG_A4XX_GRAS_SU_POINT_SIZE                             0x00002071
3230 #define A4XX_GRAS_SU_POINT_SIZE__MASK                           0xffffffff
3231 #define A4XX_GRAS_SU_POINT_SIZE__SHIFT                          0
3232 static inline uint32_t A4XX_GRAS_SU_POINT_SIZE(float val)
3233 {
3234         return ((((int32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_SIZE__SHIFT) & A4XX_GRAS_SU_POINT_SIZE__MASK;
3235 }
3236
3237 #define REG_A4XX_GRAS_ALPHA_CONTROL                             0x00002073
3238 #define A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE               0x00000004
3239 #define A4XX_GRAS_ALPHA_CONTROL_FORCE_FRAGZ_TO_FS               0x00000008
3240
3241 #define REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE                      0x00002074
3242 #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK                    0xffffffff
3243 #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT                   0
3244 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
3245 {
3246         return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK;
3247 }
3248
3249 #define REG_A4XX_GRAS_SU_POLY_OFFSET_OFFSET                     0x00002075
3250 #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK                   0xffffffff
3251 #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT                  0
3252 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
3253 {
3254         return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
3255 }
3256
3257 #define REG_A4XX_GRAS_SU_POLY_OFFSET_CLAMP                      0x00002076
3258 #define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK                    0xffffffff
3259 #define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT                   0
3260 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_CLAMP(float val)
3261 {
3262         return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK;
3263 }
3264
3265 #define REG_A4XX_GRAS_DEPTH_CONTROL                             0x00002077
3266 #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK                    0x00000003
3267 #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT                   0
3268 static inline uint32_t A4XX_GRAS_DEPTH_CONTROL_FORMAT(enum a4xx_depth_format val)
3269 {
3270         return ((val) << A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT) & A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK;
3271 }
3272
3273 #define REG_A4XX_GRAS_SU_MODE_CONTROL                           0x00002078
3274 #define A4XX_GRAS_SU_MODE_CONTROL_CULL_FRONT                    0x00000001
3275 #define A4XX_GRAS_SU_MODE_CONTROL_CULL_BACK                     0x00000002
3276 #define A4XX_GRAS_SU_MODE_CONTROL_FRONT_CW                      0x00000004
3277 #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK           0x000007f8
3278 #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT          3
3279 static inline uint32_t A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val)
3280 {
3281         return ((((int32_t)(val * 4.0))) << A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK;
3282 }
3283 #define A4XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET                   0x00000800
3284 #define A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS                0x00100000
3285
3286 #define REG_A4XX_GRAS_SC_CONTROL                                0x0000207b
3287 #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK                  0x0000000c
3288 #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT                 2
3289 static inline uint32_t A4XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val)
3290 {
3291         return ((val) << A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK;
3292 }
3293 #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK                 0x00000380
3294 #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT                7
3295 static inline uint32_t A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(uint32_t val)
3296 {
3297         return ((val) << A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK;
3298 }
3299 #define A4XX_GRAS_SC_CONTROL_MSAA_DISABLE                       0x00000800
3300 #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK                  0x0000f000
3301 #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT                 12
3302 static inline uint32_t A4XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val)
3303 {
3304         return ((val) << A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK;
3305 }
3306
3307 #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL                      0x0000207c
3308 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE    0x80000000
3309 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK                  0x00007fff
3310 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT                 0
3311 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
3312 {
3313         return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK;
3314 }
3315 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK                  0x7fff0000
3316 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT                 16
3317 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
3318 {
3319         return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK;
3320 }
3321
3322 #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_BR                      0x0000207d
3323 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE    0x80000000
3324 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK                  0x00007fff
3325 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT                 0
3326 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
3327 {
3328         return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK;
3329 }
3330 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK                  0x7fff0000
3331 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT                 16
3332 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
3333 {
3334         return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK;
3335 }
3336
3337 #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR                      0x0000209c
3338 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE    0x80000000
3339 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK                  0x00007fff
3340 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT                 0
3341 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
3342 {
3343         return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
3344 }
3345 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK                  0x7fff0000
3346 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT                 16
3347 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
3348 {
3349         return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
3350 }
3351
3352 #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_TL                      0x0000209d
3353 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE    0x80000000
3354 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK                  0x00007fff
3355 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT                 0
3356 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
3357 {
3358         return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
3359 }
3360 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK                  0x7fff0000
3361 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT                 16
3362 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
3363 {
3364         return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
3365 }
3366
3367 #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_BR                       0x0000209e
3368 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_WINDOW_OFFSET_DISABLE     0x80000000
3369 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK                   0x00007fff
3370 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT                  0
3371 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_X(uint32_t val)
3372 {
3373         return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK;
3374 }
3375 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK                   0x7fff0000
3376 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT                  16
3377 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y(uint32_t val)
3378 {
3379         return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK;
3380 }
3381
3382 #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_TL                       0x0000209f
3383 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_WINDOW_OFFSET_DISABLE     0x80000000
3384 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK                   0x00007fff
3385 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT                  0
3386 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_X(uint32_t val)
3387 {
3388         return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK;
3389 }
3390 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK                   0x7fff0000
3391 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT                  16
3392 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y(uint32_t val)
3393 {
3394         return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK;
3395 }
3396
3397 #define REG_A4XX_UCHE_CACHE_MODE_CONTROL                        0x00000e80
3398
3399 #define REG_A4XX_UCHE_TRAP_BASE_LO                              0x00000e83
3400
3401 #define REG_A4XX_UCHE_TRAP_BASE_HI                              0x00000e84
3402
3403 #define REG_A4XX_UCHE_CACHE_STATUS                              0x00000e88
3404
3405 #define REG_A4XX_UCHE_INVALIDATE0                               0x00000e8a
3406
3407 #define REG_A4XX_UCHE_INVALIDATE1                               0x00000e8b
3408
3409 #define REG_A4XX_UCHE_CACHE_WAYS_VFD                            0x00000e8c
3410
3411 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_0                        0x00000e8e
3412
3413 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_1                        0x00000e8f
3414
3415 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_2                        0x00000e90
3416
3417 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_3                        0x00000e91
3418
3419 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_4                        0x00000e92
3420
3421 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_5                        0x00000e93
3422
3423 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_6                        0x00000e94
3424
3425 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_7                        0x00000e95
3426
3427 #define REG_A4XX_HLSQ_TIMEOUT_THRESHOLD                         0x00000e00
3428
3429 #define REG_A4XX_HLSQ_DEBUG_ECO_CONTROL                         0x00000e04
3430
3431 #define REG_A4XX_HLSQ_MODE_CONTROL                              0x00000e05
3432
3433 #define REG_A4XX_HLSQ_PERF_PIPE_MASK                            0x00000e0e
3434
3435 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_0                        0x00000e06
3436
3437 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_1                        0x00000e07
3438
3439 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_2                        0x00000e08
3440
3441 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_3                        0x00000e09
3442
3443 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_4                        0x00000e0a
3444
3445 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_5                        0x00000e0b
3446
3447 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_6                        0x00000e0c
3448
3449 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_7                        0x00000e0d
3450
3451 #define REG_A4XX_HLSQ_CONTROL_0_REG                             0x000023c0
3452 #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK              0x00000010
3453 #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT             4
3454 static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)
3455 {
3456         return ((val) << A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK;
3457 }
3458 #define A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE             0x00000040
3459 #define A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART                 0x00000200
3460 #define A4XX_HLSQ_CONTROL_0_REG_RESERVED2                       0x00000400
3461 #define A4XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE                    0x04000000
3462 #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK                 0x08000000
3463 #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT                27
3464 static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val)
3465 {
3466         return ((val) << A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK;
3467 }
3468 #define A4XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE               0x10000000
3469 #define A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE               0x20000000
3470 #define A4XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE                    0x40000000
3471 #define A4XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT                   0x80000000
3472
3473 #define REG_A4XX_HLSQ_CONTROL_1_REG                             0x000023c1
3474 #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK              0x00000040
3475 #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT             6
3476 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val)
3477 {
3478         return ((val) << A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK;
3479 }
3480 #define A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE             0x00000100
3481 #define A4XX_HLSQ_CONTROL_1_REG_RESERVED1                       0x00000200
3482 #define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK                0x00ff0000
3483 #define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT               16
3484 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_COORDREGID(uint32_t val)
3485 {
3486         return ((val) << A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK;
3487 }
3488 #define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK              0xff000000
3489 #define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT             24
3490 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(uint32_t val)
3491 {
3492         return ((val) << A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK;
3493 }
3494
3495 #define REG_A4XX_HLSQ_CONTROL_2_REG                             0x000023c2
3496 #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK        0xfc000000
3497 #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT       26
3498 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val)
3499 {
3500         return ((val) << A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK;
3501 }
3502 #define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK                 0x000003fc
3503 #define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT                2
3504 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
3505 {
3506         return ((val) << A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
3507 }
3508 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK            0x0003fc00
3509 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT           10
3510 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID(uint32_t val)
3511 {
3512         return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK;
3513 }
3514 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK          0x03fc0000
3515 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT         18
3516 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID(uint32_t val)
3517 {
3518         return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK;
3519 }
3520
3521 #define REG_A4XX_HLSQ_CONTROL_3_REG                             0x000023c3
3522 #define A4XX_HLSQ_CONTROL_3_REG_REGID__MASK                     0x000000ff
3523 #define A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT                    0
3524 static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val)
3525 {
3526         return ((val) << A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_REGID__MASK;
3527 }
3528
3529 #define REG_A4XX_HLSQ_CONTROL_4_REG                             0x000023c4
3530
3531 #define REG_A4XX_HLSQ_VS_CONTROL_REG                            0x000023c5
3532 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK              0x000000ff
3533 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT             0
3534 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val)
3535 {
3536         return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK;
3537 }
3538 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK        0x0000ff00
3539 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT       8
3540 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3541 {
3542         return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3543 }
3544 #define A4XX_HLSQ_VS_CONTROL_REG_ENABLED                        0x00010000
3545 #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK          0x00fe0000
3546 #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT         17
3547 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3548 {
3549         return ((val) << A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3550 }
3551 #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK              0xff000000
3552 #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT             24
3553 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val)
3554 {
3555         return ((val) << A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK;
3556 }
3557
3558 #define REG_A4XX_HLSQ_FS_CONTROL_REG                            0x000023c6
3559 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK              0x000000ff
3560 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT             0
3561 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val)
3562 {
3563         return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK;
3564 }
3565 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK        0x0000ff00
3566 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT       8
3567 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3568 {
3569         return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3570 }
3571 #define A4XX_HLSQ_FS_CONTROL_REG_ENABLED                        0x00010000
3572 #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK          0x00fe0000
3573 #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT         17
3574 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3575 {
3576         return ((val) << A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3577 }
3578 #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK              0xff000000
3579 #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT             24
3580 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val)
3581 {
3582         return ((val) << A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK;
3583 }
3584
3585 #define REG_A4XX_HLSQ_HS_CONTROL_REG                            0x000023c7
3586 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK              0x000000ff
3587 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT             0
3588 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(uint32_t val)
3589 {
3590         return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK;
3591 }
3592 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK        0x0000ff00
3593 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT       8
3594 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3595 {
3596         return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3597 }
3598 #define A4XX_HLSQ_HS_CONTROL_REG_ENABLED                        0x00010000
3599 #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK          0x00fe0000
3600 #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT         17
3601 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3602 {
3603         return ((val) << A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3604 }
3605 #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK              0xff000000
3606 #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT             24
3607 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(uint32_t val)
3608 {
3609         return ((val) << A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK;
3610 }
3611
3612 #define REG_A4XX_HLSQ_DS_CONTROL_REG                            0x000023c8
3613 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK              0x000000ff
3614 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT             0
3615 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(uint32_t val)
3616 {
3617         return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK;
3618 }
3619 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK        0x0000ff00
3620 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT       8
3621 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3622 {
3623         return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3624 }
3625 #define A4XX_HLSQ_DS_CONTROL_REG_ENABLED                        0x00010000
3626 #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK          0x00fe0000
3627 #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT         17
3628 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3629 {
3630         return ((val) << A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3631 }
3632 #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK              0xff000000
3633 #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT             24
3634 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(uint32_t val)
3635 {
3636         return ((val) << A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK;
3637 }
3638
3639 #define REG_A4XX_HLSQ_GS_CONTROL_REG                            0x000023c9
3640 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK              0x000000ff
3641 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT             0
3642 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(uint32_t val)
3643 {
3644         return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK;
3645 }
3646 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK        0x0000ff00
3647 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT       8
3648 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3649 {
3650         return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3651 }
3652 #define A4XX_HLSQ_GS_CONTROL_REG_ENABLED                        0x00010000
3653 #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK          0x00fe0000
3654 #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT         17
3655 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3656 {
3657         return ((val) << A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3658 }
3659 #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK              0xff000000
3660 #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT             24
3661 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val)
3662 {
3663         return ((val) << A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK;
3664 }
3665
3666 #define REG_A4XX_HLSQ_CS_CONTROL                                0x000023ca
3667
3668 #define REG_A4XX_HLSQ_CL_NDRANGE_0                              0x000023cd
3669
3670 #define REG_A4XX_HLSQ_CL_NDRANGE_1                              0x000023ce
3671
3672 #define REG_A4XX_HLSQ_CL_NDRANGE_2                              0x000023cf
3673
3674 #define REG_A4XX_HLSQ_CL_NDRANGE_3                              0x000023d0
3675
3676 #define REG_A4XX_HLSQ_CL_NDRANGE_4                              0x000023d1
3677
3678 #define REG_A4XX_HLSQ_CL_NDRANGE_5                              0x000023d2
3679
3680 #define REG_A4XX_HLSQ_CL_NDRANGE_6                              0x000023d3
3681
3682 #define REG_A4XX_HLSQ_CL_CONTROL_0                              0x000023d4
3683
3684 #define REG_A4XX_HLSQ_CL_CONTROL_1                              0x000023d5
3685
3686 #define REG_A4XX_HLSQ_CL_KERNEL_CONST                           0x000023d6
3687
3688 #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_X                         0x000023d7
3689
3690 #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Y                         0x000023d8
3691
3692 #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Z                         0x000023d9
3693
3694 #define REG_A4XX_HLSQ_CL_WG_OFFSET                              0x000023da
3695
3696 #define REG_A4XX_HLSQ_UPDATE_CONTROL                            0x000023db
3697
3698 #define REG_A4XX_PC_BINNING_COMMAND                             0x00000d00
3699 #define A4XX_PC_BINNING_COMMAND_BINNING_ENABLE                  0x00000001
3700
3701 #define REG_A4XX_PC_DRAWCALL_SETUP_OVERRIDE                     0x00000d0c
3702
3703 #define REG_A4XX_PC_PERFCTR_PC_SEL_0                            0x00000d10
3704
3705 #define REG_A4XX_PC_PERFCTR_PC_SEL_1                            0x00000d11
3706
3707 #define REG_A4XX_PC_PERFCTR_PC_SEL_2                            0x00000d12
3708
3709 #define REG_A4XX_PC_PERFCTR_PC_SEL_3                            0x00000d13
3710
3711 #define REG_A4XX_PC_PERFCTR_PC_SEL_4                            0x00000d14
3712
3713 #define REG_A4XX_PC_PERFCTR_PC_SEL_5                            0x00000d15
3714
3715 #define REG_A4XX_PC_PERFCTR_PC_SEL_6                            0x00000d16
3716
3717 #define REG_A4XX_PC_PERFCTR_PC_SEL_7                            0x00000d17
3718
3719 #define REG_A4XX_PC_BIN_BASE                                    0x000021c0
3720
3721 #define REG_A4XX_PC_VSTREAM_CONTROL                             0x000021c2
3722 #define A4XX_PC_VSTREAM_CONTROL_SIZE__MASK                      0x003f0000
3723 #define A4XX_PC_VSTREAM_CONTROL_SIZE__SHIFT                     16
3724 static inline uint32_t A4XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val)
3725 {
3726         return ((val) << A4XX_PC_VSTREAM_CONTROL_SIZE__SHIFT) & A4XX_PC_VSTREAM_CONTROL_SIZE__MASK;
3727 }
3728 #define A4XX_PC_VSTREAM_CONTROL_N__MASK                         0x07c00000
3729 #define A4XX_PC_VSTREAM_CONTROL_N__SHIFT                        22
3730 static inline uint32_t A4XX_PC_VSTREAM_CONTROL_N(uint32_t val)
3731 {
3732         return ((val) << A4XX_PC_VSTREAM_CONTROL_N__SHIFT) & A4XX_PC_VSTREAM_CONTROL_N__MASK;
3733 }
3734
3735 #define REG_A4XX_PC_PRIM_VTX_CNTL                               0x000021c4
3736 #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK                      0x0000000f
3737 #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT                     0
3738 static inline uint32_t A4XX_PC_PRIM_VTX_CNTL_VAROUT(uint32_t val)
3739 {
3740         return ((val) << A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT) & A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK;
3741 }
3742 #define A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART                 0x00100000
3743 #define A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST                0x02000000
3744 #define A4XX_PC_PRIM_VTX_CNTL_PSIZE                             0x04000000
3745
3746 #define REG_A4XX_PC_PRIM_VTX_CNTL2                              0x000021c5
3747 #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__MASK       0x00000007
3748 #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT      0
3749 static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val)
3750 {
3751         return ((val) << A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT) & A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__MASK;
3752 }
3753 #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__MASK        0x00000038
3754 #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__SHIFT       3
3755 static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val)
3756 {
3757         return ((val) << A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__SHIFT) & A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__MASK;
3758 }
3759 #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_ENABLE                  0x00000040
3760
3761 #define REG_A4XX_PC_RESTART_INDEX                               0x000021c6
3762
3763 #define REG_A4XX_PC_GS_PARAM                                    0x000021e5
3764 #define A4XX_PC_GS_PARAM_MAX_VERTICES__MASK                     0x000003ff
3765 #define A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT                    0
3766 static inline uint32_t A4XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val)
3767 {
3768         return ((val) << A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A4XX_PC_GS_PARAM_MAX_VERTICES__MASK;
3769 }
3770 #define A4XX_PC_GS_PARAM_INVOCATIONS__MASK                      0x0000f800
3771 #define A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT                     11
3772 static inline uint32_t A4XX_PC_GS_PARAM_INVOCATIONS(uint32_t val)
3773 {
3774         return ((val) << A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT) & A4XX_PC_GS_PARAM_INVOCATIONS__MASK;
3775 }
3776 #define A4XX_PC_GS_PARAM_PRIMTYPE__MASK                         0x01800000
3777 #define A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT                        23
3778 static inline uint32_t A4XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)
3779 {
3780         return ((val) << A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_GS_PARAM_PRIMTYPE__MASK;
3781 }
3782 #define A4XX_PC_GS_PARAM_LAYER                                  0x80000000
3783
3784 #define REG_A4XX_PC_HS_PARAM                                    0x000021e7
3785 #define A4XX_PC_HS_PARAM_VERTICES_OUT__MASK                     0x0000003f
3786 #define A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT                    0
3787 static inline uint32_t A4XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val)
3788 {
3789         return ((val) << A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT) & A4XX_PC_HS_PARAM_VERTICES_OUT__MASK;
3790 }
3791 #define A4XX_PC_HS_PARAM_SPACING__MASK                          0x00600000
3792 #define A4XX_PC_HS_PARAM_SPACING__SHIFT                         21
3793 static inline uint32_t A4XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val)
3794 {
3795         return ((val) << A4XX_PC_HS_PARAM_SPACING__SHIFT) & A4XX_PC_HS_PARAM_SPACING__MASK;
3796 }
3797 #define A4XX_PC_HS_PARAM_PRIMTYPE__MASK                         0x01800000
3798 #define A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT                        23
3799 static inline uint32_t A4XX_PC_HS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)
3800 {
3801         return ((val) << A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_HS_PARAM_PRIMTYPE__MASK;
3802 }
3803
3804 #define REG_A4XX_VBIF_VERSION                                   0x00003000
3805
3806 #define REG_A4XX_VBIF_CLKON                                     0x00003001
3807 #define A4XX_VBIF_CLKON_FORCE_ON_TESTBUS                        0x00000001
3808
3809 #define REG_A4XX_VBIF_ABIT_SORT                                 0x0000301c
3810
3811 #define REG_A4XX_VBIF_ABIT_SORT_CONF                            0x0000301d
3812
3813 #define REG_A4XX_VBIF_GATE_OFF_WRREQ_EN                         0x0000302a
3814
3815 #define REG_A4XX_VBIF_IN_RD_LIM_CONF0                           0x0000302c
3816
3817 #define REG_A4XX_VBIF_IN_RD_LIM_CONF1                           0x0000302d
3818
3819 #define REG_A4XX_VBIF_IN_WR_LIM_CONF0                           0x00003030
3820
3821 #define REG_A4XX_VBIF_IN_WR_LIM_CONF1                           0x00003031
3822
3823 #define REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB                       0x00003049
3824
3825 #define REG_A4XX_UNKNOWN_0CC5                                   0x00000cc5
3826
3827 #define REG_A4XX_UNKNOWN_0CC6                                   0x00000cc6
3828
3829 #define REG_A4XX_UNKNOWN_0D01                                   0x00000d01
3830
3831 #define REG_A4XX_UNKNOWN_0E42                                   0x00000e42
3832
3833 #define REG_A4XX_UNKNOWN_0EC2                                   0x00000ec2
3834
3835 #define REG_A4XX_UNKNOWN_2001                                   0x00002001
3836
3837 #define REG_A4XX_UNKNOWN_209B                                   0x0000209b
3838
3839 #define REG_A4XX_UNKNOWN_20EF                                   0x000020ef
3840
3841 #define REG_A4XX_UNKNOWN_2152                                   0x00002152
3842
3843 #define REG_A4XX_UNKNOWN_2153                                   0x00002153
3844
3845 #define REG_A4XX_UNKNOWN_2154                                   0x00002154
3846
3847 #define REG_A4XX_UNKNOWN_2155                                   0x00002155
3848
3849 #define REG_A4XX_UNKNOWN_2156                                   0x00002156
3850
3851 #define REG_A4XX_UNKNOWN_2157                                   0x00002157
3852
3853 #define REG_A4XX_UNKNOWN_21C3                                   0x000021c3
3854
3855 #define REG_A4XX_UNKNOWN_21E6                                   0x000021e6
3856
3857 #define REG_A4XX_UNKNOWN_2209                                   0x00002209
3858
3859 #define REG_A4XX_UNKNOWN_22D7                                   0x000022d7
3860
3861 #define REG_A4XX_UNKNOWN_2352                                   0x00002352
3862
3863 #define REG_A4XX_TEX_SAMP_0                                     0x00000000
3864 #define A4XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR                   0x00000001
3865 #define A4XX_TEX_SAMP_0_XY_MAG__MASK                            0x00000006
3866 #define A4XX_TEX_SAMP_0_XY_MAG__SHIFT                           1
3867 static inline uint32_t A4XX_TEX_SAMP_0_XY_MAG(enum a4xx_tex_filter val)
3868 {
3869         return ((val) << A4XX_TEX_SAMP_0_XY_MAG__SHIFT) & A4XX_TEX_SAMP_0_XY_MAG__MASK;
3870 }
3871 #define A4XX_TEX_SAMP_0_XY_MIN__MASK                            0x00000018
3872 #define A4XX_TEX_SAMP_0_XY_MIN__SHIFT                           3
3873 static inline uint32_t A4XX_TEX_SAMP_0_XY_MIN(enum a4xx_tex_filter val)
3874 {
3875         return ((val) << A4XX_TEX_SAMP_0_XY_MIN__SHIFT) & A4XX_TEX_SAMP_0_XY_MIN__MASK;
3876 }
3877 #define A4XX_TEX_SAMP_0_WRAP_S__MASK                            0x000000e0
3878 #define A4XX_TEX_SAMP_0_WRAP_S__SHIFT                           5
3879 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_S(enum a4xx_tex_clamp val)
3880 {
3881         return ((val) << A4XX_TEX_SAMP_0_WRAP_S__SHIFT) & A4XX_TEX_SAMP_0_WRAP_S__MASK;
3882 }
3883 #define A4XX_TEX_SAMP_0_WRAP_T__MASK                            0x00000700
3884 #define A4XX_TEX_SAMP_0_WRAP_T__SHIFT                           8
3885 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_T(enum a4xx_tex_clamp val)
3886 {
3887         return ((val) << A4XX_TEX_SAMP_0_WRAP_T__SHIFT) & A4XX_TEX_SAMP_0_WRAP_T__MASK;
3888 }
3889 #define A4XX_TEX_SAMP_0_WRAP_R__MASK                            0x00003800
3890 #define A4XX_TEX_SAMP_0_WRAP_R__SHIFT                           11
3891 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_R(enum a4xx_tex_clamp val)
3892 {
3893         return ((val) << A4XX_TEX_SAMP_0_WRAP_R__SHIFT) & A4XX_TEX_SAMP_0_WRAP_R__MASK;
3894 }
3895 #define A4XX_TEX_SAMP_0_ANISO__MASK                             0x0001c000
3896 #define A4XX_TEX_SAMP_0_ANISO__SHIFT                            14
3897 static inline uint32_t A4XX_TEX_SAMP_0_ANISO(enum a4xx_tex_aniso val)
3898 {
3899         return ((val) << A4XX_TEX_SAMP_0_ANISO__SHIFT) & A4XX_TEX_SAMP_0_ANISO__MASK;
3900 }
3901 #define A4XX_TEX_SAMP_0_LOD_BIAS__MASK                          0xfff80000
3902 #define A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT                         19
3903 static inline uint32_t A4XX_TEX_SAMP_0_LOD_BIAS(float val)
3904 {
3905         return ((((int32_t)(val * 256.0))) << A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A4XX_TEX_SAMP_0_LOD_BIAS__MASK;
3906 }
3907
3908 #define REG_A4XX_TEX_SAMP_1                                     0x00000001
3909 #define A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK                      0x0000000e
3910 #define A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT                     1
3911 static inline uint32_t A4XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
3912 {
3913         return ((val) << A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
3914 }
3915 #define A4XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF                  0x00000010
3916 #define A4XX_TEX_SAMP_1_UNNORM_COORDS                           0x00000020
3917 #define A4XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR                    0x00000040
3918 #define A4XX_TEX_SAMP_1_MAX_LOD__MASK                           0x000fff00
3919 #define A4XX_TEX_SAMP_1_MAX_LOD__SHIFT                          8
3920 static inline uint32_t A4XX_TEX_SAMP_1_MAX_LOD(float val)
3921 {
3922         return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A4XX_TEX_SAMP_1_MAX_LOD__MASK;
3923 }
3924 #define A4XX_TEX_SAMP_1_MIN_LOD__MASK                           0xfff00000
3925 #define A4XX_TEX_SAMP_1_MIN_LOD__SHIFT                          20
3926 static inline uint32_t A4XX_TEX_SAMP_1_MIN_LOD(float val)
3927 {
3928         return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A4XX_TEX_SAMP_1_MIN_LOD__MASK;
3929 }
3930
3931 #define REG_A4XX_TEX_CONST_0                                    0x00000000
3932 #define A4XX_TEX_CONST_0_TILED                                  0x00000001
3933 #define A4XX_TEX_CONST_0_SRGB                                   0x00000004
3934 #define A4XX_TEX_CONST_0_SWIZ_X__MASK                           0x00000070
3935 #define A4XX_TEX_CONST_0_SWIZ_X__SHIFT                          4
3936 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_X(enum a4xx_tex_swiz val)
3937 {
3938         return ((val) << A4XX_TEX_CONST_0_SWIZ_X__SHIFT) & A4XX_TEX_CONST_0_SWIZ_X__MASK;
3939 }
3940 #define A4XX_TEX_CONST_0_SWIZ_Y__MASK                           0x00000380
3941 #define A4XX_TEX_CONST_0_SWIZ_Y__SHIFT                          7
3942 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Y(enum a4xx_tex_swiz val)
3943 {
3944         return ((val) << A4XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Y__MASK;
3945 }
3946 #define A4XX_TEX_CONST_0_SWIZ_Z__MASK                           0x00001c00
3947 #define A4XX_TEX_CONST_0_SWIZ_Z__SHIFT                          10
3948 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Z(enum a4xx_tex_swiz val)
3949 {
3950         return ((val) << A4XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Z__MASK;
3951 }
3952 #define A4XX_TEX_CONST_0_SWIZ_W__MASK                           0x0000e000
3953 #define A4XX_TEX_CONST_0_SWIZ_W__SHIFT                          13
3954 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_W(enum a4xx_tex_swiz val)
3955 {
3956         return ((val) << A4XX_TEX_CONST_0_SWIZ_W__SHIFT) & A4XX_TEX_CONST_0_SWIZ_W__MASK;
3957 }
3958 #define A4XX_TEX_CONST_0_MIPLVLS__MASK                          0x000f0000
3959 #define A4XX_TEX_CONST_0_MIPLVLS__SHIFT                         16
3960 static inline uint32_t A4XX_TEX_CONST_0_MIPLVLS(uint32_t val)
3961 {
3962         return ((val) << A4XX_TEX_CONST_0_MIPLVLS__SHIFT) & A4XX_TEX_CONST_0_MIPLVLS__MASK;
3963 }
3964 #define A4XX_TEX_CONST_0_FMT__MASK                              0x1fc00000
3965 #define A4XX_TEX_CONST_0_FMT__SHIFT                             22
3966 static inline uint32_t A4XX_TEX_CONST_0_FMT(enum a4xx_tex_fmt val)
3967 {
3968         return ((val) << A4XX_TEX_CONST_0_FMT__SHIFT) & A4XX_TEX_CONST_0_FMT__MASK;
3969 }
3970 #define A4XX_TEX_CONST_0_TYPE__MASK                             0x60000000
3971 #define A4XX_TEX_CONST_0_TYPE__SHIFT                            29
3972 static inline uint32_t A4XX_TEX_CONST_0_TYPE(enum a4xx_tex_type val)
3973 {
3974         return ((val) << A4XX_TEX_CONST_0_TYPE__SHIFT) & A4XX_TEX_CONST_0_TYPE__MASK;
3975 }
3976
3977 #define REG_A4XX_TEX_CONST_1                                    0x00000001
3978 #define A4XX_TEX_CONST_1_HEIGHT__MASK                           0x00007fff
3979 #define A4XX_TEX_CONST_1_HEIGHT__SHIFT                          0
3980 static inline uint32_t A4XX_TEX_CONST_1_HEIGHT(uint32_t val)
3981 {
3982         return ((val) << A4XX_TEX_CONST_1_HEIGHT__SHIFT) & A4XX_TEX_CONST_1_HEIGHT__MASK;
3983 }
3984 #define A4XX_TEX_CONST_1_WIDTH__MASK                            0x3fff8000
3985 #define A4XX_TEX_CONST_1_WIDTH__SHIFT                           15
3986 static inline uint32_t A4XX_TEX_CONST_1_WIDTH(uint32_t val)
3987 {
3988         return ((val) << A4XX_TEX_CONST_1_WIDTH__SHIFT) & A4XX_TEX_CONST_1_WIDTH__MASK;
3989 }
3990
3991 #define REG_A4XX_TEX_CONST_2                                    0x00000002
3992 #define A4XX_TEX_CONST_2_FETCHSIZE__MASK                        0x0000000f
3993 #define A4XX_TEX_CONST_2_FETCHSIZE__SHIFT                       0
3994 static inline uint32_t A4XX_TEX_CONST_2_FETCHSIZE(enum a4xx_tex_fetchsize val)
3995 {
3996         return ((val) << A4XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A4XX_TEX_CONST_2_FETCHSIZE__MASK;
3997 }
3998 #define A4XX_TEX_CONST_2_PITCH__MASK                            0x3ffffe00
3999 #define A4XX_TEX_CONST_2_PITCH__SHIFT                           9
4000 static inline uint32_t A4XX_TEX_CONST_2_PITCH(uint32_t val)
4001 {
4002         return ((val) << A4XX_TEX_CONST_2_PITCH__SHIFT) & A4XX_TEX_CONST_2_PITCH__MASK;
4003 }
4004 #define A4XX_TEX_CONST_2_SWAP__MASK                             0xc0000000
4005 #define A4XX_TEX_CONST_2_SWAP__SHIFT                            30
4006 static inline uint32_t A4XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val)
4007 {
4008         return ((val) << A4XX_TEX_CONST_2_SWAP__SHIFT) & A4XX_TEX_CONST_2_SWAP__MASK;
4009 }
4010
4011 #define REG_A4XX_TEX_CONST_3                                    0x00000003
4012 #define A4XX_TEX_CONST_3_LAYERSZ__MASK                          0x00003fff
4013 #define A4XX_TEX_CONST_3_LAYERSZ__SHIFT                         0
4014 static inline uint32_t A4XX_TEX_CONST_3_LAYERSZ(uint32_t val)
4015 {
4016         return ((val >> 12) << A4XX_TEX_CONST_3_LAYERSZ__SHIFT) & A4XX_TEX_CONST_3_LAYERSZ__MASK;
4017 }
4018 #define A4XX_TEX_CONST_3_DEPTH__MASK                            0x7ffc0000
4019 #define A4XX_TEX_CONST_3_DEPTH__SHIFT                           18
4020 static inline uint32_t A4XX_TEX_CONST_3_DEPTH(uint32_t val)
4021 {
4022         return ((val) << A4XX_TEX_CONST_3_DEPTH__SHIFT) & A4XX_TEX_CONST_3_DEPTH__MASK;
4023 }
4024
4025 #define REG_A4XX_TEX_CONST_4                                    0x00000004
4026 #define A4XX_TEX_CONST_4_LAYERSZ__MASK                          0x0000000f
4027 #define A4XX_TEX_CONST_4_LAYERSZ__SHIFT                         0
4028 static inline uint32_t A4XX_TEX_CONST_4_LAYERSZ(uint32_t val)
4029 {
4030         return ((val >> 12) << A4XX_TEX_CONST_4_LAYERSZ__SHIFT) & A4XX_TEX_CONST_4_LAYERSZ__MASK;
4031 }
4032 #define A4XX_TEX_CONST_4_BASE__MASK                             0xffffffe0
4033 #define A4XX_TEX_CONST_4_BASE__SHIFT                            5
4034 static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val)
4035 {
4036         return ((val >> 5) << A4XX_TEX_CONST_4_BASE__SHIFT) & A4XX_TEX_CONST_4_BASE__MASK;
4037 }
4038
4039 #define REG_A4XX_TEX_CONST_5                                    0x00000005
4040
4041 #define REG_A4XX_TEX_CONST_6                                    0x00000006
4042
4043 #define REG_A4XX_TEX_CONST_7                                    0x00000007
4044
4045
4046 #endif /* A4XX_XML */