src/gallium/drivers/radeonsi/si_compute.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "tgsi/tgsi_parse.h"
  26 #include "util/u_memory.h"
  27 #include "util/u_upload_mgr.h"
  28 #include "radeon/radeon_elf_util.h"
  29
  30 #include "amd_kernel_code_t.h"
  31 #include "radeon/r600_cs.h"
  32 #include "si_pipe.h"
  33 #include "sid.h"
  34
  35 #define MAX_GLOBAL_BUFFERS 20
  36
  37 struct si_compute {
  38         unsigned ir_type;
  39         unsigned local_size;
  40         unsigned private_size;
  41         unsigned input_size;
  42         struct si_shader shader;
  43
  44         struct pipe_resource *global_buffers[MAX_GLOBAL_BUFFERS];
  45         unsigned use_code_object_v2 : 1;
  46         unsigned variable_group_size : 1;
  47 };
  48
  49 struct dispatch_packet {
  50         uint16_t header;
  51         uint16_t setup;
  52         uint16_t workgroup_size_x;
  53         uint16_t workgroup_size_y;
  54         uint16_t workgroup_size_z;
  55         uint16_t reserved0;
  56         uint32_t grid_size_x;
  57         uint32_t grid_size_y;
  58         uint32_t grid_size_z;
  59         uint32_t private_segment_size;
  60         uint32_t group_segment_size;
  61         uint64_t kernel_object;
  62         uint64_t kernarg_address;
  63         uint64_t reserved2;
  64 };
  65
  66 static const amd_kernel_code_t *si_compute_get_code_object(
  67         const struct si_compute *program,
  68         uint64_t symbol_offset)
  69 {
  70         if (!program->use_code_object_v2) {
  71                 return NULL;
  72         }
  73         return (const amd_kernel_code_t*)
  74                 (program->shader.binary.code + symbol_offset);
  75 }
  76
  77 static void code_object_to_config(const amd_kernel_code_t *code_object,
  78                                   struct si_shader_config *out_config) {
  79
  80         uint32_t rsrc1 = code_object->compute_pgm_resource_registers;
  81         uint32_t rsrc2 = code_object->compute_pgm_resource_registers >> 32;
  82         out_config->num_sgprs = code_object->wavefront_sgpr_count;
  83         out_config->num_vgprs = code_object->workitem_vgpr_count;
  84         out_config->float_mode = G_00B028_FLOAT_MODE(rsrc1);
  85         out_config->rsrc1 = rsrc1;
  86         out_config->lds_size = MAX2(out_config->lds_size, G_00B84C_LDS_SIZE(rsrc2));
  87         out_config->rsrc2 = rsrc2;
  88         out_config->scratch_bytes_per_wave =
  89                 align(code_object->workitem_private_segment_byte_size * 64, 1024);
  90 }
  91
  92 static void *si_create_compute_state(
  93         struct pipe_context *ctx,
  94         const struct pipe_compute_state *cso)
  95 {
  96         struct si_context *sctx = (struct si_context *)ctx;
  97         struct si_screen *sscreen = (struct si_screen *)ctx->screen;
  98         struct si_compute *program = CALLOC_STRUCT(si_compute);
  99         struct si_shader *shader = &program->shader;
 100
 101
 102         program->ir_type = cso->ir_type;
 103         program->local_size = cso->req_local_mem;
 104         program->private_size = cso->req_private_mem;
 105         program->input_size = cso->req_input_mem;
 106         program->use_code_object_v2 = HAVE_LLVM >= 0x0400 &&
 107                                         cso->ir_type == PIPE_SHADER_IR_NATIVE;
 108
 109
 110         if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
 111                 struct si_shader_selector sel;
 112                 bool scratch_enabled;
 113
 114                 memset(&sel, 0, sizeof(sel));
 115
 116                 sel.tokens = tgsi_dup_tokens(cso->prog);
 117                 if (!sel.tokens) {
 118                         FREE(program);
 119                         return NULL;
 120                 }
 121
 122                 tgsi_scan_shader(cso->prog, &sel.info);
 123                 sel.type = PIPE_SHADER_COMPUTE;
 124                 sel.local_size = cso->req_local_mem;
 125
 126                 p_atomic_inc(&sscreen->b.num_shaders_created);
 127
 128                 program->shader.selector = &sel;
 129
 130                 if (si_shader_create(sscreen, sctx->tm, &program->shader,
 131                                      &sctx->b.debug)) {
 132                         FREE(sel.tokens);
 133                         FREE(program);
 134                         return NULL;
 135                 }
 136
 137                 scratch_enabled = shader->config.scratch_bytes_per_wave > 0;
 138
 139                 shader->config.rsrc1 =
 140                            S_00B848_VGPRS((shader->config.num_vgprs - 1) / 4) |
 141                            S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8) |
 142                            S_00B848_DX10_CLAMP(1) |
 143                            S_00B848_FLOAT_MODE(shader->config.float_mode);
 144
 145                 shader->config.rsrc2 = S_00B84C_USER_SGPR(SI_CS_NUM_USER_SGPR) |
 146                            S_00B84C_SCRATCH_EN(scratch_enabled) |
 147                            S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
 148                            S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
 149                            S_00B84C_LDS_SIZE(shader->config.lds_size);
 150
 151                 program->variable_group_size =
 152                         sel.info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0;
 153
 154                 FREE(sel.tokens);
 155                 program->shader.selector = NULL;
 156         } else {
 157                 const struct pipe_llvm_program_header *header;
 158                 const char *code;
 159                 header = cso->prog;
 160                 code = cso->prog + sizeof(struct pipe_llvm_program_header);
 161
 162                 radeon_elf_read(code, header->num_bytes, &program->shader.binary);
 163                 if (program->use_code_object_v2) {
 164                         const amd_kernel_code_t *code_object =
 165                                 si_compute_get_code_object(program, 0);
 166                         code_object_to_config(code_object, &program->shader.config);
 167                 } else {
 168                         si_shader_binary_read_config(&program->shader.binary,
 169                                      &program->shader.config, 0);
 170                 }
 171                 si_shader_dump(sctx->screen, &program->shader, &sctx->b.debug,
 172                                PIPE_SHADER_COMPUTE, stderr);
 173                 si_shader_binary_upload(sctx->screen, &program->shader);
 174         }
 175
 176         return program;
 177 }
 178
 179 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
 180 {
 181         struct si_context *sctx = (struct si_context*)ctx;
 182         sctx->cs_shader_state.program = (struct si_compute*)state;
 183 }
 184
 185 static void si_set_global_binding(
 186         struct pipe_context *ctx, unsigned first, unsigned n,
 187         struct pipe_resource **resources,
 188         uint32_t **handles)
 189 {
 190         unsigned i;
 191         struct si_context *sctx = (struct si_context*)ctx;
 192         struct si_compute *program = sctx->cs_shader_state.program;
 193
 194         if (!resources) {
 195                 for (i = first; i < first + n; i++) {
 196                         pipe_resource_reference(&program->global_buffers[i], NULL);
 197                 }
 198                 return;
 199         }
 200
 201         for (i = first; i < first + n; i++) {
 202                 uint64_t va;
 203                 uint32_t offset;
 204                 pipe_resource_reference(&program->global_buffers[i], resources[i]);
 205                 va = r600_resource(resources[i])->gpu_address;
 206                 offset = util_le32_to_cpu(*handles[i]);
 207                 va += offset;
 208                 va = util_cpu_to_le64(va);
 209                 memcpy(handles[i], &va, sizeof(va));
 210         }
 211 }
 212
 213 static void si_initialize_compute(struct si_context *sctx)
 214 {
 215         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 216         uint64_t bc_va;
 217
 218         radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
 219         radeon_emit(cs, 0);
 220         radeon_emit(cs, 0);
 221         radeon_emit(cs, 0);
 222
 223         radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
 224         /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
 225         radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
 226         radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
 227
 228         if (sctx->b.chip_class >= CIK) {
 229                 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
 230                 radeon_set_sh_reg_seq(cs,
 231                                      R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
 232                 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
 233                                 S_00B864_SH1_CU_EN(0xffff));
 234                 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
 235                                 S_00B868_SH1_CU_EN(0xffff));
 236         }
 237
 238         /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
 239          * and is now per pipe, so it should be handled in the
 240          * kernel if we want to use something other than the default value,
 241          * which is now 0x22f.
 242          */
 243         if (sctx->b.chip_class <= SI) {
 244                 /* XXX: This should be:
 245                  * (number of compute units) * 4 * (waves per simd) - 1 */
 246
 247                 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
 248                                   0x190 /* Default value */);
 249         }
 250
 251         /* Set the pointer to border colors. */
 252         bc_va = sctx->border_color_buffer->gpu_address;
 253
 254         if (sctx->b.chip_class >= CIK) {
 255                 radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2);
 256                 radeon_emit(cs, bc_va >> 8);  /* R_030E00_TA_CS_BC_BASE_ADDR */
 257                 radeon_emit(cs, bc_va >> 40); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
 258         } else {
 259                 if (sctx->screen->b.info.drm_major == 3 ||
 260                     (sctx->screen->b.info.drm_major == 2 &&
 261                      sctx->screen->b.info.drm_minor >= 48)) {
 262                         radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR,
 263                                               bc_va >> 8);
 264                 }
 265         }
 266
 267         sctx->cs_shader_state.emitted_program = NULL;
 268         sctx->cs_shader_state.initialized = true;
 269 }
 270
 271 static bool si_setup_compute_scratch_buffer(struct si_context *sctx,
 272                                             struct si_shader *shader,
 273                                             struct si_shader_config *config)
 274 {
 275         uint64_t scratch_bo_size, scratch_needed;
 276         scratch_bo_size = 0;
 277         scratch_needed = config->scratch_bytes_per_wave * sctx->scratch_waves;
 278         if (sctx->compute_scratch_buffer)
 279                 scratch_bo_size = sctx->compute_scratch_buffer->b.b.width0;
 280
 281         if (scratch_bo_size < scratch_needed) {
 282                 r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
 283
 284                 sctx->compute_scratch_buffer = (struct r600_resource*)
 285                         pipe_buffer_create(&sctx->screen->b.b, 0,
 286                                            PIPE_USAGE_DEFAULT, scratch_needed);
 287
 288                 if (!sctx->compute_scratch_buffer)
 289                         return false;
 290         }
 291
 292         if (sctx->compute_scratch_buffer != shader->scratch_bo && scratch_needed) {
 293                 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
 294
 295                 si_shader_apply_scratch_relocs(sctx, shader, config, scratch_va);
 296
 297                 if (si_shader_binary_upload(sctx->screen, shader))
 298                         return false;
 299
 300                 r600_resource_reference(&shader->scratch_bo,
 301                                         sctx->compute_scratch_buffer);
 302         }
 303
 304         return true;
 305 }
 306
 307 static bool si_switch_compute_shader(struct si_context *sctx,
 308                                      struct si_compute *program,
 309                                      struct si_shader *shader,
 310                                      const amd_kernel_code_t *code_object,
 311                                      unsigned offset)
 312 {
 313         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 314         struct si_shader_config inline_config = {0};
 315         struct si_shader_config *config;
 316         uint64_t shader_va;
 317
 318         if (sctx->cs_shader_state.emitted_program == program &&
 319             sctx->cs_shader_state.offset == offset)
 320                 return true;
 321
 322         if (program->ir_type == PIPE_SHADER_IR_TGSI) {
 323                 config = &shader->config;
 324         } else {
 325                 unsigned lds_blocks;
 326
 327                 config = &inline_config;
 328                 if (code_object) {
 329                         code_object_to_config(code_object, config);
 330                 } else {
 331                         si_shader_binary_read_config(&shader->binary, config, offset);
 332                 }
 333
 334                 lds_blocks = config->lds_size;
 335                 /* XXX: We are over allocating LDS.  For SI, the shader reports
 336                 * LDS in blocks of 256 bytes, so if there are 4 bytes lds
 337                 * allocated in the shader and 4 bytes allocated by the state
 338                 * tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
 339                 */
 340                 if (sctx->b.chip_class <= SI) {
 341                         lds_blocks += align(program->local_size, 256) >> 8;
 342                 } else {
 343                         lds_blocks += align(program->local_size, 512) >> 9;
 344                 }
 345
 346                 assert(lds_blocks <= 0xFF);
 347
 348                 config->rsrc2 &= C_00B84C_LDS_SIZE;
 349                 config->rsrc2 |=  S_00B84C_LDS_SIZE(lds_blocks);
 350         }
 351
 352         if (!si_setup_compute_scratch_buffer(sctx, shader, config))
 353                 return false;
 354
 355         if (shader->scratch_bo) {
 356                 COMPUTE_DBG(sctx->screen, "Waves: %u; Scratch per wave: %u bytes; "
 357                             "Total Scratch: %u bytes\n", sctx->scratch_waves,
 358                             config->scratch_bytes_per_wave,
 359                             config->scratch_bytes_per_wave *
 360                             sctx->scratch_waves);
 361
 362                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 363                               shader->scratch_bo, RADEON_USAGE_READWRITE,
 364                               RADEON_PRIO_SCRATCH_BUFFER);
 365         }
 366
 367         shader_va = shader->bo->gpu_address + offset;
 368         if (program->use_code_object_v2) {
 369                 /* Shader code is placed after the amd_kernel_code_t
 370                  * struct. */
 371                 shader_va += sizeof(amd_kernel_code_t);
 372         }
 373
 374         radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, shader->bo,
 375                                   RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
 376
 377         radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
 378         radeon_emit(cs, shader_va >> 8);
 379         radeon_emit(cs, shader_va >> 40);
 380
 381         radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
 382         radeon_emit(cs, config->rsrc1);
 383         radeon_emit(cs, config->rsrc2);
 384
 385         COMPUTE_DBG(sctx->screen, "COMPUTE_PGM_RSRC1: 0x%08x "
 386                 "COMPUTE_PGM_RSRC2: 0x%08x\n", config->rsrc1, config->rsrc2);
 387
 388         radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
 389                   S_00B860_WAVES(sctx->scratch_waves)
 390                      | S_00B860_WAVESIZE(config->scratch_bytes_per_wave >> 10));
 391
 392         sctx->cs_shader_state.emitted_program = program;
 393         sctx->cs_shader_state.offset = offset;
 394         sctx->cs_shader_state.uses_scratch =
 395                 config->scratch_bytes_per_wave != 0;
 396
 397         return true;
 398 }
 399
 400 static void setup_scratch_rsrc_user_sgprs(struct si_context *sctx,
 401                                           const amd_kernel_code_t *code_object,
 402                                           unsigned user_sgpr)
 403 {
 404         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 405         uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
 406
 407         unsigned max_private_element_size = AMD_HSA_BITS_GET(
 408                         code_object->code_properties,
 409                         AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE);
 410
 411         uint32_t scratch_dword0 = scratch_va & 0xffffffff;
 412         uint32_t scratch_dword1 =
 413                 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
 414                 S_008F04_SWIZZLE_ENABLE(1);
 415
 416         /* Disable address clamping */
 417         uint32_t scratch_dword2 = 0xffffffff;
 418         uint32_t scratch_dword3 =
 419                 S_008F0C_ELEMENT_SIZE(max_private_element_size) |
 420                 S_008F0C_INDEX_STRIDE(3) |
 421                 S_008F0C_ADD_TID_ENABLE(1);
 422
 423
 424         if (sctx->screen->b.chip_class < VI) {
 425                 /* BUF_DATA_FORMAT is ignored, but it cannot be
 426                    BUF_DATA_FORMAT_INVALID. */
 427                 scratch_dword3 |=
 428                         S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8);
 429         }
 430
 431         radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
 432                                                         (user_sgpr * 4), 4);
 433         radeon_emit(cs, scratch_dword0);
 434         radeon_emit(cs, scratch_dword1);
 435         radeon_emit(cs, scratch_dword2);
 436         radeon_emit(cs, scratch_dword3);
 437 }
 438
 439 static void si_setup_user_sgprs_co_v2(struct si_context *sctx,
 440                                       const amd_kernel_code_t *code_object,
 441                                       const struct pipe_grid_info *info,
 442                                       uint64_t kernel_args_va)
 443 {
 444         struct si_compute *program = sctx->cs_shader_state.program;
 445         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 446
 447         static const enum amd_code_property_mask_t workgroup_count_masks [] = {
 448                 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X,
 449                 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y,
 450                 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z
 451         };
 452
 453         unsigned i, user_sgpr = 0;
 454         if (AMD_HSA_BITS_GET(code_object->code_properties,
 455                         AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER)) {
 456                 if (code_object->workitem_private_segment_byte_size > 0) {
 457                         setup_scratch_rsrc_user_sgprs(sctx, code_object,
 458                                                                 user_sgpr);
 459                 }
 460                 user_sgpr += 4;
 461         }
 462
 463         if (AMD_HSA_BITS_GET(code_object->code_properties,
 464                         AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR)) {
 465                 struct dispatch_packet dispatch;
 466                 unsigned dispatch_offset;
 467                 struct r600_resource *dispatch_buf = NULL;
 468                 uint64_t dispatch_va;
 469
 470                 /* Upload dispatch ptr */
 471                 memset(&dispatch, 0, sizeof(dispatch));
 472
 473                 dispatch.workgroup_size_x = info->block[0];
 474                 dispatch.workgroup_size_y = info->block[1];
 475                 dispatch.workgroup_size_z = info->block[2];
 476
 477                 dispatch.grid_size_x = info->grid[0] * info->block[0];
 478                 dispatch.grid_size_y = info->grid[1] * info->block[1];
 479                 dispatch.grid_size_z = info->grid[2] * info->block[2];
 480
 481                 dispatch.private_segment_size = program->private_size;
 482                 dispatch.group_segment_size = program->local_size;
 483
 484                 dispatch.kernarg_address = kernel_args_va;
 485
 486                 u_upload_data(sctx->b.uploader, 0, sizeof(dispatch), 256,
 487                                 &dispatch, &dispatch_offset,
 488                                 (struct pipe_resource**)&dispatch_buf);
 489
 490                 if (!dispatch_buf) {
 491                         fprintf(stderr, "Error: Failed to allocate dispatch "
 492                                         "packet.");
 493                 }
 494                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, dispatch_buf,
 495                                   RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
 496
 497                 dispatch_va = dispatch_buf->gpu_address + dispatch_offset;
 498
 499                 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
 500                                                         (user_sgpr * 4), 2);
 501                 radeon_emit(cs, dispatch_va);
 502                 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(dispatch_va >> 32) |
 503                                 S_008F04_STRIDE(0));
 504
 505                 r600_resource_reference(&dispatch_buf, NULL);
 506                 user_sgpr += 2;
 507         }
 508
 509         if (AMD_HSA_BITS_GET(code_object->code_properties,
 510                         AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR)) {
 511                 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
 512                                                         (user_sgpr * 4), 2);
 513                 radeon_emit(cs, kernel_args_va);
 514                 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
 515                                 S_008F04_STRIDE(0));
 516                 user_sgpr += 2;
 517         }
 518
 519         for (i = 0; i < 3 && user_sgpr < 16; i++) {
 520                 if (code_object->code_properties & workgroup_count_masks[i]) {
 521                         radeon_set_sh_reg_seq(cs,
 522                                 R_00B900_COMPUTE_USER_DATA_0 +
 523                                 (user_sgpr * 4), 1);
 524                         radeon_emit(cs, info->grid[i]);
 525                         user_sgpr += 1;
 526                 }
 527         }
 528 }
 529
 530 static void si_upload_compute_input(struct si_context *sctx,
 531                                     const amd_kernel_code_t *code_object,
 532                                     const struct pipe_grid_info *info)
 533 {
 534         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 535         struct si_compute *program = sctx->cs_shader_state.program;
 536         struct r600_resource *input_buffer = NULL;
 537         unsigned kernel_args_size;
 538         unsigned num_work_size_bytes = program->use_code_object_v2 ? 0 : 36;
 539         uint32_t kernel_args_offset = 0;
 540         uint32_t *kernel_args;
 541         void *kernel_args_ptr;
 542         uint64_t kernel_args_va;
 543         unsigned i;
 544
 545         /* The extra num_work_size_bytes are for work group / work item size information */
 546         kernel_args_size = program->input_size + num_work_size_bytes;
 547
 548         u_upload_alloc(sctx->b.uploader, 0, kernel_args_size, 256,
 549                        &kernel_args_offset,
 550                        (struct pipe_resource**)&input_buffer, &kernel_args_ptr);
 551
 552         kernel_args = (uint32_t*)kernel_args_ptr;
 553         kernel_args_va = input_buffer->gpu_address + kernel_args_offset;
 554
 555         if (!code_object) {
 556                 for (i = 0; i < 3; i++) {
 557                         kernel_args[i] = info->grid[i];
 558                         kernel_args[i + 3] = info->grid[i] * info->block[i];
 559                         kernel_args[i + 6] = info->block[i];
 560                 }
 561         }
 562
 563         memcpy(kernel_args + (num_work_size_bytes / 4), info->input,
 564                program->input_size);
 565
 566
 567         for (i = 0; i < (kernel_args_size / 4); i++) {
 568                 COMPUTE_DBG(sctx->screen, "input %u : %u\n", i,
 569                         kernel_args[i]);
 570         }
 571
 572
 573         radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, input_buffer,
 574                                   RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
 575
 576         if (code_object) {
 577                 si_setup_user_sgprs_co_v2(sctx, code_object, info, kernel_args_va);
 578         } else {
 579                 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
 580                 radeon_emit(cs, kernel_args_va);
 581                 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
 582                                 S_008F04_STRIDE(0));
 583         }
 584
 585         r600_resource_reference(&input_buffer, NULL);
 586 }
 587
 588 static void si_setup_tgsi_grid(struct si_context *sctx,
 589                                 const struct pipe_grid_info *info)
 590 {
 591         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 592         unsigned grid_size_reg = R_00B900_COMPUTE_USER_DATA_0 +
 593                                   4 * SI_SGPR_GRID_SIZE;
 594
 595         if (info->indirect) {
 596                 uint64_t base_va = r600_resource(info->indirect)->gpu_address;
 597                 uint64_t va = base_va + info->indirect_offset;
 598                 int i;
 599
 600                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 601                                  (struct r600_resource *)info->indirect,
 602                                  RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
 603
 604                 for (i = 0; i < 3; ++i) {
 605                         radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
 606                         radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
 607                                         COPY_DATA_DST_SEL(COPY_DATA_REG));
 608                         radeon_emit(cs, (va +  4 * i));
 609                         radeon_emit(cs, (va + 4 * i) >> 32);
 610                         radeon_emit(cs, (grid_size_reg >> 2) + i);
 611                         radeon_emit(cs, 0);
 612                 }
 613         } else {
 614                 struct si_compute *program = sctx->cs_shader_state.program;
 615
 616                 radeon_set_sh_reg_seq(cs, grid_size_reg, program->variable_group_size ? 6 : 3);
 617                 radeon_emit(cs, info->grid[0]);
 618                 radeon_emit(cs, info->grid[1]);
 619                 radeon_emit(cs, info->grid[2]);
 620                 if (program->variable_group_size) {
 621                         radeon_emit(cs, info->block[0]);
 622                         radeon_emit(cs, info->block[1]);
 623                         radeon_emit(cs, info->block[2]);
 624                 }
 625         }
 626 }
 627
 628 static void si_emit_dispatch_packets(struct si_context *sctx,
 629                                      const struct pipe_grid_info *info)
 630 {
 631         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 632         bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
 633         unsigned waves_per_threadgroup =
 634                 DIV_ROUND_UP(info->block[0] * info->block[1] * info->block[2], 64);
 635
 636         radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
 637                           S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0));
 638
 639         radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
 640         radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]));
 641         radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]));
 642         radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]));
 643
 644         if (info->indirect) {
 645                 uint64_t base_va = r600_resource(info->indirect)->gpu_address;
 646
 647                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 648                                  (struct r600_resource *)info->indirect,
 649                                  RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
 650
 651                 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
 652                                 PKT3_SHADER_TYPE_S(1));
 653                 radeon_emit(cs, 1);
 654                 radeon_emit(cs, base_va);
 655                 radeon_emit(cs, base_va >> 32);
 656
 657                 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, render_cond_bit) |
 658                                 PKT3_SHADER_TYPE_S(1));
 659                 radeon_emit(cs, info->indirect_offset);
 660                 radeon_emit(cs, 1);
 661         } else {
 662                 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, render_cond_bit) |
 663                                 PKT3_SHADER_TYPE_S(1));
 664                 radeon_emit(cs, info->grid[0]);
 665                 radeon_emit(cs, info->grid[1]);
 666                 radeon_emit(cs, info->grid[2]);
 667                 radeon_emit(cs, 1);
 668         }
 669 }
 670
 671
 672 static void si_launch_grid(
 673                 struct pipe_context *ctx, const struct pipe_grid_info *info)
 674 {
 675         struct si_context *sctx = (struct si_context*)ctx;
 676         struct si_compute *program = sctx->cs_shader_state.program;
 677         const amd_kernel_code_t *code_object =
 678                 si_compute_get_code_object(program, info->pc);
 679         int i;
 680         /* HW bug workaround when CS threadgroups > 256 threads and async
 681          * compute isn't used, i.e. only one compute job can run at a time.
 682          * If async compute is possible, the threadgroup size must be limited
 683          * to 256 threads on all queues to avoid the bug.
 684          * Only SI and certain CIK chips are affected.
 685          */
 686         bool cs_regalloc_hang =
 687                 (sctx->b.chip_class == SI ||
 688                  sctx->b.family == CHIP_BONAIRE ||
 689                  sctx->b.family == CHIP_KABINI) &&
 690                 info->block[0] * info->block[1] * info->block[2] > 256;
 691
 692         if (cs_regalloc_hang)
 693                 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
 694                                  SI_CONTEXT_CS_PARTIAL_FLUSH;
 695
 696         si_decompress_compute_textures(sctx);
 697
 698         /* Add buffer sizes for memory checking in need_cs_space. */
 699         r600_context_add_resource_size(ctx, &program->shader.bo->b.b);
 700         /* TODO: add the scratch buffer */
 701
 702         if (info->indirect) {
 703                 r600_context_add_resource_size(ctx, info->indirect);
 704
 705                 /* The hw doesn't read the indirect buffer via TC L2. */
 706                 if (r600_resource(info->indirect)->TC_L2_dirty) {
 707                         sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
 708                         r600_resource(info->indirect)->TC_L2_dirty = false;
 709                 }
 710         }
 711
 712         si_need_cs_space(sctx);
 713
 714         if (!sctx->cs_shader_state.initialized)
 715                 si_initialize_compute(sctx);
 716
 717         if (sctx->b.flags)
 718                 si_emit_cache_flush(sctx);
 719
 720         if (!si_switch_compute_shader(sctx, program, &program->shader,
 721                                         code_object, info->pc))
 722                 return;
 723
 724         si_upload_compute_shader_descriptors(sctx);
 725         si_emit_compute_shader_userdata(sctx);
 726
 727         if (si_is_atom_dirty(sctx, sctx->atoms.s.render_cond)) {
 728                 sctx->atoms.s.render_cond->emit(&sctx->b,
 729                                                 sctx->atoms.s.render_cond);
 730                 si_set_atom_dirty(sctx, sctx->atoms.s.render_cond, false);
 731         }
 732
 733         if (program->input_size || program->ir_type == PIPE_SHADER_IR_NATIVE)
 734                 si_upload_compute_input(sctx, code_object, info);
 735
 736         /* Global buffers */
 737         for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) {
 738                 struct r600_resource *buffer =
 739                                 (struct r600_resource*)program->global_buffers[i];
 740                 if (!buffer) {
 741                         continue;
 742                 }
 743                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, buffer,
 744                                           RADEON_USAGE_READWRITE,
 745                                           RADEON_PRIO_COMPUTE_GLOBAL);
 746         }
 747
 748         if (program->ir_type == PIPE_SHADER_IR_TGSI)
 749                 si_setup_tgsi_grid(sctx, info);
 750
 751         si_ce_pre_draw_synchronization(sctx);
 752
 753         si_emit_dispatch_packets(sctx, info);
 754
 755         si_ce_post_draw_synchronization(sctx);
 756
 757         sctx->compute_is_busy = true;
 758         sctx->b.num_compute_calls++;
 759         if (sctx->cs_shader_state.uses_scratch)
 760                 sctx->b.num_spill_compute_calls++;
 761
 762         if (cs_regalloc_hang)
 763                 sctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
 764 }
 765
 766
 767 static void si_delete_compute_state(struct pipe_context *ctx, void* state){
 768         struct si_compute *program = (struct si_compute *)state;
 769         struct si_context *sctx = (struct si_context*)ctx;
 770
 771         if (!state) {
 772                 return;
 773         }
 774
 775         if (program == sctx->cs_shader_state.program)
 776                 sctx->cs_shader_state.program = NULL;
 777
 778         if (program == sctx->cs_shader_state.emitted_program)
 779                 sctx->cs_shader_state.emitted_program = NULL;
 780
 781         si_shader_destroy(&program->shader);
 782         FREE(program);
 783 }
 784
 785 static void si_set_compute_resources(struct pipe_context * ctx_,
 786                 unsigned start, unsigned count,
 787                 struct pipe_surface ** surfaces) { }
 788
 789 void si_init_compute_functions(struct si_context *sctx)
 790 {
 791         sctx->b.b.create_compute_state = si_create_compute_state;
 792         sctx->b.b.delete_compute_state = si_delete_compute_state;
 793         sctx->b.b.bind_compute_state = si_bind_compute_state;
 794 /*       ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
 795         sctx->b.b.set_compute_resources = si_set_compute_resources;
 796         sctx->b.b.set_global_binding = si_set_global_binding;
 797         sctx->b.b.launch_grid = si_launch_grid;
 798 }