1 /**************************************************************************
3 * Copyright 2003 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include "main/mtypes.h"
30 #include "main/context.h"
31 #include "main/enums.h"
32 #include "main/colormac.h"
33 #include "main/fbobject.h"
35 #include "brw_context.h"
36 #include "brw_defines.h"
37 #include "intel_blit.h"
38 #include "intel_buffers.h"
39 #include "intel_fbo.h"
40 #include "intel_reg.h"
41 #include "intel_batchbuffer.h"
42 #include "intel_mipmap_tree.h"
44 #define FILE_DEBUG_FLAG DEBUG_BLIT
47 intel_miptree_set_alpha_to_one(struct brw_context *brw,
48 struct intel_mipmap_tree *mt,
49 int x, int y, int width, int height);
51 static GLuint translate_raster_op(GLenum logicop)
54 case GL_CLEAR: return 0x00;
55 case GL_AND: return 0x88;
56 case GL_AND_REVERSE: return 0x44;
57 case GL_COPY: return 0xCC;
58 case GL_AND_INVERTED: return 0x22;
59 case GL_NOOP: return 0xAA;
60 case GL_XOR: return 0x66;
61 case GL_OR: return 0xEE;
62 case GL_NOR: return 0x11;
63 case GL_EQUIV: return 0x99;
64 case GL_INVERT: return 0x55;
65 case GL_OR_REVERSE: return 0xDD;
66 case GL_COPY_INVERTED: return 0x33;
67 case GL_OR_INVERTED: return 0xBB;
68 case GL_NAND: return 0x77;
69 case GL_SET: return 0xFF;
88 unreachable("not reached");
93 * Emits the packet for switching the blitter from X to Y tiled or back.
95 * This has to be called in a single BEGIN_BATCH_BLT_TILED() /
96 * ADVANCE_BATCH_TILED(). This is because BCS_SWCTRL is saved and restored as
97 * part of the power context, not a render context, and if the batchbuffer was
98 * to get flushed between setting and blitting, or blitting and restoring, our
99 * tiling state would leak into other unsuspecting applications (like the X
103 set_blitter_tiling(struct brw_context *brw,
104 bool dst_y_tiled, bool src_y_tiled)
106 assert(brw->gen >= 6);
108 /* Idle the blitter before we update how tiling is interpreted. */
109 OUT_BATCH(MI_FLUSH_DW);
114 OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
115 OUT_BATCH(BCS_SWCTRL);
116 OUT_BATCH((BCS_SWCTRL_DST_Y | BCS_SWCTRL_SRC_Y) << 16 |
117 (dst_y_tiled ? BCS_SWCTRL_DST_Y : 0) |
118 (src_y_tiled ? BCS_SWCTRL_SRC_Y : 0));
121 #define BEGIN_BATCH_BLT_TILED(n, dst_y_tiled, src_y_tiled) do { \
122 BEGIN_BATCH_BLT(n + ((dst_y_tiled || src_y_tiled) ? 14 : 0)); \
123 if (dst_y_tiled || src_y_tiled) \
124 set_blitter_tiling(brw, dst_y_tiled, src_y_tiled); \
127 #define ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled) do { \
128 if (dst_y_tiled || src_y_tiled) \
129 set_blitter_tiling(brw, false, false); \
134 blt_pitch(struct intel_mipmap_tree *mt)
136 int pitch = mt->pitch;
143 intel_miptree_blit_compatible_formats(mesa_format src, mesa_format dst)
145 /* The BLT doesn't handle sRGB conversion */
146 assert(src == _mesa_get_srgb_format_linear(src));
147 assert(dst == _mesa_get_srgb_format_linear(dst));
149 /* No swizzle or format conversions possible, except... */
153 /* ...we can either discard the alpha channel when going from A->X,
154 * or we can fill the alpha channel with 0xff when going from X->A
156 if (src == MESA_FORMAT_B8G8R8A8_UNORM || src == MESA_FORMAT_B8G8R8X8_UNORM)
157 return (dst == MESA_FORMAT_B8G8R8A8_UNORM ||
158 dst == MESA_FORMAT_B8G8R8X8_UNORM);
160 if (src == MESA_FORMAT_R8G8B8A8_UNORM || src == MESA_FORMAT_R8G8B8X8_UNORM)
161 return (dst == MESA_FORMAT_R8G8B8A8_UNORM ||
162 dst == MESA_FORMAT_R8G8B8X8_UNORM);
168 * Implements a rectangular block transfer (blit) of pixels between two
171 * Our blitter can operate on 1, 2, or 4-byte-per-pixel data, with generous,
172 * but limited, pitches and sizes allowed.
174 * The src/dst coordinates are relative to the given level/slice of the
177 * If @src_flip or @dst_flip is set, then the rectangle within that miptree
178 * will be inverted (including scanline order) when copying. This is common
179 * in GL when copying between window system and user-created
180 * renderbuffers/textures.
183 intel_miptree_blit(struct brw_context *brw,
184 struct intel_mipmap_tree *src_mt,
185 int src_level, int src_slice,
186 uint32_t src_x, uint32_t src_y, bool src_flip,
187 struct intel_mipmap_tree *dst_mt,
188 int dst_level, int dst_slice,
189 uint32_t dst_x, uint32_t dst_y, bool dst_flip,
190 uint32_t width, uint32_t height,
193 /* The blitter doesn't understand multisampling at all. */
194 if (src_mt->num_samples > 0 || dst_mt->num_samples > 0)
197 /* No sRGB decode or encode is done by the hardware blitter, which is
198 * consistent with what we want in the callers (glCopyTexSubImage(),
199 * glBlitFramebuffer(), texture validation, etc.).
201 mesa_format src_format = _mesa_get_srgb_format_linear(src_mt->format);
202 mesa_format dst_format = _mesa_get_srgb_format_linear(dst_mt->format);
204 /* The blitter doesn't support doing any format conversions. We do also
205 * support blitting ARGB8888 to XRGB8888 (trivial, the values dropped into
206 * the X channel don't matter), and XRGB8888 to ARGB8888 by setting the A
207 * channel to 1.0 at the end.
209 if (!intel_miptree_blit_compatible_formats(src_format, dst_format)) {
210 perf_debug("%s: Can't use hardware blitter from %s to %s, "
211 "falling back.\n", __func__,
212 _mesa_get_format_name(src_format),
213 _mesa_get_format_name(dst_format));
217 /* According to the Ivy Bridge PRM, Vol1 Part4, section 1.2.1.2 (Graphics
218 * Data Size Limitations):
220 * The BLT engine is capable of transferring very large quantities of
221 * graphics data. Any graphics data read from and written to the
222 * destination is permitted to represent a number of pixels that
223 * occupies up to 65,536 scan lines and up to 32,768 bytes per scan line
224 * at the destination. The maximum number of pixels that may be
225 * represented per scan line’s worth of graphics data depends on the
228 * Furthermore, intelEmitCopyBlit (which is called below) uses a signed
229 * 16-bit integer to represent buffer pitch, so it can only handle buffer
230 * pitches < 32k. However, the pitch is measured in bytes for linear buffers
231 * and dwords for tiled buffers.
233 * As a result of these two limitations, we can only use the blitter to do
234 * this copy when the miptree's pitch is less than 32k linear or 128k tiled.
236 if (blt_pitch(src_mt) >= 32768 || blt_pitch(dst_mt) >= 32768) {
237 perf_debug("Falling back due to >= 32k/128k pitch\n");
241 /* The blitter has no idea about HiZ or fast color clears, so we need to
242 * resolve the miptrees before we do anything.
244 intel_miptree_slice_resolve_depth(brw, src_mt, src_level, src_slice);
245 intel_miptree_slice_resolve_depth(brw, dst_mt, dst_level, dst_slice);
246 intel_miptree_resolve_color(brw, src_mt);
247 intel_miptree_resolve_color(brw, dst_mt);
250 src_y = minify(src_mt->physical_height0, src_level - src_mt->first_level) - src_y - height;
253 dst_y = minify(dst_mt->physical_height0, dst_level - dst_mt->first_level) - dst_y - height;
255 int src_pitch = src_mt->pitch;
256 if (src_flip != dst_flip)
257 src_pitch = -src_pitch;
259 uint32_t src_image_x, src_image_y, dst_image_x, dst_image_y;
260 intel_miptree_get_image_offset(src_mt, src_level, src_slice,
261 &src_image_x, &src_image_y);
262 intel_miptree_get_image_offset(dst_mt, dst_level, dst_slice,
263 &dst_image_x, &dst_image_y);
264 src_x += src_image_x;
265 src_y += src_image_y;
266 dst_x += dst_image_x;
267 dst_y += dst_image_y;
269 /* The blitter interprets the 16-bit destination x/y as a signed 16-bit
270 * value. The values we're working with are unsigned, so make sure we don't
273 if (src_x >= 32768 || src_y >= 32768 || dst_x >= 32768 || dst_y >= 32768) {
274 perf_debug("Falling back due to >=32k offset [src(%d, %d) dst(%d, %d)]\n",
275 src_x, src_y, dst_x, dst_y);
279 if (!intelEmitCopyBlit(brw,
282 src_mt->bo, src_mt->offset,
285 dst_mt->bo, dst_mt->offset,
294 /* XXX This could be done in a single pass using XY_FULL_MONO_PATTERN_BLT */
295 if (_mesa_get_format_bits(src_format, GL_ALPHA_BITS) == 0 &&
296 _mesa_get_format_bits(dst_format, GL_ALPHA_BITS) > 0) {
297 intel_miptree_set_alpha_to_one(brw, dst_mt,
306 alignment_valid(struct brw_context *brw, unsigned offset, uint32_t tiling)
308 /* Tiled buffers must be page-aligned (4K). */
309 if (tiling != I915_TILING_NONE)
310 return (offset & 4095) == 0;
312 /* On Gen8+, linear buffers must be cacheline-aligned. */
314 return (offset & 63) == 0;
322 intelEmitCopyBlit(struct brw_context *brw,
325 drm_intel_bo *src_buffer,
329 drm_intel_bo *dst_buffer,
332 GLshort src_x, GLshort src_y,
333 GLshort dst_x, GLshort dst_y,
334 GLshort w, GLshort h,
337 GLuint CMD, BR13, pass = 0;
338 int dst_y2 = dst_y + h;
339 int dst_x2 = dst_x + w;
340 drm_intel_bo *aper_array[3];
341 bool dst_y_tiled = dst_tiling == I915_TILING_Y;
342 bool src_y_tiled = src_tiling == I915_TILING_Y;
344 if (!alignment_valid(brw, dst_offset, dst_tiling))
346 if (!alignment_valid(brw, src_offset, src_tiling))
349 if ((dst_y_tiled || src_y_tiled) && brw->gen < 6)
352 assert(!dst_y_tiled || (dst_pitch % 128) == 0);
353 assert(!src_y_tiled || (src_pitch % 128) == 0);
355 /* do space check before going any further */
357 aper_array[0] = brw->batch.bo;
358 aper_array[1] = dst_buffer;
359 aper_array[2] = src_buffer;
361 if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) {
362 intel_batchbuffer_flush(brw);
371 unsigned length = brw->gen >= 8 ? 10 : 8;
373 intel_batchbuffer_require_space(brw, length * 4, BLT_RING);
374 DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
376 src_buffer, src_pitch, src_offset, src_x, src_y,
377 dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h);
379 /* Blit pitch must be dword-aligned. Otherwise, the hardware appears to drop
380 * the low bits. Offsets must be naturally aligned.
382 if (src_pitch % 4 != 0 || src_offset % cpp != 0 ||
383 dst_pitch % 4 != 0 || dst_offset % cpp != 0)
386 /* For big formats (such as floating point), do the copy using 16 or 32bpp
387 * and multiply the coordinates.
396 assert(cpp % 4 == 0);
404 BR13 = br13_for_cpp(cpp) | translate_raster_op(logic_op) << 16;
409 CMD = XY_SRC_COPY_BLT_CMD;
412 CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
418 if (dst_tiling != I915_TILING_NONE) {
422 if (src_tiling != I915_TILING_NONE) {
427 if (dst_y2 <= dst_y || dst_x2 <= dst_x) {
431 assert(dst_x < dst_x2);
432 assert(dst_y < dst_y2);
433 assert(src_offset + (src_y + h - 1) * abs(src_pitch) +
434 (w * cpp) <= src_buffer->size);
435 assert(dst_offset + (dst_y + h - 1) * abs(dst_pitch) +
436 (w * cpp) <= dst_buffer->size);
438 BEGIN_BATCH_BLT_TILED(length, dst_y_tiled, src_y_tiled);
439 OUT_BATCH(CMD | (length - 2));
440 OUT_BATCH(BR13 | (uint16_t)dst_pitch);
441 OUT_BATCH(SET_FIELD(dst_y, BLT_Y) | SET_FIELD(dst_x, BLT_X));
442 OUT_BATCH(SET_FIELD(dst_y2, BLT_Y) | SET_FIELD(dst_x2, BLT_X));
444 OUT_RELOC64(dst_buffer,
445 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
448 OUT_RELOC(dst_buffer,
449 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
452 OUT_BATCH(SET_FIELD(src_y, BLT_Y) | SET_FIELD(src_x, BLT_X));
453 OUT_BATCH((uint16_t)src_pitch);
455 OUT_RELOC64(src_buffer,
456 I915_GEM_DOMAIN_RENDER, 0,
459 OUT_RELOC(src_buffer,
460 I915_GEM_DOMAIN_RENDER, 0,
464 ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled);
466 intel_batchbuffer_emit_mi_flush(brw);
472 intelEmitImmediateColorExpandBlit(struct brw_context *brw,
474 GLubyte *src_bits, GLuint src_size,
477 drm_intel_bo *dst_buffer,
480 GLshort x, GLshort y,
481 GLshort w, GLshort h,
484 int dwords = ALIGN(src_size, 8) / 4;
485 uint32_t opcode, br13, blit_cmd;
487 if (dst_tiling != I915_TILING_NONE) {
488 if (dst_offset & 4095)
490 if (dst_tiling == I915_TILING_Y)
494 assert((logic_op >= GL_CLEAR) && (logic_op <= (GL_CLEAR + 0x0f)));
495 assert(dst_pitch > 0);
500 DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n",
502 dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords);
504 unsigned xy_setup_blt_length = brw->gen >= 8 ? 10 : 8;
505 intel_batchbuffer_require_space(brw, (xy_setup_blt_length * 4) +
506 (3 * 4) + dwords * 4, BLT_RING);
508 opcode = XY_SETUP_BLT_CMD;
510 opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
511 if (dst_tiling != I915_TILING_NONE) {
512 opcode |= XY_DST_TILED;
516 br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29);
517 br13 |= br13_for_cpp(cpp);
519 blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */
520 if (dst_tiling != I915_TILING_NONE)
521 blit_cmd |= XY_DST_TILED;
523 BEGIN_BATCH_BLT(xy_setup_blt_length + 3);
524 OUT_BATCH(opcode | (xy_setup_blt_length - 2));
526 OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
527 OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
529 OUT_RELOC64(dst_buffer,
530 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
533 OUT_RELOC(dst_buffer,
534 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
537 OUT_BATCH(0); /* bg */
538 OUT_BATCH(fg_color); /* fg */
539 OUT_BATCH(0); /* pattern base addr */
543 OUT_BATCH(blit_cmd | ((3 - 2) + dwords));
544 OUT_BATCH(SET_FIELD(y, BLT_Y) | SET_FIELD(x, BLT_X));
545 OUT_BATCH(SET_FIELD(y + h, BLT_Y) | SET_FIELD(x + w, BLT_X));
548 intel_batchbuffer_data(brw, src_bits, dwords * 4, BLT_RING);
550 intel_batchbuffer_emit_mi_flush(brw);
555 /* We don't have a memmove-type blit like some other hardware, so we'll do a
556 * rectangular blit covering a large space, then emit 1-scanline blit at the
557 * end to cover the last if we need.
560 intel_emit_linear_blit(struct brw_context *brw,
561 drm_intel_bo *dst_bo,
562 unsigned int dst_offset,
563 drm_intel_bo *src_bo,
564 unsigned int src_offset,
567 struct gl_context *ctx = &brw->ctx;
568 GLuint pitch, height;
569 int16_t src_x, dst_x;
572 /* The pitch given to the GPU must be DWORD aligned, and
573 * we want width to match pitch. Max width is (1 << 15 - 1),
574 * rounding that down to the nearest DWORD is 1 << 15 - 4
576 pitch = ROUND_DOWN_TO(MIN2(size, (1 << 15) - 1), 4);
577 height = (pitch == 0) ? 1 : size / pitch;
578 src_x = src_offset % 64;
579 dst_x = dst_offset % 64;
580 ok = intelEmitCopyBlit(brw, 1,
581 pitch, src_bo, src_offset - src_x, I915_TILING_NONE,
582 pitch, dst_bo, dst_offset - dst_x, I915_TILING_NONE,
583 src_x, 0, /* src x/y */
584 dst_x, 0, /* dst x/y */
585 pitch, height, /* w, h */
588 _mesa_problem(ctx, "Failed to linear blit %dx%d\n", pitch, height);
590 src_offset += pitch * height;
591 dst_offset += pitch * height;
592 src_x = src_offset % 64;
593 dst_x = dst_offset % 64;
594 size -= pitch * height;
595 assert (size < (1 << 15));
596 pitch = ALIGN(size, 4);
599 ok = intelEmitCopyBlit(brw, 1,
600 pitch, src_bo, src_offset - src_x, I915_TILING_NONE,
601 pitch, dst_bo, dst_offset - dst_x, I915_TILING_NONE,
602 src_x, 0, /* src x/y */
603 dst_x, 0, /* dst x/y */
607 _mesa_problem(ctx, "Failed to linear blit %dx%d\n", size, 1);
612 * Used to initialize the alpha value of an ARGB8888 miptree after copying
613 * into it from an XRGB8888 source.
615 * This is very common with glCopyTexImage2D(). Note that the coordinates are
616 * relative to the start of the miptree, not relative to a slice within the
620 intel_miptree_set_alpha_to_one(struct brw_context *brw,
621 struct intel_mipmap_tree *mt,
622 int x, int y, int width, int height)
626 drm_intel_bo *aper_array[2];
631 DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
632 __func__, mt->bo, pitch, x, y, width, height);
634 BR13 = br13_for_cpp(cpp) | 0xf0 << 16;
635 CMD = XY_COLOR_BLT_CMD;
636 CMD |= XY_BLT_WRITE_ALPHA;
638 if (mt->tiling != I915_TILING_NONE) {
644 /* do space check before going any further */
645 aper_array[0] = brw->batch.bo;
646 aper_array[1] = mt->bo;
648 if (drm_intel_bufmgr_check_aperture_space(aper_array,
649 ARRAY_SIZE(aper_array)) != 0) {
650 intel_batchbuffer_flush(brw);
653 unsigned length = brw->gen >= 8 ? 7 : 6;
654 bool dst_y_tiled = mt->tiling == I915_TILING_Y;
656 BEGIN_BATCH_BLT_TILED(length, dst_y_tiled, false);
657 OUT_BATCH(CMD | (length - 2));
659 OUT_BATCH(SET_FIELD(y, BLT_Y) | SET_FIELD(x, BLT_X));
660 OUT_BATCH(SET_FIELD(y + height, BLT_Y) | SET_FIELD(x + width, BLT_X));
663 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
667 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
670 OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
671 ADVANCE_BATCH_TILED(dst_y_tiled, false);
673 intel_batchbuffer_emit_mi_flush(brw);